CSE 370 Spring 2006 Introduction to Digital Design Lecture 12: Adders Last Lecture 1 PLAsand PALS: Today 1 Adders = bit full adder = Computes sum, carry-out ECarryin allows cascaded adders Binary full adder eat [sum adder | cout Full adder: Alternative Implementation = Multilevel logic Slower Less gates 2XORS, 2 ANDs, 1 OR ‘sum = (88) Cn out = ACin + 8Cin + AB = (2 ByCin + AB ae oo th tt HDs CETTE] ote cubpde. 6.4 °, Co T T sum, | sum, 1 éveton4-bit ripple-carry adder/subtractor = Circuit adds or subtracts 2s complement, A-8 =A +(-B)=A+B'+1 Problem: Ripple-carry delay = Carry propagation limits adder speed 2p, “{] Tea a . 7 hal ae : Uy sa exon f 7 (eed Bae (Pi oA ee yh fo oh ok no J ad Ie tetera eet Ripple-carry adder timing One solution: Carry lookahead diagram logic mCritical delay ‘= Compute all the carves in parallel Carry propagation T Detve cre fom the data inpts 1111 + 0001 = 10000 is worst case saangrcss [ENot from intermediate carries Use two-level logic E Compute all sums in parallel = Cascade simple adders to make large adders = Speed improvement 1 16-bit ripple-carry ~32 gate delays 16-bit cam-lookehead: ~8 gate delays = Issues ‘= Complex combinational logicFull adder again ad oe aj . yon Carry-lookahead logic 1 Cary generate: G = AB, "Generate cary when A= samy propagate: P, = Axor B ' Propagate carry.n to cary.out when (Axor B)= 4 s= Sum and Coutin ers of generate/propagate Axor B, x0r C, Bxor G, AB +O(A 10° B) GHOP, Carry-lookahead logic (cont'd) 1 Reexpress the cary lgicin tems of Gand P £O,=G,+2,0, EC)=G,+P/C,=6, +P,G #P.PIC EC;=G, +P:C,=G,+P.G, + P:P,G +P.PPLC EC,=G,+P\C, = G, +P\G: +P:P,G, +P,P.P\G, + PPP PCy '= Implement each carry equation with two-fevel logic = Derive intermediate results directly from inputs Rather than from carries Allows "sum" computations to proceed in parallel Implementing the carry- lookahead logic aay Lege ompleaty ° Soe uessns wl