IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 32, NO.
3, MARCH 1997
A Low Noise Readout Detector Circuit
for Nanoampere Sensor Applications
Donald C. Thelen, Jr. and Dahlon D. Chu
Abstract—A readout detector IC has been developed which is
capable of detecting nanoampere photo-current signals of interest
in a high (microampere) background illumination or dc noise
level (SNR = 80 dB). The readout detector sensor IC processes
transient signals of interest from a separate photo-diode pixel
array chip. Low noise signal conditioning, filtering, and signal
thresholding implement smart sensor detection of only “active
pixels.” This detector circuit can also be used to perform signal
conditioning for other sensor applications that require detection
of very small signals in a high background noise environment.
Index Terms— Detectors, image sensors, integrated circuit
noise, intelligent sensors, photodiodes, switched-capacitor
circuits.
I. INTRODUCTION
B IOLOGICAL image systems demonstrate that image pro-
cessing can be done very efficiently if raw pixel in-
formation is processed in parallel to extract only relevant
information. This parallel preprocessing dramatically reduces
the amount of information that the central processing unit
(CPU) has to process. Even with the relatively low bandwidths
of biological hardware, they are much faster than the inherently
serial computation of most digital computers. Reducing the
amount of information sent to the CPU also reduces the power
consumed by the pad drivers and makes it easier to keep
digital switching noise off the sensitive analog pre-amplifiers.
The application of the image processor dictates the relevant
information to be collected and processed. Image processing
pertaining to edge extraction, motion sensing, texture, or
intensity changes is usually concerned with only one or
two criteria. For example, fingerprint analysis could ignore
motion, temporal intensity changes, and average intensity.
Missile tracking can be done without trying to figure out
what shape the target is. Paint job inspection may only be
interested in texture, and locating lightning strikes might only
pay attention to temporal changes in intensity. In our satellite
communications application, we need to constantly monitor
pixels for flashes of light which have significant energy in the
100 Hz to 20 kHz bandwidth. When such a signal is detected,
the data from that pixel is amplified, low pass filtered, and
routed to an analog-to-digital converter (ADC) for processing
by the CPU. The signals of interest may be as small as 1 nA
Manuscript received August 15, 1996; revised November 6, 1996.
D. C. Thelen, Jr. is with Microelectronics Research Center, University of
New Mexico, Albuquerque, NM 87106 USA.
D. D. Chu is with Custom Microcircuits & Nonvolatile Memories, Sandia
National Laboratories, Albuquerque, NM 87185-1074 USA.
Publisher Item Identifier S 0018-9200(97)01288-2.
0018–9200/97$10.00  1997 IEEE
337
and have a background illumination as large as 10 A. One
way to remove the background signal is to integrate the output
signal and feed it back to the input [1]. For an array of 1024
pixels, 32 signal processors must fit on one chip and consume
less than 62.5 mW. The chip must also operate in a satellite
radiation environment.
II. CIRCUIT DESCRIPTION AND SYSTEM REQUIREMENTS
Many array-based sensing systems impose constraints on the
design and implementation of the readout detector electronics
such as low noise and low power operation [2]. In our
satellite-based sensor system we faced the following technical
challenges in the design of the readout detector electronics:
1) input referred noise less than or equal to the photo-diode
shot noise in the hundreds of picoampere range;
2) on-chip 100 Hz to 20 kHz band pass filtering of photo-
diode signal;
3) ability to adjust and disable the low frequency (100 Hz,
200 Hz, 300 Hz, etc.) high pass pole;
4) hold the dc background signal (static background image
subtraction) for several seconds.
Fig. 1 shows a block diagram of a single pixel readout
detector circuit. A transimpedance amplifier (TIA) converts
the photo-diode current to voltage which then goes through a
gain stage also used as a low-pass filter. Its bias current is set to
produce a 3-dB 20-kHz roll-off. Next, dc and low frequency
( 100 Hz) noise components of the signal are removed by a
switched-capacitor integrator (background subtractor circuit)
feeding back to the input of the transimpedance amplifier
through resistors . Finally, an auto-zeroed comparator with
an adjustable trigger level detects signals of interest. Tripping
the comparator turns off the clock to the background subtract
circuit, causing it to hold its present value. This permits an
ADC to digitize data from this activated pixel. Note that the
integrator will not alias signals being fed to the ADC because
the switched capacitor integrator clock has been disabled by
the comparator. Since the clock turns off when a signal trips
the comparator, there are two transfer functions for input
signals. The background signals ( 100 Hz) see a sampled
data system while the transient signals pass through only
continuous circuits. The transfer function from the photo-diode
to the comparator input for background signals below the
Nyquist rate is
(1)
338
Fig. 1. A single pixel readout detector signal processing module.
Notice that the pole is inside the unit circle (therefore the loop
is stable) when . There is a
zero at dc which removes the background illumination
and flicker noise from the transimpedance amplifier below
100 Hz. Simulated background subtraction is shown in Fig. 2
when the input is a current ramp. The response of an equivalent
circuit loop using a continuous time integrator having the
same time constant as our sampled system is shown for
comparison.
Once the clock stops, transient signals are simply low passed
by the transimpedance amplifier output buffer
kHz
(2)
kHz
The gain stage is set at k ,
and the unity gain frequency of the integrator is set to 10 Hz
by using a 16 pF to 1 pF capacitor ratio with a 1 kHz
sampling clock. This sets the high pass pole of the overall
loop to 100 Hz. The 1 kHz clock was chosen to keep the
switched capacitor ratios small and is skewed to a 99% duty
cycle to maximize the time that the circuit looks for signals
of interest. All circuits are differential for better rejection of
power supply noise, but the input signal is single ended, so two
conversions are necessary. The transimpedance amplifier must
convert its single-ended input to a differential output, and the
integrator should supply a single-ended background canceling
current through the feedback resistors. This is accomplished by
connecting the common-mode feedback amplifier of the actual
integrator used, shown in Fig. 5, so there is no voltage across
the feedback resistor connected to the negative TIA input. The
common-mode feedback amplifier in the TIA performs the
required single-ended-to-differential conversion.
III. TRANSIMPEDANCE AMPLIFIER DESIGN
The most simple way of converting photo-diode current to
a voltage is to connect a resistor between the photo diode
IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 32, NO. 3, MARCH 1997
and ground, then buffer the resulting voltage. In practice, this
is not done because parasitic capacitance can cause low pass
filtering of the input current. One remedy is to place a current
buffer between the photo diode and the resistor to keep the
input resistance low, thereby pushing the parasitic pole up in
frequency [3].
A current buffer TIA is shown in Fig. 3. Input current
enters the buffer at the source of the cascode transistor MP3.
The input resistance seen by the current is approximately
. Since the drain current of a MOSFET equals the
source current, the input current flows to the drain of MN1
and the output resistors (RL). The current in the pull downs
MN3 and MN4 is controlled by the common-mode feedback
amplifier (CMF). For the single-ended input current, the cur-
rent from the drain of MP3 splits so half goes through the
output resistor and half through MN3. The noise analysis in
Section V shows the superiority of this circuit over an op-
amp-based transimpedance amplifier given our constraints on
power consumption and area.
Fig. 4 shows a small signal model of the TIA. Although
the signal path for the current buffer driving a resistor does
not include a feedback loop, the common-mode feedback
loop still requires a stability analysis. Moreover, since the
input is single-ended, the common-mode feedback ampli-
fier needs to have high gain as shown by the dc transfer
function of common-mode voltage to single-ended input cur-
rent
(3)
where and are the output impedance of the n-channel
and p-channel cascode current mirrors, respectively, is the
transconductance of MN3 and MN4, and is the common-
mode feedback amplifier gain. If we assume that the cascode
current mirror output impedances are very large, this equation
THELEN AND CHU: LOW NOISE READOUT DETECTOR CIRCUIT 339

Fig. 2. Simulated 10 2 gain stage output for a ramped input current.

Fig. 3. Schematic of a current buffer transimpedance amplifier.

340
Fig. 4. Small signal model of the current buffer transimpedance amplifier.
Fig. 5. Integrator with glitch suppression capacitor.
simplifies to
(4)
Therefore, the common-mode feedback amplifier gain and
n-channel current mirror transconductance must be large to
maintain a small common-mode voltage on the output when
the input is a single-ended current. There are two tradeoffs
which must be considered when minimizing the common-
mode output voltage. First, we will show in Section V that
it is desirable to keep as small as possible to minimize
the input referred thermal noise of the buffer. Second, the
common-mode feedback loop will have very high gain because
the cascode amplifier will add between 60–80 dB of gain to the
common-mode feedback amplifier. To stabilize this high-gain
feedback loop, compensation capacitors are fed back around
the cascode gain stages making use of the Miller effect to
IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 32, NO. 3, MARCH 1997
create a dominant pole. The small signal model is the familiar
two-stage operational transconductance amplifier (OTA) model
[4]. To maintain stability, where is the
capacitance on the transimpedance amplifier outputs, and
is the transconductance of the CMFB amplifier differential
pair. Buffered compensation is used to avoid the right half
plane zero.
IV. SWITCHED-CAPACITOR INTEGRATOR DESIGN
The integrator was realized as a switched capacitor circuit
because the 10 ms time constant was too long for RC or
transconductor C topologies. The desired time constant was
realized by using a 1 kHz sample clock and a 16 : 1 capac-
itor ratio. Since the signals coming into the integrator are
bandlimited to 20 kHz, and the sample clock is only 1 kHz,
we have to address aliasing of both signals and noise. Signal
current can be divided into two parts. There is a slowly varying
THELEN AND CHU: LOW NOISE READOUT DETECTOR CIRCUIT
(a)
(b)
(c)
(d)
Fig. 6. Alternative switched-capacitor integrator switch configurations.
background signal which is bandlimited between 0 and 100 Hz,
and there are transient signals which we are looking for that
are less that 20 kHz. There is a system requirement that the
background subtraction not be updated while we are digitizing
a transient signal. Therefore, the integrator clock is turned off
any time there is a transient with energy above 100 Hz and
there is no aliasing. To keep the integrator transfer function
valid with continuous feedback through the transimpedance
amplifier and the gain stage, the integrator must not have a
continuous path from input to output. The integrator input is
delayed, which corresponds to the forward Euler configuration.
The integrator must also have low offset compared to the
comparator threshold which may be set as low as 4 mV.
Since this is about the same as the expected offset of a
CMOS OTA, an offset canceling integrator is required. The
341
(a)
(b)
(c)
(d)
Fig. 7. Equivalent circuits for evaluating switch configurations.
Nagaraj integrator [5], [6] was chosen because it uses only
three capacitors, the output does not slew to zero on each half
clock, and it is parasitic insensitive. The integrator with the
glitch suppression capacitor was shown in Fig. 5.
A differential integrator has no ground connection to either
of the op-amp inputs and has no dc feedback path from the
op-amp outputs to establish a common-mode voltage on the
op-amp inputs. It is conceivable, therefore, that the op-amp
could be biased with a common mode input voltage which
forces the differential pair out of saturation. Reverse bias diode
leakage in the switches, charge injection, and initial conditions
during power up could all lead to a common-mode voltage at
342
Fig. 8. Simulated output noise due to op-amps with clock running.
the op-amp input. There are four different ways to arrange the
switches for a simple integrator as shown in Fig. 6.
When evaluating these configurations to see which removes
the common-mode component best, it helps to connect both
inputs to signal ground, and model the op-amp as a capacitor
to ground as shown in Fig. 7. This simplification assumes
that the op-amp has infinite gain, and therefore, the inputs
are constrained to be the same voltage, and that the outputs
of the integrator are not moving so the integrating capacitors
appear to go to ground.
In the arrangement of Fig. 7(a), the input capacitors, , noise are from the op-amps and the transimpedance amplifier.
are charged to 0 V on phase 1 and must share charge with
the integrating capacitors, , on phase 2. After several clock
cycles, the common-mode charge on the integrating capacitors
will be dissipated. In the arrangement of Fig. 7(b), the input
capacitors are initialized to zero on phase 1, but on phase 2
the voltage on the left side of the input capacitors becomes
the same as the initial voltage on the integrating capacitors
and no charge transfers. In the scheme of Fig. 7(c), the
voltage on the input capacitors cannot be determined during
phase 1, but the two voltages are equal. On phase 2, charge
transfers until the voltage on the input capacitors becomes the
same as the voltage on the integrating capacitors. No more
charge transfers on successive clocks. The charge on the input
capacitors cannot be determined during phase 1 for the scheme
of Fig. 7(d), and no charge transfers on phase 2 because the
left side of the input capacitors floats to the sum of the two
capacitor voltages. Therefore, scheme (a) is the only one which
IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 32, NO. 3, MARCH 1997
will remove the common-mode input signal from the op-amp
when parasitic capacitors are ignored.
V. THERMAL NOISE
Thermal noise comes from four main places in this circuit;
the 400 k resistors, the op-amps, the transimpedance ampli-
fier, and the switches in the integrator. With the clocks stopped,
there is a continuous transfer function from each of these noise
sources to the loop output. The most significant sources of
When the clocks are running, there are still continuous transfer
functions from each of the noise sources to the output for
both phases of the clock, and the noise on the integrator input
capacitors gets sampled and held. Impulse sampling of noise
(whose bandwidth is 20 kHz or more) with a 1 kHz clock
results in images of the noise centered at the harmonics of the
clock, with severe aliasing. If the power spectral density of
the presampled noise is white, except for band limiting, the
number of overlapping noise images in the frequency range
is given in [7] as
(5)
where is the bandwidth of the presampled noise, and
is the sample frequency. When is an integer multiple
of , or when , the total noise in the frequency
THELEN AND CHU: LOW NOISE READOUT DETECTOR CIRCUIT 343

Fig. 9. FFT of simulated output noise due to op-amps with clock running.

Fig. 10. Simulated output noise due to all sources with clock running.
344 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 32, NO. 3, MARCH 1997

Fig. 11. FFT of simulated output noise due to all sources with clock running.

Fig. 12. Simulated output noise due to all sources with clock stopped.
THELEN AND CHU: LOW NOISE READOUT DETECTOR CIRCUIT 345

Fig. 13. FFT of simulated output noise due to all sources with clock stopped.

range is

(6)

where is the presampled noise energy. Holding the impulse

samples causes the aliased noise to be attenuated by the sinc
function. The total sampled-and-held noise is now given in
(7) as

(7)

This system has a duty cycle very close to one and a ratio
of noise bandwidth to sample frequency of about 500 for the
integrator op-amp. The output is therefore expected to have a
noise component which is relatively flat up to 20 kHz, a lobe of
aliased noise below 1 kHz, and possibly higher frequency lobes
if they are above the white noise floor. Transient simulations
of the loop were performed on Saber, followed by an FFT to
examine the frequency content of the output. The op-amps
were modeled as single pole, finite gain amplifiers with a
noisy resistor at the input. The switches were modeled as ideal
Fig. 14. Die photo of the four pixel readout detector test chip.
digitally controlled switches with a series noisy resistor. No
flicker noise was added to the models. A plot of the gain stage
output when only the op-amp noise is turned on is shown The output of the gain stage is plotted in Fig. 10 for all the
in Fig. 8. The sampled noise is clearly superimposed on the noise sources turned on. The FFT of this wave form is shown
continuous noise. The FFT of this simulation output is shown in Fig. 11. It is harder to see the higher frequency lobes of the
in Fig. 9. The first three lobes of the attenuation of the sampled-and-held noise with the increased broadband noise
aliased noise are visible along with the broad band component. level.
346
Fig. 15. Step response of a readout detector circuit loop.
The output of the gain stage with all noise sources turned
on and the clocks turned off is shown in Figs. 12 and 13. With
the sampled-and-held noise missing, the noise power spectral
density is relatively flat.
The input referred current noise of the transimpedance
amplifier (Fig. 3) is dominated by the mean square sum of
the current noise in transistors MP1, MP2, MN3, and MN4.
Thermal noise current is proportional to , so the drain
current and the of these transistors must be made small
to minimize thermal noise. To minimize the flicker noise, the
channel lengths of MP1, MP2, MN3, and MN4 must be made
long and their drain currents small. Therefore, optimizing noise
performance also complements our efforts to minimize area
and power consumption to fit 32 channels on a chip. However,
there is a tradeoff with having too small of a bias current in
the buffer. If the input current coming out of INP exceeds the
bias current supplied from MP1, the input current signal will
be clipped. We also want to have the input impedance of the
current buffer be low, but we cannot have a large bias current
to accomplish this. A small input impedance can be obtained
by increasing the of transistor MP3 by making its
large. In our application, the input current is unidirectional (we
expect pulses of light, not darkness) so the input stage can
actually be used in a class AB fashion. Note that the current
coming into the INP pin increases the of MP3 and can be
much larger than the bias current without causing clipping.
VI. CORRELATED NOISE
Signals from neighboring circuits can couple through the
power supplies, the substrate, and from parallel or overlapping
IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 32, NO. 3, MARCH 1997
interconnect onto sensitive nodes such as the transimpedance
amplifier input. Capacitive coupling from parallel and overlap-
ping interconnect were avoided by careful layout and shielding
of sensitive nodes. Differential circuits were also used to reject
cross talk through the power supplies. A separate power supply
connected only to the substrate keeps voltage drops on the
main supply lines from modulating the substrate and causing
cross talk. Because the input pads are low impedance, the
voltage swings will be small, and minimal coupling between
neighboring pixels will occur. A “dummy” pad was connected
to the unused input of the transimpedance amplifier. This was
done to allow for common-mode noise cancellation at the input
pads caused by noise from the substrate coupled through the
pad metal and electrostatic discharge (ESD) protection device
diodes.
VII. OFFSETS, LEAKAGE, CHARGE
INJECTION, AND NONLINEARITY
Close attention was paid to the cell and chip layout using
matched and common centroid layout techniques to reduce in-
put offsets. The ability to hold the background level for several
seconds was achieved by using a differential integrator. While
the integrator is holding the background current, any leakage
current on the switches between the sampling capacitor and the
op-amp will be seen as a common mode signal, and rejected by
the common-mode feedback circuit. Charge injection was also
reduced to a common-mode signal by using delayed clocks on
switches where the gate-to-source voltage is signal dependent
[8]. In the integrator, only the switches connected to the input
cause signal-dependent charge injection.
THELEN AND CHU: LOW NOISE READOUT DETECTOR CIRCUIT
Fig. 16. Comparator and 10 2 gain stage outputs for a 6-nA input step.
N-well resistors were used in the transimpedance amplifier.
These resistors are known to have several problems including a
nonlinear voltage-to-current relationship, distributed parasitic
capacitance, large process variation, and large temperature
coefficient. Using differential circuits cancels the odd or-
der nonlinearities of the n-well resistors. The distributed
capacitance does not cause sufficient phase shift to cause
instability in the current buffer transimpedance amplifier. The
gain variation caused by the large resistor process variation
and temperature coefficient was compensated for by using a
trimming network for the 400 k resistors.
VIII. MEASURED RESULTS
We have evaluated the performance of the readout detector
test chip shown in Fig. 14.
The test chip was fabricated using Orbit Semiconductor’s
1.2- m n-well process. Fig. 15 shows a step response of the
readout circuit.
A 1.36 V input (755 nA via a 1.8 M resistor) step is
applied to the readout detector input. The output changes
before the next clock edge, demonstrating the continuous path
from photo-diode to output. On the next clock, 62.5% of the
step is subtracted. With successive clocks we see that the
circuit “subtracts” out the dc background current in 8 ms (five
time constants) which corresponds to our 100 Hz high pass
pole. Fig. 16 shows the comparator and gain stage outputs
when a small step is applied to the input. The input is trace 1,
the gain stage output is trace 2, and the comparator output is
trace 3. The input step is 6 nA. The gain stage output is clearly
much larger than the noise, and the low power comparator
delay is about 10 s.
Fig. 17 shows the output of the integrator when the input
is a 18-nA 50-Hz triangle wave. Trace 1 is the input, and
trace 2 is the integrator output. The signal is slow enough
that it is considered a background signal and subtracted out.
Noise contributions from the integrator switches and op-amp
are clearly visible at this scale.
Fig. 18 shows a spectrum analyzer plot of the noise on the
10 gain stage output with the clocks running.
347
Fig. 17. Integrator output with a 18-nA 50-kHz triangle wave input.
Fig. 18. Spectrum analyzer plot of 10 2 gain stage noise.
Harmonics of the clock are due to power supply spiking. We
can see the first two lobes of the characteristic sinc attenuation
of the aliased sampled-and-held noise. The noise level agrees
well with simulation.
IX. SUMMARY
We have developed a low noise readout detector circuit
suitable for sensing applications that require detection of
nanoampere signals. Moreover, in our satellite communica-
tions application, the circuit is able to discriminate transient
light pulse signals having a characteristic amplitude and band-
width out of a large (static) background image. Special circuit
techniques were developed to maximize signal sensitivity
and minimize noise source contributions. Measurements taken
from the chip demonstrate nanoampere signal sensitivity over
a 100 Hz to 20 kHz bandwidth.
ACKNOWLEDGMENT
The authors would like to especially thank J. Falls, J. Schae-
fer, and R. Kay from Sandia, for system concept development
and measurements. The authors are also grateful for D. Dixon,
A. Medina, and M. Knoll from Sandia for their support of this
project.
348 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 32, NO. 3, MARCH 1997

REFERENCES Donald C. Thelen, Jr. received the M.S.E.E. degree

from Montana State University, Bozeman, in 1984
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[7] J. H. Fischer, “Noise sources and calculation techniques for switched the Master’s in electrical engineering at Cornell
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[8] K. L. Lee and R. G. Meyer, “Low-distortion switched-capacitor fil- In 1986 he joined Sandia National Laboratories
ter design techniques,” IEEE J. Solid-State Circuits, vol. SC-20, pp. in Albuquerque, NM, as a Member of Technical
1103–1113, Dec. 1985. Staff in the microprocessors and memories group
designing radiation-hardened integrated circuits. In
1988 he joined startup Brooktree Corporation in San
Diego, CA, where he assisted in the design of high
performance PC and workstation graphics (RAMDAC) chips. From 1990 to
1993 he was at ABB HAFO in San Diego, CA, working on custom low-
power mixed-signal ASIC’s, for use in biomedical electronic products such
as pacemakers and hearing aid devices. In 1993 he returned to Sandia National
Laboratories as a Senior Member of Technical Staff. He is currently in the
custom microcircuits and nonvolatile memories group and specializes in the
design and development of custom mixed-signal IC’s that interface to sensor
chips and remote sensing systems.