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    X: Don'T Care: Loada Storea Adda Suba Ina Outa Jpos Jneg JZ JNZ JMP Halt

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    Daniel Felipe
    This document defines the instruction set architecture (ISA) for a simple processor. It includes instructions to load from memory into a register A, store from A to memory, perform arithmetic operations of addition and subtraction on A using values from memory, input and output to/from a data pin, conditional and unconditional jump instructions, and a halt instruction. The instructions are encoded into binary with an x don't care bit and the memory address or jump target in the aaaaaa bits.

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    X: Don'T Care: Loada Storea Adda Suba Ina Outa Jpos Jneg JZ JNZ JMP Halt

    Uploaded by

    Daniel Felipe
    15 views1 page
    This document defines the instruction set architecture (ISA) for a simple processor. It includes instructions to load from memory into a register A, store from A to memory, perform arithmetic operations of addition and subtraction on A using values from memory, input and output to/from a data pin, conditional and unconditional jump instructions, and a halt instruction. The instructions are encoded into binary with an x don't care bit and the memory address or jump target in the aaaaaa bits.

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    ISA.docx

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    This document defines the instruction set architecture (ISA) for a simple processor. It includes instructions to load from memory into a register A, store from A to memory, perform arithmetic operations of addition and subtraction on A using values from memory, input and output to/from a data pin, conditional and unconditional jump instructions, and a halt instruction. The instructions are encoded into binary with an x don't care bit and the memory address or jump target in the aaaaaa bits.

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    © All Rights Reserved
    Download as DOCX, PDF, TXT or read online from Scribd
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    Download as docx, pdf, or txt
    15 views1 page

    X: Don'T Care: Loada Storea Adda Suba Ina Outa Jpos Jneg JZ JNZ JMP Halt

    Uploaded by

    Daniel Felipe
    This document defines the instruction set architecture (ISA) for a simple processor. It includes instructions to load from memory into a register A, store from A to memory, perform arithmetic operations of addition and subtraction on A using values from memory, input and output to/from a data pin, conditional and unconditional jump instructions, and a halt instruction. The instructions are encoded into binary with an x don't care bit and the memory address or jump target in the aaaaaa bits.

    Copyright:

    © All Rights Reserved
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    Download as docx, pdf, or txt
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    ISA: Instruction Set Architecture:

    x: don’t care

    Instruction Encoding Operation Comment


    loadA 0000xxaaaaaa ARAM[aaaaaa]
    storeA 0001xxaaaaaa RAM[aaaaaa]A
    addA 0010xxaaaaaa AA+RAM[aaaaaa]
    subA 0011xxaaaaaa AA-RAM[aaaaaa]
    inA 0100xxxxxxxx ADin
    outA 0101xxxxxxxx DoutA
    jpos 0110xxaaaaaa If(A>0) then PC=aaaaaa
    jneg 0111xxaaaaaa If(A<0) then PC=aaaaaa
    jz 1000xxaaaaaa If(A==0) then PC=aaaaaa
    jnz 1001xxaaaaaa If(A!=0) then PC=aaaaaa
    jmp 1010xxaaaaaa PC=aaaaaa
    halt 1011xxxxxxxx halt

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