Program 27

Aim: To implement given conditions on a PLC.

Program:

Input Output
I0.1 L1 (ON)
I0.2 L1,L2 (ON)
I0.3 L1,L2,L3 (ON)
I0.4 Reset all

Solution:

Ladder Logic
 Program 28

Aim: To implement basic Timer Circuit (Ton)

Theory:

PLC timers are instructions that provide the same functions as on-delay and
off-delay mechanical and electronic timing relays. A PLC timer provides a
preset delay to the control actions.

In general, there are three types of PLC timer delays, ON-delay timer, OFF-
delay timer and retentive timer on.

The terms represented in the timer block in the PLC are a Preset value which
means the delay period of the timer, an Accumulated value which is the
current delay of the timer.

A timer begins the counting on time-based intervals and continues until the
accumulated value equals the preset value. When the accumulated value
equals the preset time the output will be energized. Then the timer sets the
output.

TON timer or ON delay timer

An ON delay timer is used where we need a time delay before the time delay
before an instruction becomes true.

A representation TON timer is shown above, which contains,

Timer number: The timer file name

Time base: which is shown in seconds,
 Preset value: Numeric valve set as the delay required to the timer.
Accumalated value: The values are counting is displayed from zero. Value
becomes zero whenever the timer is reset

 The timer starts operating when the rung condition becomes true. The
timer delay starts counting when the rung condition starts to accumulate.
 When the Preset value becomes equal to the accumulated value, the
output is made true.
 The timed output becomes true sometime after the timer rung becomes
true; hence, the timer is said to have an on-delay.
 The length of the delay can be adjusted by setting the preset value.

Program:

Turn on an output light, 5 seconds after switch is turned on.

Solution:

Ladder Logic
 Program 29

Aim: To implement basic Timer Circuit (TOFF).

Theory:

TOFF timer or OFF delay timer:

A TOFF timer will keep the output energized for a preset time after the rung signal has gone
false.

The TOFF timer will have all the contents as in the TON timer, with the similar function.
 When the rung timer is true, the output will be true without any delay. When the rung
signal becomes false the timer starts operating.
 The timer starts accumulating times when the rung condition becomes true, until the
accumulated value becomes equal to the Preset value.
 The output turns off when the output will turn false when the accumulated value
equals the preset value.

Solution:

Ladder Logic:
 Program 30

Aim: To implement TOFF Timer Circuit using TON Timer Circuit.

Solution:

Ladder Logic:
 Program 31

Aim: To implement given conditions on a PLC.

Program:

LED ON after
1 2 seconds
2 4 seconds
3 6 seconds
4 8 seconds

Solution:

Ladder Logic
 Program 32

Aim: To implement given conditions on a PLC.

Program:

There are 4 LED’s which get ON after interval of 2 seconds consecutively and
LED which glows first gets OFF after the next LED gets ON.

LED ON after
1 2 seconds
2 4 seconds
3 6 seconds
4 8 seconds

Solution:

Ladder Logic
?
 Program 33

Aim: To implement given conditions on a PLC.

Program:

SEQUENCE OUTPUT
2 seconds after input is triggered L1,L2,L3,L4 ON
2 seconds further L1 OFF
2 seconds further L2 OFF
2 seconds further L3 OFF
2 seconds further L4 OFF

Solution:

Ladder Logic
 Program 34

Aim: To implement given conditions on a PLC.

Program:

There are 6 LED’s namely L1,L2,L3,L4,L5 and L6 and they follow a certain
sequence after an input is triggered.
SEQUENCE OUTPUT
2 seconds after input is triggered L1,L2 ON

2 seconds further L3,L4 ON

 2 seconds further L5,L6 ON

2 seconds further L1,L2,L3 OFF

2 seconds further L2,L4,L6 OFF

2 seconds further All ON
2 seconds further All OFF

Solution:

Ladder Logic
 Program 35

Aim: To implement given conditions on a PLC.

There are 3 motors namely M1,M2 and M3.

M1 starts as soon as switch is on and after 10 seconds M1 goes off and

simultaneously M2 starts and after 5 seconds M2 goes off and simultaneously
M3 starts and after 10 seconds M3 goes off and M1 starts again and cycle is
repeated.

Solution:

Ladder Logic
 Program 36

Aim: To implement 2 pole traffic light signal system on PLC.

Program: There is a 2 pole traffic light system having 3 status LED’s.

Solution:

Ladder Logic
 Program 37

Aim: To implement 4 pole traffic light signal system on PLC.

Program: There is a 4 pole traffic light system having 2 status LED’s.

Solution:

Ladder Logic
 Program 38

Aim: To implement given conditions on a PLC

Theory:
A pulse is a burst of current, voltage, or electromagnetic-field energy. In practical electronic
and computer systems, a pulse may last from a fraction of a nanosecond up to several seconds
or even minutes. In digital systems, pulses comprise brief bursts of DC (direct current)
voltage, with each burst having an abrupt beginning (or rise) and an abrupt ending (or decay).

Program:

Input No. Of pulses to trigger Output

output

1 5 1,2 ON

2 4 3,4 ON

3 3 All OFF

Solution:

Ladder Logic
 Program 39

Aim: To implement a car parking system on a PLC.

Program:

There are 15 parking slots in a building and there are 2 status LED’s both on the
entrance and exit.

LED STATUS

Red No parking space available

Green Parking space available

Solution:

Ladder Logic
 Program 40

Aim: To implement a pulse counter on a PLC.

Theory:

Duty Cycle
When the signal is high, we call this "on time". To describe the amount of "on time" , we use
the concept of duty cycle. Duty cycle is measured in percentage. The percentage duty cycle
specifically describes the percentage of time a digital signal is on over an interval or period of
time. This period is the inverse of the frequency of the waveform.
If a digital signal spends half of the time on and the other half off, we would say the digital
signal has a duty cycle of 50% and resembles an ideal square wave. If the percentage is
higher than 50%, the digital signal spends more time in the high state than the low state and
vice versa if the duty cycle is less than 50%. Here is a graph that illustrates these three
scenarios:

50%, 75%, and 25% Duty Cycle Examples

100% duty cycle would be the same as setting the voltage to 5 Volts (high). 0% duty cycle
would be the same as grounding the signal.

Program:

Implement a pulse counter with 50% duty cycle up to 10 pulses.

Solution:

Ladder Logic
 Program 41

Aim: To implement given conditions on a PLC.

Program:

In a class with seating capacity of 20 there are 3 status LED’s

LED Status
RED ON till the class is full
GREEN ON when class gets full ; Initially Off;
Remains ON for 10 seconds provided
20 students remain in the class then
gets turned OFF.
YELLOW Gets turned ON after green LED is
OFF ; Remains ON for 15 seconds and
then gets turned OFF.

Solution:

Ladder Logic