Industrial Automation and

PLC Programming

Submitted To:- Submitted By:-

Dr. Hitesh Pahuja Anmol Ahuja ACSD

Navrinder Singh

CDAC,Mohali Tanveer Singh Dhandli

Vishal Singh
 INDEX
SR.NO CONTENT PAGE REMARKS
NO.

1 PLC program to implement Logic Gates

2 PLC program to implement various Boolean

functions

3 PLC program to implement Boolean function with

don’t care.

4 PLC program to implement combinational logic

circuit Y1=1 is the input binary number is 5 or less

then 5 Y2=1 if input binary number is 9 or more

then 9.

5 A circuit has 4 inputs (A, B, C, and D) and 2

outputs (Y1, Y2). One of the outputs is high when

majority of inputs are high. The second output is

high when all inputs are of same type. Design the

combinational circuit and implement it in PLC.

6 PLC Program to Implement Binary to BCD

Converter.

7 PLC Program to Implement BCD to Excess-3 Code

Conversion.

8 PLC Program to Implement Half Adder and Full

Adder
9 PLC Program to Implement Binary to Gray Code

Conversion

10 PLC Program to Implement 2-bit Magnitude

Comparator

11 PLC Program to Implement 4x1 Multiplexer

12 PLC Program to Implement 8x1 Multiplexer

13 PLC Program to Implement 3x8 Decoder

14 PLC Program to Implement Gray code to Binary

Code Conversion

15 PLC Program to Implement 1x8 Demultiplexer

16 PLC Program to Implement seven segment display

decoder.

17 PLC Program to turn on Motor and Lamp with ON

button and to turn it off with OFF button

18 PLC Program to Implement the following logic:

1,1,2 - > Motor 1 ON

3,3,4 - > Motor 2 ON

5 - > Motor 1, Motor 2 OFF

19 PLC Program to Implement the following logic:

Input Switch 1 -> Motor 1, Motor 2 ON

 Input Switch 2 - > Motor 3, Motor 4 ON

Input Switch 3 - > Motor 5, Motor 6 ON

Input Switch 4 - >All Motors OFF

20 PLC Program to Implement the following logic:

Input Switch 1 -> Motor 1, Motor 2 ON

Input Switch 2 - > Motor 3, Motor 4 ON

Input Switch 3 - > Motor 1, Motor 3 OFF

Input Switch 4 - > Motor 2, Motor 4 OFF

21 PLC Program to Implement the following logic:

0,1,2 - > Motor ON

3,4,5 - > Motor OFF

22 PLC Program to Implement Toggle switch.

23 A selection committee comprises 4 members

including the chairman in order for coordination to

the selected she/he has to support at least two

members. The chairman however can post any

candidate through. If each member is provided with

switch. Design a logic that will ring a bell when

 candidate is selected.

24 Design a 1:4 De Mux using a Laddar Logic

.Assume the input are connected to input control

signal and the output terminal

25 1.....1 on 2,3,4 OFF

2.....2on 1,3,4 OFF

3.....3on 1,2,4 OFF

4.....4on 1,2,3 OFF

5.................RESET ALL

26 PRESS 1 (1,2,3) ON `

PRESS 2 1 OFF

PRESS 3 2 OFF

PRESS 4 3 OFF

27 Implementation of basic TON Timer circuit.

28 Implementation of basic TOFF Timer circuit.

29 To Implement TOFF using TON

30 PLC Program to Implement the following logic:

LED 1 ON after 2 second

 LED 2 ON after 4 second

LED 3 ON after 6 second

All OFF after 8 second

31 PLC Program to Implement the following logic:

After 2 second L1,L2 ON

After 2 second L3,L4 ON

After 2 second L5,L6 ON

After 2 second L1,L3,L5 OFF

After 2 second L2,L4,L6 OFF

After 2 second All ON

After 2 second All OFF

32 PLC Program to Implement the following logic:

LED 1 ON after 2 second

LED 2 ON after 2 second

LED 3 ON after 2 second

LED 4 ON after 2 second

Without Loop

33 PLC Program to Implement the following logic:

LED 1 ON after 2 second

LED 2 ON after 2 second

LED 3 ON after 2 second

 LED 4 ON after 2 second

With Loop

34 3 Motor System

M1 Will start as soon as switch is pressed

After 10 sec M1 off M2 start

After 5 sec M2 off M3 start

After 10 sec M3 off M1 start

And repeat

35 To implement All LED initially ON and OFF each

after 2 sec on Switch Pressed

36 Implementation of 2 Pole Traffic Light using Timer

circuit.

37 Implementation of 4 Pole Traffic Light using Timer

circuit.

38 To implement Counter Program 1

49 To implement Car Parking System

40 To generate 10 pulses after S1 is pressed

41 To implement Classroom and Staff room Logic

Light System

42 To implement a batch counting operation to sort

parts automatically for quality control.

43 To implement following logic on PLC:

 LED 1,LED 6 ON after 2 second

LED 2,LED 5 ON after 2 second

LED 3,LED 4 ON after 2 second

All OFF after 2 seconds

Loop repeats 3 times

44 To implement following logic on PLC:

LED 1 ON after 2 second

LED 2 ON after 2 second

LED 3 ON after 2 second

LED 4 ON after 2 second

LED 5 ON after 2 second

Sequence is repeated 3 times.

4th time all the output’s are turned off.

Repeat the process from beginning.

45 To implement washing machine.

46 To implement a conveyor belt system for a

mechanical stack machine.

47 To implement an automatic counting spool system.

 INTRODUCTION

A programmable logic controller (PLC) or programmable controller is an industrial digital

computer which has been ruggedized and adapted for the control of manufacturing processes,
such as assembly lines, or robotic devices, or any activity that requires high reliability control
and ease of programming and process fault diagnosis.
 Program 1

OBJECTIVE: Execute ladder diagram of AND, OR, NOT, NAND, NOR, X-OR, X-NOR
gate.

THEORY:

A logic gate is an elementary building block of a digital circuit. Most logic gates have two inputs
and one output. At any given moment, every terminal is in one of the two binary conditions low
(0) or high (1), represented by different voltage levels. The logic state of a terminal can, and
generally does, change often, as the circuit processes data. In most logic gates, the low state is
approximately zero volts (0 V), while the high state is approximately five volts positive (+5 V).

There are seven basic logic gates: AND, OR, XOR, NOT, NAND, NOR, and XNOR.

AND gate

The AND gate is so named because, if 0 is called "false" and 1 is called "true," the gate acts in the
same way as the logical "and" operator. The following illustration and table show the circuit symbol
and logic combinations for an AND gate. (In the symbol, the input terminals are at left and the
output terminal is at right.) The output is "true" when both inputs are "true." Otherwise, the output
is "false." Input 1 Input 2 Output
0 0 0
0 1 0
1 0 0
1 1 1

OR gate

The OR gate gets its name from the fact that it behaves after the fashion of the logical inclusive
"or." The output is "true" if either or both of the inputs are "true." If both inputs are "false," then the

Input 1 Input 2 Output

0 0 0
0 1 1
1 0 1
1 1 1

output is "false."
XOR gate

The XOR( exclusive-OR ) gate acts in the same way as the logical "either/or." The output is
"true" if either, but not both, of the inputs are "true." The output is "false" if both inputs are
"false" or if both inputs are "true." Another way of looking at this circuit is to observe that the
output is 1 if the inputs are different, but 0 if the inputs are the same.

Input 1 Input 2 Output

0 0 0
0 1 1
1 0 1
1 1 0

Inverter or NOT gate

A logical inverter , sometimes called a NOT gate to differentiate it from other types of electronic
inverter devices, has only one input. It reverses the logic state.

Input Output
1 0
0 1

NAND gate

The NAND gate operates as an AND gate followed by a NOT gate. It acts in the manner of the
logical operation "and" followed by negation. The output is "false" if both inputs are "true."
Otherwise, the output is "true."

Input 1 Input 2 Output

0 0 1
0 1 1
1 0 1
1 1 0

NOR gate
 The NOR gate is a combination OR gate followed by an inverter. Its output is "true" if both
inputs are "false." Otherwise, the output is "false."

Input 1 Input 2 Output

0 0 1
0 1 0
1 0 0
1 1 0

XNOR gate

The XNOR (exclusive-NOR) gate is a combination XOR gate followed by an inverter. Its output
is "true" if the inputs are the same, and"false" if the inputs are different.

Input 1 Input 2 Output

0 0 1
0 1 0
1 0 0
1 1 1

Ladder Logic
 PROGRAM 2
AIM: PLC program to implement various Boolean functions.
THEORY:
A Boolean function is a special kind of mathematical function f:Xn→Xf:Xn→Xof degree n, where
X={0,1}X={0,1} is a Boolean domain and n is a non-negative integer. It describes the way how to
derive Boolean output from Boolean inputs.

Boolean Expressions
A Boolean expression always produces a Boolean value. A Boolean expression is composed of a
combination of the Boolean constants (True or False), Boolean variables and logical connectives.
Each Boolean expression represents a Boolean function.
Example − AB′CAB′C is a Boolean expression.

Canonical Forms
For a Boolean expression there are two kinds of canonical forms −

 The sum of minterms (SOM) form

 The product of maxterms (POM) form

The Sum of Minterms (SOM) or Sum of Products (SOP) form
A minterm is a product of all variables taken either in their direct or complemented form. Any
Boolean function can be expressed as a sum of its 1-minterms and the inverse of the function can be
expressed as a sum of its 0-minterms. Hence,
F (list of variables) = ∑ (list of 1-minterm indices)
and
F' (list of variables) = ∑ (list of 0-minterm indices)

A B C Term Minterm

0 0 0 x’y’z’ m0

0 0 1 x’y’z m1

0 1 0 x’yz’ m2

0 1 1 x’yz m3

1 0 0 xy’z’ m4
 1 0 1 xy’z m5

1 1 0 xyz’ m6

1 1 1 xyz m7

PROGRAM:
1) f(w,x,y) =∑(1,3,5,7)
2) f(a,b,c,d)=∑(0,1,2,3,5,7,9,11)

SOLUTION:
K-MAP

1)

f(w,x,y) = y

2)

f(a,b,c,d) = a'b' + b'd + a'd

LADDER LOGIC
1)

CPU_Input1 refers to input ‘y’

2)
 PROGRAM 3
AIM: PLC program to implement Boolean function with don’t care condition.

THEORY:
In digital logic, a don't-care term for a function is an input-sequence (a series of bits)
for which the function output does not matter. An input that is known never to occur is
a can't-happen term. Both these types of conditions are treated the same way in
logic design and may be referred to collectively as don't-care conditions for brevity.
[1]
The designer of a logic circuit to implement the function need not care about such
inputs, but can choose the circuit's output arbitrarily, usually such that the simplest
circuit results (minimization). Examples of don't-care terms are the binary values
1010 through 1111 (10 through 15 in decimal) for a function that takes a binary-coded
decimal (BCD) value, because a BCD value never takes on such values (so
called pseudo-tetrades).
Don't care" may also refer to an unknown value in a multi-valued logic system, in
which case it may also be called an X value. In the verilog hardware language such
values are denoted by the letter "X".
PROGRAM:
1) f(A,B,C,D)= m(0,4,5,7,11,15) + Σd(1,10,12,13,14)

f(A,B,C,D)=D+A’C’+AC
LADDER LOGIC
 PROGRAM 4
AIM: PLC program to implement the combination of logic circuits.

THEORY:
The input to combinations logic circuit is a 4-bit binary number. Design the logic
circuit with two outputs (Y1, Y2) for the following conditions. Also develop PLC
program in Ladder Logic for the same.
Y1=1 if the input binary number is 5 or less than 5.
Y2=1 if the input binary number is 9 or more than 9.
Program Solution

 To solve this problem, first the table showing ON state of Y1 and Y2 is

created. (When Y1 or Y2 is 1).

 According to the table designed, Y1 and Y2 both will have different equations,
Y1 when input binary number is 5 or less than 5 and Y2 when input is 9 or more
than 9.

 To obtain these equations, Karnaugh-Map method is again used.

 By solving output expressions, we obtained minimized form of equation

which is then applied into Ladder Diagram.

Output table and Karnaugh-Map method to solve Y1 and Y2 equations

Binary Inputs Outputs
A B C D Y1 Y2
0 0 0 0 1 0
0 0 0 1 1 0
0 0 1 0 1 0
0 0 1 1 1 0
0 1 0 0 1 0
0 1 0 1 1 0
0 1 1 0 0 0
0 1 1 1 0 0
1 0 0 0 0 0
1 0 0 1 0 1
1 0 1 0 0 1
1 0 1 1 0 1
1 1 0 0 0 1
1 1 0 1 0 1
1 1 1 0 0 1
1 1 1 1 0 1

Combinational Circuit for outputs expressed using logic gates.

LADDER LOGIC:
PROGRAM 5
AIM: PLC program to implement the combination of circuit.
THEORY:
A circuit has 4 inputs (A, B, C, and D) and 2 outputs (Y1, Y2). One of the outputs is
high when majority of inputs are high. The second output is high when all inputs are
of same type. Design the combinational circuit and implement it in PLC using Ladder
Diagram programming language.
Y1=1 if majority of inputs are high.
Y2=1 if A=B=C=D.
Problem Solution

 To solve this problem, first the table showing ON state of Y1 and Y2 is

created. (When Y1 or Y2 is 1).

 To obtain these equations, Karnaugh-Map method is again used.

 By solving output expressions, we obtained minimized form of equation

which is then applied into Ladder Diagram.

Output table and Karnaugh-Map method to solve Y1 and Y2 equations.

Binary Inputs Outputs
A B C D Y1 Y2
0 0 0 0 0 1
0 0 0 1 0 0
0 0 1 0 0 0
0 0 1 1 0 0
0 1 0 0 0 0
0 1 0 1 0 0
0 1 1 0 0 0
0 1 1 1 1 0
1 0 0 0 0 0
1 0 0 1 0 0
1 0 1 0 0 0
1 0 1 1 1 0
1 1 0 0 0 0
1 1 0 1 1 0
1 1 1 0 1 0
1 1 1 1 1 1

Combinational Circuit for outputs expressed using logic gates

Ladder Logic
 PROGRAM 6
AIM: PLC implementation of binary to BCD conversion.

THEORY:
BINARY BCD
Implementing Binary to BCD converter in PLC using Ladder Diagram programming
language.
Problem Solution

 Writing truth table showing the relation between Binary as input and BCD as
output.

 To obtain these equations, Karnaugh-Map method is again used.

 For each BCD output D4, D3, D2, D1 and D0, write Karnaugh-Map.

 From the K-Map, obtaining a simplified expression for each BCD output in
terms of Binary inputs.

 Realize the code converter using the Logic Gates.

 And from the same simplified expressions, draw a Ladder Diagram to obtain
BCD output in terms of Binary inputs.

Truth Table relating Binary to BCD

Decimal Binary input BCD output
B3 B2 B1 B0 D4 D3 D2 D2
D0
0 0 0 0 0 0 0 0 0
0
1 0 0 0 1 0 0 0 0
1
2 0 0 1 0 0 0 0 1
 0
3 0 0 1 1 0 0 0 1
1
4 0 1 0 0 0 0 1 0
0
5 0 1 0 1 0 0 1 0
1
6 0 1 1 0 0 0 1 1
0
7 0 1 1 1 0 0 1 1
1
8 1 0 0 0 0 1 0 0
0
9 1 0 0 1 0 1 0 0
1
10 1 0 1 0 1 0 0 0
0
11 1 0 1 1 1 0 0 0
1
12 1 1 0 0 1 0 0 1
0
13 1 1 0 1 1 0 0 1
1
14 1 1 1 0 1 0 1 0
0
15 1 1 1 1 1 0 1 0
1
Boolean expression for each BCD bits can be written as
D4= m(10, 11, 12, 13, 14, 15)
D3= m(8, 9)
D2= m(4, 5, 6, 7, 14, 15)
D1= m(2, 3, 6, 7, 12, 13)
D0= m(1, 3, 5, 7, 9, 11, 13, 15)
Realizing code conversion using Logic Gates
Ladder Logic
 PROGRAM 7
AIM: program for the conversion of BCD to excess 3 code.

THEORY:
Implementing BCD to Excess-3 code conversion in PLC using Ladder Diagram
programming language.
Problem Solution

 Excess-3 code can be derived from BCD code by adding 3 to each number.

 For example, Decimal number 12 is represented as 0001 0010 in BCD. If we

add 3 that is to add 0011 0011 then the corresponding Excess-3 code is 0100 0101.

 Write the truth table relating BCD and Excess-3.

 Write Karnaugh-Map for each output and obtain simplified expression.

 Implement BCD to Excess-3 code conversion circuit using Logic Gates.

 Implement Logic Gates’ circuit in PLC using Ladder Diagram programming

language.

Truth Table relating BCD and Excess-3 codes

Decimal BCD inputs Excess-3 Code outputs
B3 B2 B1 B0 E3 E2 E1 E0
0 0 0 0 0 0 0 1 1
1 0 0 0 1 0 1 0 0
2 0 0 1 0 0 1 0 1
3 0 0 1 1 0 1 1 0
4 0 1 0 0 0 1 1 1
5 0 1 0 1 1 0 0 0
6 0 1 1 0 1 0 0 1
7 0 1 1 1 1 0 1 0
8 1 0 0 0 1 0 1 1
9 1 0 0 1 1 1 0 0
Boolean expression for each Excess-3 code bits
E3= m(5, 6, 7, 8, 9)
E2= m(1, 2, 3, 4, 9)
E1= m(0, 3, 4, 6, 7, 8)
E0= m(0, 2, 4, 6, 8)
Karnaugh-Map solution for each output

Realizing code conversion using Logic Gates

Ladder Logic
 PROGRAM 8
AIM: PLC program to impliment half adder.

THEORY:
A half adder is a type of adder, an electronic circuit that performs the addition of
numbers. The half adder is able to add two single binary digits and provide the output
plus a carry value. It has two inputs, called A and B, and two outputs S (sum) and C
(carry). The common representation uses a XOR logic gate and an AND logic gate

Half Adder truth table:s an example of a simple, functional digital circuit built from
two logic gates. The half adder

A(input) B (input) C (output) S (output)

 0 0 0 0

1 0 0 1

0 1 0 1

1 1 1 0

AND gate; thus, when voltage is applied A input of the XOR gate, the A input to the
AND gate same voltage.UTY

-down selector and view the resulting output.

CIRCUIT DIAGRAM:

K MAP:
Sum = A’B’C + AB’C’+ A’BC’ + ABC Cout = AB + AC +BC
 PROGRAM 9
AIM: PLC implementation of binary to grey conversion.

THEORY:
Binary to Gray Code Conversion

This conversion method strongly follows the EX-OR gate operation between binary
bits . The below steps & solved example may useful to know how to perform binary
to gray code conversion.

1. To convert binary to gray code, bring down the most siginificant digit of the given
binary number, because, the first digit or most siginificant digit of the gray code
number is same as the binary number.
2. To obtain the successive gray coded bits to produce the equivalent gray coded
number for the given binary, add the first bit or the most siginificant digit of binary to
the second one and write down the result next to the first bit of gray code, add the
second binary bit to third one and write down the result next to the second bit of gray
code, follow this operation until the last binary bit and write down the results based on
EX-OR logic to produce the equivalent gray coded binary.

Binary to Gray Code Converter

The logical circuit which converts the binary code to equivalent gray code is known
as binary to gray code converter. An n-bit gray code can be obtained by reflecting
an n-1 bit code about an axis after 2 n-1 rows and putting the MSB (Most Significant
Bit) of 0 above the axis and the MSB of 1 below the axis. Reflection of Gray codes is
shown below.
Ladder Logic
 PROGRAM 10

AIM: PLC implementation 2- bit comparator.

THEORY:
2-Bit Comparator

A 2-bit comparator compares two binary numbers, each of two bits and produces their
relation such as one number is equal or greater than or less than the other. The figure
below shows the block diagram of a two-bit comparator which has four inputs and
three outputs.

The first number A is designated as A = A1A0 and the second number is designated as
B = B1B0. This comparator produces three outputs as G (G = 1 if A>B), E (E = 1, if A
= B) and L (L = 1 if A<B).

TRUTH TABLE :
K MAP:

Ladder Logic
 PROGRAM 11
AIM: PLC program to implement 4*1 MUX.

THEORY:
Digital Multiplexer

Definition: Multiplexer is a combinational logic circuit which allows only one

input at a particular time to generate the output. The signals which control which
input will be reflected at the output end is determined by the SELECT INPUT lines.
A multiplexer is often written as MUX in the abbreviated form. It is also called as
Many-to-One circuit. This is because of its ability to select one signal out of many
inputs.

The MUX is the very crucial component of the communication system. This is
because, in such systems, we need to select a single channel from various other
channels. A multiplexer can be considered as a digitally controlled switch. The
controlling code which selects a particular input line can be given as binary input in
the form of selection line. The output will be one of the inputs given to MUX, which
is decided by selection lines.

Truth table

INPUT
DATA SELECT INPUTS INPUT OUTPUT
SELECTED

A B D D Z

0 0 D0 0 0
 1 1

0 1 D1 0 0

1 1

1 0 D2 0 0

1 1

1 1 D3 0 0

1 1

Ladder Logic
 PROGRAM 12
AIM: PLC program to implement 8*1 MUX.

THEORY:
8-to-1 Multiplexer

An 8-to-1 multiplexer consists of eight data inputs D0 through D7, three input select
lines S2 through S0 and a single output line Y. Depending on the select lines
combinations, multiplexer decodes the inputs.

The below figure shows the block diagram of an 8-to-1 multiplexer with enable input
that enable or disable the multiplexer. Since the number data bits given to the MUX
are eight then 3 bits (23=8) are needed to select one of the eight data bits.

The truth table for an 8-to1 multiplexer is given below with eight combinations of
inputs so as to generate each output corresponds to input.

For example, if S2= 0, S1=1 and S0=0 then the data output Y is equal to D2. Similarly
the data outputs D0 to D7 will be selected through the combinations of S2, S1 and S0
as shown in below figure.
From the above truth table, the Boolean equation for the output is given as

Ladder Logic
 PROGRAM 13
AIM: PLC program to implement 3*8 decoder.

THEORY:
3 Line to 8 Line Decoder
This decoder circuit gives 8 logic outputs for 3 inputs and has a enable pin. The
circuit is designed with AND and NAND logic gates. It takes 3 binary inputs and
activates one of the eight outputs. 3 to 8 line decoder circuit is also called as binary to
an octal decoder.

3 to 8 Line Decoder Block DiagramThe decoder circuit works only when the Enable
pin (E) is high. S0, S1 and S2 are three different inputs and D0, D1, D2, D3. D4. D5.
D6. D7 are the eight outputs.

Circuit Diagram
3 to 8 Decoder Circuit3 to 8 Line Decoder Truth Table
The below table gives the truth table of 3 to 8 line decoder.

S0 S1 S2 E D0 D1 D2 D3 D4 D5 D6 D7
x x x 0 0 0 0 0 0 0 0 0
0 0 0 1 0 0 0 0 0 0 0 1
0 0 1 1 0 0 0 0 0 0 1 0
0 1 0 1 0 0 0 0 0 1 0 0
0 1 1 1 0 0 0 0 1 0 0 0
1 0 0 1 0 0 0 1 0 0 0 0
1 0 1 1 0 0 1 0 0 0 0 0
1 1 0 1 0 1 0 0 0 0 0 0
1 1 1 1 1 0 0 0 0 0 0 0
When the Enable pin (E) is low all the output pins are low.

Ladder Logic
 Program – 14

Aim : PLC program to implement Grey to Binary code conversion.

Theory :
Gray Code to Binary Conversion
Gray code to binary conversion is a very simple and easy process.
Following steps can make your idea clear on this type of conversions.
1. The MSB of the binary number will be equal to the MSB of the given
gray code.
2. Now if the second gray bit is 0, then the second binary bit will be the
same as the previous or the first bit . If the gray bit is 1 the second
binary bit will alter. If it was 1 it will be 0 and if it was 0 it will be
1.
3. This step is continued for all the bits to do Gray code to binary
cconversion.
Ladder Logic
 Program – 15

Aim – PLC program to implement 1 * 8 De-Multiplexer .

Theory - DEMUX are used to implement general-purpose logic systems. A

demultiplexer takes one single input data line and distributes it to any one of a number
of individual output lines one at a time. Demultiplexing is the process of converting a
signal containing multiple analog or digital signals backs into the original and
separate signals. A demultiplexer of 2^n outputs has n select lines.
1-8 De-multiplexers
The demultiplexer is also called as data distributors as it requires one input, 3 selected
lines and 8 outputs. De-multiplexer takes one single input data line, and then switches
it to any one of the output line. 1-to-8 demultiplexer circuit diagram is shown below;
 PLC program for 1*8 de-multiplexer :

Ladder Logic
 Program – 16

Aim : PLC progam to implement 7 segment display.

Theory :
A seven-segment display (SSD), or seven-segment indicator, is a form of
electronic display device for displaying decimalnumerals that is an alternative to the
more complex dot matrix displays.
Seven-segment displays are widely used in digital clocks, electronic meters, basic
calculators, and other electronic devices that display numerical information.
Ladder Logic
 Program – 17

Aim : PLC program to operate a simple motor

Theory :
A motor which is started by pressing a button switch although the switch contact
does not remain closed . It is required that motor continues to run until a stop
button is pressed . It means the latching is used to stay motor run until the
push button is pressed again .
 Program – 18

Aim – PLC program to run a motor and ignite a lamp simultaneously .

 Program – 19

Aim – PLC program to implement the following conditions :

1.) Lamp glows when the motor starts .
2.) Lamp is off when the motor stops .
Theory :
When the input is given to motor drive , the motor starts and lamp glows
and after some time , when the motor stops, it should indicate that the lamp is off.
Two inputs are given :
A.) One for the motor start.
B.) Same for the motor stop.
And we obtain lamp glow in one condition and lamp off in other condition.

PROGRAM 20

AIM: Implementation of PLC program for given conditions.

PROGARM:
Input Switch 1 -> Motor 1, Motor 2 ON
Input Switch 2 - > Motor 3, Motor 4 ON
Input Switch 3 - > Motor 1, Motor 3 OFF
Input Switch 4 - > Motor 2, Motor 4 OFF

Ladder Logic
 PROGRAM 21

AIM: Implementation of PLC program for given conditions.

PROGARM:
A selection committee comprises of four members including the chairman.In order for
a candidate to be selected he or she has to have support of at least two members.The
chairman however , can post any candidate through.If each member is provided with a
switch design a logic that will ring a bell when candidate is selected.

SOLUTION:
Truth table

INPUTS OUTPUTS*
S1 (Chairman) S2 S3 S4 Selection
0 0 0 0 0
0 0 0 1 0
0 0 1 0 0
0 0 1 1 1
0 1 0 0 0
0 1 0 1 1
0 1 1 0 1
0 1 1 1 1
1 0 0 0 1
1 0 0 1 1
1 0 1 0 1
1 0 1 1 1
1 1 0 0 1
1 1 0 1 1
1 1 1 0 1
1 1 1 1 1

*Bell rings when Output (Selection) is ‘1’.

K-Map
 Selection = S2S3 + S2S4 + S3S4 + S1

Ladder Logic

PROGRAM 22
AIM: Implementation of PLC program for a 1:4 DEMUX.
PROGARM:
Design a 1:4 DEMUX using the ladder logic.Assume the input are connected to input
control signals and the output terminals.

SOLUTION:
Truth table

Ladder Logic
 PROGRAM 23

AIM: Implementation of PLC program for given conditions.

PROGARM:

INPUT OUTPUT
ON OFF
1 1 2,3,4
2 2 1,3,4
3 3 1,2,4
4 4 1,2,3
5 ALL

SOLUTION:
Ladder Logic
 PROGRAM 24

AIM: Implementation of PLC program for given conditions.

PROGARM:

INPUT OUTPUT
1 1,2,3 ON
2 1 OFF
3 2 OFF
4 3 OFF

SOLUTION:
Ladder Logic
 PROGRAM 25

AIM: Implementation of PLC program for given conditions.

PROGARM:
INPUT OUTPUT
1 1,2 ON
2 3,4 ON
3 1,3 OFF
4 2,4 OFF

SOLUTION:
Ladder Logic
 PROGRAM 26

AIM: Implementation of PLC program for given conditions.

PROGARM:
INPUT OUTPUT
0,1,2 Q0.0 (ON)
3,4,5 Q0.0 (OFF)

SOLUTION:
Ladder Logic
*CPU_Input7 is used as a reset bit.
 Program 27

Aim: To implement given conditions on a PLC.

Program:

Input Output

I0.1 L1 (ON)

I0.2 L1,L2 (ON)

I0.3 L1,L2,L3 (ON)

I0.4 Reset all

Solution:

Ladder Logic
 Program 28

Aim: To implement basic Timer Circuit (Ton)

Theory:
PLC timers are instructions that provide the same functions as on-delay and off-delay
mechanical and electronic timing relays. A PLC timer provides a preset delay to the
control actions.

In general, there are three types of PLC timer delays, ON-delay timer, OFF-delay
timer and retentive timer on.

The terms represented in the timer block in the PLC are a Preset value which means
the delay period of the timer, an Accumulated value which is the current delay of the
timer.

A timer begins the counting on time-based intervals and continues until the
accumulated value equals the preset value. When the accumulated value equals the
preset time the output will be energized. Then the timer sets the output.

TON timer or ON delay timer

An ON delay timer is used where we need a time delay before the time delay before
an instruction becomes true.

A representation TON timer is shown above, which contains,

Timer number: The timer file name

Time base: which is shown in seconds,
Preset value: Numeric valve set as the delay required to the timer.
Accumalated value: The values are counting is displayed from zero. Value becomes
 zero whenever the timer is reset

 The timer starts operating when the rung condition becomes true.

The timer delay starts counting when the rung condition starts to

accumulate.

 When the Preset value becomes equal to the accumulated value,

the output is made true.

 The timed output becomes true sometime after the timer rung

becomes true; hence, the timer is said to have an on-delay.

 The length of the delay can be adjusted by setting the preset

value.
Program:
Turn on an output light, 5 seconds after switch is turned on.
Solution:
Ladder Logic
 Program 29
Aim: To implement basic Timer Circuit (TOFF).
Theory:

TOFF timer or OFF delay timer:

A TOFF timer will keep the output energized for a preset time after the rung signal
has gone false.

The TOFF timer will have all the contents as in the TON timer, with the similar
function.
 When the rung timer is true, the output will be true without any delay. When
the rung signal becomes false the timer starts operating.

 The timer starts accumulating times when the rung condition becomes true,
until the accumulated value becomes equal to the Preset value.

 The output turns off when the output will turn false when the accumulated
value equals the preset value.

Solution:

Ladder Logic:
 Program 30

Aim: To implement TOFF Timer Circuit using TON Timer Circuit.

Solution:

Ladder Logic:
 Program 31

Aim: To implement given conditions on a PLC.

Program:
 LED ON after

1 2 seconds

2 4 seconds

3 6 seconds

4 8 seconds

Solution:

Ladder Logic
 Program 32

Aim: To implement given conditions on a PLC.

Program:

There are 4 LED’s which get ON after interval of 2 seconds consecutively

and LED which glows first gets OFF after the next LED gets ON.

LED ON after

1 2 seconds

2 4 seconds

3 6 seconds

4 8 seconds
Solution:

Ladder Logic
 Program 33

Aim: To implement given conditions on a PLC.

Program:

SEQUENCE OUTPUT

2 seconds after input is triggered L1,L2,L3,L4 ON

2 seconds further L1 OFF

2 seconds further L2 OFF

2 seconds further L3 OFF

2 seconds further L4 OFF

Solution:

Ladder Logic
 Program 34

Aim: To implement given conditions on a PLC.

Program:

There are 6 LED’s namely L 1,L2,L3,L4,L5 and L6 and they follow a certain

sequence after an input is triggered.

SEQUENCE OUTPUT

2 seconds after input is triggered L1,L2 ON

2 seconds further L3,L4 ON

2 seconds further L5,L6 ON

 2 seconds further L1,L2,L3 OFF

2 seconds further L2,L4,L6 OFF

2 seconds further All ON

2 seconds further All OFF

Solution:

Ladder Logic
 Program 35

Aim: To implement given conditions on a PLC.

There are 3 motors namely M1,M2 and M3.

M1 starts as soon as switch is on and after 10 seconds M1 goes off and

simultaneously M2 starts and after 5 seconds M2 goes off and

simultaneously M3 starts and after 10 seconds M3 goes off and M1 starts

again and cycle is repeated.

Solution:

Ladder Logic
 Program 36

Aim: To implement 2 pole traffic light signal system on PLC.

Program: There is a 2 pole traffic light system having 3 status LED’s.

Solution:

Ladder Logic
 Program 37

Aim: To implement 4 pole traffic light signal system on PLC.

Program: There is a 4 pole traffic light system having 2 status LED’s.

Solution:

Ladder Logic
 Program 38

Aim: To implement given conditions on a PLC

Theory:
A pulse is a burst of current, voltage, or electromagnetic-field energy. In practical
electronic and computer systems, a pulse may last from a fraction of a nanosecond up
to several seconds or even minutes. In digital systems, pulses comprise brief bursts of
DC (direct current) voltage, with each burst having an abrupt beginning (or rise) and
an abrupt ending (or decay).

Program:

Input No. Of pulses to trigger Output

output

1 5 1,2 ON

2 4 3,4 ON

3 3 All OFF

Solution:

Ladder Logic
 Program 39

Aim: To implement a car parking system on a PLC.

Program:

There are 15 parking slots in a building and there are 2 status LED’s both

on the entrance and exit.

LED STATUS

Red No parking space available

Green Parking space available

Solution:

Ladder Logic
 Program 40

Aim: To implement a pulse counter on a PLC.

Theory:

Duty Cycle

When the signal is high, we call this "on time". To describe the amount of "on time" ,
we use the concept of duty cycle. Duty cycle is measured in percentage. The
percentage duty cycle specifically describes the percentage of time a digital signal is
on over an interval or period of time. This period is the inverse of the frequency of the
waveform.
If a digital signal spends half of the time on and the other half off, we would say the
digital signal has a duty cycle of 50% and resembles an ideal square wave. If the
percentage is higher than 50%, the digital signal spends more time in the high state
than the low state and vice versa if the duty cycle is less than 50%. Here is a graph
that illustrates these three scenarios:
50%, 75%, and 25% Duty Cycle Examples

100% duty cycle would be the same as setting the voltage to 5 Volts (high). 0% duty
cycle would be the same as grounding the signal.

Program:

Implement a pulse counter with 50% duty cycle up to 10 pulses.

Solution:

Ladder Logic
Program 41
Aim: To implement given conditions on a PLC.

Program:

In a class with seating capacity of 20 there are 3 status LED’s

LED Status

RED ON till the class is full

GREEN ON when class gets full ; Initially Off;

Remains ON for 10 seconds provided

20 students remain in the class then

gets turned OFF.

YELLOW Gets turned ON after green LED is

OFF ; Remains ON for 15 seconds and

then gets turned OFF.

Solution:

Ladder Logic
 s Program 42

Aim: To implement given conditions on a PLC.

Program:

Solution:

Ladder Logic
 Program 43

Aim: To implement given conditions on a PLC.

Program:

SEQUENCE OUTPUT

2 seconds after input is triggered L1,L6 ON

2 seconds further L2,L5 ON

2 seconds further L3,L4 ON

2 seconds further All OFF

*Sequence repeats three times.

Ladder Logic
 Program 44
Aim: To implement given conditions on a PLC.
Program:

SEQUENCE OUTPUT
2 seconds after input is triggered L1 ON
2 seconds further L2 ON
2 seconds further L3 ON
2 seconds further L4 ON
2 seconds further L5 ON

*Sequence is repeated 3 times.

*4th time all the output’s are turned off.
*Repeat the process from beginning.
Solution:
Ladder logic
 Program 45

Aim: To implement washing machine on a PLC.

Program:
SEQUENCE OUTPUT
As soon as input is triggered Water inlet
2 seconds further Surf inlet
2 seconds further Forward (10 times alternatively)
Backward (10 times alternatively)

20 seconds further Drain

5 seconds further Spin

10 seconds further Off

Solution:

Ladder logic
 Program 46

Aim: To implement given conditions on a PLC.

Program:

Solution:

Ladder logic
 Program 47

Aim: To implement given conditions on a PLC.

Program:

Ladder logic