UNIVERSIDAD NACIONAL MAYOR DE SAN MARCOS

(Universidad del Perú, Decana de América)

Circuitos Digitales

TEMA : TRABAJO DE VHDL

PROFESOR : Ing. Alarcón Matutti, Rubén

ALUMNO: Corbera Ramos José Carlos

CODIGO: 12190007
2.47 a) Escriba el código VHDL para describir las funciones siguientes:

𝑓1 = 𝑥1 . ̅̅̅
𝑥3 + 𝑥2 . ̅̅̅
𝑥3 + ̅̅̅.
𝑥3 ̅̅̅
𝑥4 + 𝑥1 . 𝑥2 + 𝑥1 . ̅̅̅
𝑥4

𝑓2 = (𝑥1 + ̅̅̅).
𝑥3 (𝑥1 + 𝑥2 + ̅̅̅).
𝑥4 (𝑥2 + ̅̅̅
𝑥3 + ̅̅̅)
𝑥4

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

entity numero is

port( x1:in STD_LOGIC;

x2:in STD_LOGIC;

x3:in STD_LOGIC;

x4:in STD_LOGIC;

f1,f2:OUT STD_LOGIC);
end numero;

architecture dataflow of numero is

signal s1,s2,s3,s4,s5,s6,s7,s8: STD_LOGIC;

constant gate_delay: Time:=5 ns;

begin

L1:s1<=x1 and (not x3) after gate_delay;

L2:s2<=x1 and x2 after gate_delay;

L3:s3<=x2 and (not x3) after gate_delay;

L4:s4<=(not x3) and (not x4)after gate_delay;

L5:s5<=x1 and (not x4)after gate_delay;

L6:s6<=s1 or s2 after gate_delay;

L7:s7<=s3 or s4 after gate_delay;

L8:s8<=s7 or s5 after gate_delay;

L9:f1<=s8 or s6 after gate_delay;

f2<=(x1 or(not x3))and(x1 or x2 or(not x4))and(x2 or(not x3) or(not x4));

end dataflow;

b) Use simulación funcional para probar que 𝑓1 = 𝑓2

2.48 Considere las instrucciones siguientes de asignación en VHDL

F1<=((x1 and x3)or(not x1 and not x3))or((x2 and x4)or(not x2 and not x4));

F2<=(x1 and x2 and not x3 and not x4)or(not x1 and not x2 and x3 and x4)

or(x1 and not x2 and not x3 and x4)or(not x1 and x2 and x3 and not x4);

a) Escriba el código VHDL para describir las funciones:

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

entity problema2 is

port( x1:in STD_LOGIC;

x2:in STD_LOGIC;
 x3:in STD_LOGIC;

x4:in STD_LOGIC;

F1,F2:OUT STD_LOGIC);

end problema2;

architecture behavioral of problema2 is

begin

F1<=((x1 and x3)or(not x1 and not x3))or((x2 and x4)or(not x2 and not x4));

F2<=(x1 and x2 and not x3 and not x4)or(not x1 and not x2 and x3 and x4)

or(x1 and not x2 and not x3 and x4)or(not x1 and x2 and x3 and not x4);

end behavioral;

b) Use simulación funcional para comprobar que 𝑓1 = 𝑓̅2

4.38. Escriba el codigo VHDL para implementar la siguiente función

𝑓(𝑥1 … 𝑥4 ) = ∑ 𝑚(0,1,2,4,5,7,8,9,11,12,14,15)
library ieee;

use ieee.std_logic_1164.all;

use ieee.std_logic_unsigned.all;

use ieee.std_logic_arith.all;

entity problema33 is

port( x : in std_logic_vector(3 downto 0);

F : out std_logic_vector (0 downto 0));

end problema33 ;

architecture behavioral of problema33 is

begin

with x select F<="1" when "0000",

"1" when "0001",

"1" when "0010",

"1" when "0100",

 "1" when "0101",

"1" when "0111",

"1" when "1000",

"1" when "1001",

"1" when "1011",

"1" when "1110",

"1" when "1111",

"0" when others;

end behavioral;

4.39. Escriba el codigo VHDL para implementar la siguiente función

𝑓(𝑥1 … 𝑥4 ) = ∑ 𝑚(1,4,7,14,15) + 𝐷(0,5,9)

𝑓1 =. ̅̅̅.
𝑥1 ̅̅̅
𝑥3 + 𝑥2 . 𝑥3 . 𝑥4 + 𝑥1 . 𝑥2 . 𝑥3
library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

entity problema9 is

port( x1:in STD_LOGIC;

x2:in STD_LOGIC;

x3:in STD_LOGIC;

x4:in STD_LOGIC;

F1:OUT STD_LOGIC);

end problema9;

architecture behavioral of problema9 is

begin

F1<=((not x1) and (not x3))or( x2 and x3 and x4)or(x1 and x2 and x3);

end behavioral;
4.40 Escriba el codigo VHDL para implementar la siguiente función

𝑓(𝑥1 … 𝑥4 ) = ∏ 𝑀(6,8,9,12,13)

library ieee;

use ieee.std_logic_1164.all;

use ieee.std_logic_unsigned.all;

use ieee.std_logic_arith.all;

entity problema4 is

port( x : in std_logic_vector(3 downto 0);

 F : out std_logic_vector (0 downto 0));

end problema4 ;

architecture behavioral of problema4 is

begin

with x select F<="1" when "0000",

"1" when "0001",

"1" when "0010",

"1" when "0011",

"1" when "0100",

"1" when "0101",

"1" when "0111",

"1" when "1010",

"1" when "1011",

"1" when "1110",

"1" when "1111",

"0" when others;

end behavioral;

4.41. Escriba el codigo VHDL para implementar la siguiente función

 𝑓(𝑥1 … 𝑥4 ) = ∏ 𝑀(3,11,14) + 𝐷(0,2,10,12)

𝑓1 = ( 𝑥2 + ̅̅̅)(𝑥
𝑥3 ̅̅̅1̅ + ̅̅̅
𝑥2 +𝑥4 ))

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

entity problema10 is

port( x1:in STD_LOGIC;

x2:in STD_LOGIC;

x3:in STD_LOGIC;

x4:in STD_LOGIC;

F1:OUT STD_LOGIC);

end problema10;

architecture behavioral of problema10 is

begin

F1<=(x2 and (not x3)) or ( (not x1) and (not x2) and x4);

end behavioral;
 COMENTARIOS

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

Son las librerías a usarse para evocar los respectivos operadores lógicos

entity problema10 is

Se le asigna el nombre a la función lógica

port( x1:in STD_LOGIC;

x2:in STD_LOGIC;

x3:in STD_LOGIC;

x4:in STD_LOGIC;

F1:OUT STD_LOGIC);

La instrucción port especifica las entradas y salidas

Luego viene la segunda parte que es la arquitectura que sirve para describir la operación
interna de la función lógica

architecture behavioral of problema10 is

begin
F1<=(x2 and (not x3)) or ( (not x1) and (not x2) and x4);

end behavioral;