UG6165 Ibuttom para Autoclave

DS1922F Autoclave Temperature Logger
with 8KB Data-Log Memory Developer Guide
General Description Benefits and Features

The iButton® autoclave temperature logger (DS1922F*) is ●● Verifies Autoclave Sterilization Time and Temperature
a rugged, self-sufficient solution ideal for the extreme heat • Automatically Measures and Stores Temperature
and humidity of autoclave applications. Temperature data and Time Readings
is recorded at a user-defined rate and stored in password- • Withstands Harsh Autoclave Sterilization Cycles
protected memory to prevent tampering. A total of 8192 ●● Simplifies Record Keeping by Eliminating Paper Log
8-bit readings or 4096 16-bit readings, taken at equidis- Books and Printouts
tant intervals ranging from 1s to 273hr, can be stored. • Programmable Operation and Results Uploading
Additionally, 512 bytes of SRAM store application-specific Using Companion PC Software
information and 64 bytes store calibration data. A mission ●● Precalibrated and Easy to Use
to collect data can be programmed to begin immediately, • Precalibrated to NIST Traceable References
after a user-defined delay, or after a temperature alarm. • Compatible with Any Steam-Sterilization Autoclave
Access to the memory and control functions can be pass- Cycle Duration with Temperature Up to +140°C
word protected. The DS1922F is configured and commu- • Typically 150 Uses Before Replacement
nicates with a host-computing device through the serial
1-Wire® protocol, which requires only a single data lead ●● Supplement to Biological Indicators
• Use the DS1922F as an Instant Proxy Indicator
and a ground return. Every DS1922F is factory lasered
While Waiting on Spore Test Results
with a guaranteed unique 64-bit registration number that
allows for traceability.
Applications
●● High-Temperature Logging (Process Monitoring,
Industrial Temperature Monitoring)
●● Steam Sterilization
iButton and 1-Wire are registered trademarks of Maxim Integrated

Products, Inc.
*FDA and CE certifications pending. Pin Configuration appears at end of data sheet.
19-7599; Rev 1; 5/15

Absolute Maximum Ratings

IO Voltage Range to GND .......................................-0.3V to +6V Junction Temperature......................................................+150°C
IO Sink Current...................................................................20mA Storage Temperature Range............................-25°C to +140°C*
Operating Temperature Range ........................+15°C to +140°C
*Storage or operation above +50°C significantly reduces battery life with an upper limit of 100hr cumulative at +140°C. The recom-
mended storage temperature for maximum battery lifetime is between +5°C and +35°C.
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these
or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect
device reliability.
Electrical Characteristics
(VPUP = 3.0V to 5.25V, unless otherwise noted.)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

Operating Temperature TA DS1922F (Note 1) +15 +140 °C
I/O PIN GENERAL DATA
1-Wire Pullup Resistance RPUP (Notes 2, 3) 2.2 kΩ
Input Capacitance CIO (Note 4) 100 800 pF
Input Load Current IL I/O pin at VPUP 6 10 µA
High-to-Low Switching Threshold VTL (Notes 5, 6) 0.4 3.2 V
Input Low Voltage VIL (Notes 2, 7) 0.3 V
Low-to-High Switching Threshold VTH (Notes 5, 8) 0.7 3.4 V
Switching Hysteresis VHY (Note 9) 0.09 N/A V
Output Low Voltage VOL At 4mA (Note 10) 0.4 V
Standard speed, RPUP = 2.2kΩ 5
Recovery Time Overdrive speed, RPUP = 2.2kΩ 2
tREC µs
(Note 2) Overdrive speed, directly prior to reset
5
pulse; RPUP = 2.2kΩ
Rising-Edge Hold-Off Time tREH (Note 11) 0.6 2.0 µs
Standard speed 65
Time Slot Duration (Note 2) tSLOT Overdrive speed, VPUP > 4.5V 8 µs
Overdrive speed 9.5
I/O PIN 1-Wire RESET, PRESENCE-DETECT CYCLE
Standard speed, VPUP > 4.5V 480 720
Standard speed 690 720
Reset Low Time (Note 2) tRSTL µs
Overdrive speed, VPUP > 4.5V 48 80
Overdrive speed 70 80
Presence-Detect High Time tPDH Standard speed 15 63.5 µs
Overdrive speed 2 7
www.maximintegrated.com Maxim Integrated │ 2

Electrical Characteristics (continued)

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

Standard speed, VPUP > 4.5V 1.5 5
Presence-Detect Fall Time
tFPD Standard speed 1.5 8 µs
(Note 12)
Overdrive speed 0.15 1
Presence-Detect Low Time tPDL µs
Overdrive speed, VPUP > 4.5V 7 24
Overdrive speed 7 28
Presence-Detect Sample Time
tMSP Standard speed 71.5 75 µs
(Note 2)
Overdrive speed 8 9
I/O PIN 1-Wire WRITE
Write-Zero Low Time
tW0L Overdrive speed, VPUP > 4.5V 6 12 µs
(Notes 2, 13)
Overdrive speed 7.5 12
Write-One Low Time Standard speed 5 15
tW1L µs
(Notes 2, 13) Overdrive speed 1 1.95
I/O PIN 1-Wire READ
Read Low Time Standard speed 5 15 - d
tRL µs
(Notes 2, 14) Overdrive speed 1 1.95 - d
Read Sample Time Standard speed tRL + d 15
tMSR µs
(Notes 2, 14) Overdrive speed tRL + d 1.95
REAL-TIME CLOCK (RTC)
See the RTC Accuracy Min/
Accuracy
graph Month
Frequency Deviation DF 0°C to +125°C -600 +60 ppm
TEMPERATURE CONVERTER
Conversion Time 8-bit mode 30 75
tCONV ms
(Note 15) 16-bit mode (11 bits) 240 600
Conversion Error Without Software +15°C to +130°C (Note 18) ±7.7
Dq %
Correction (Notes 16, 17) +130°C to +140°C ±1.4
Conversion Error With Software +15°C to +130°C (N/A)
Dq %
Correction (Notes 17, 19) +115°C to +140°C ±1
Cycle = ramp from +25°C to > +135°C and
Temperature Cycles NTCY 150 Cycles
back to +25°C (Note 20)

Electrical Characteristics (continued)

Note 1: Operation above +125°C is restricted to mission operations only. Communication and 1-Wire pin specifications are not
specified for operation above +125°C.
Note 2: System requirement.
Note 3: Maximum allowable pullup resistance is a function of the number of 1-Wire devices in the system and 1-Wire recovery
times. The specified value here applies to systems with only one device and with the minimum 1-Wire recovery times. For
more heavily loaded systems, an active pullup such as that in the DS2480B can be required.
Note 4: Capacitance on the data pin could be 800pF when VPUP is first applied. If a 2.2kΩ resistor is used to pull up the data line
2.5μs after VPUP has been applied, the parasite capacitance does not affect normal communications.
Note 5: VTL and VTH are a function of the internal supply voltage, which is a function of VPUP and the 1-Wire recovery times. The
VTH and VTL maximum specifications are valid at VPUPMAX (5.25V). In any case, VTL < VTH < VPUP.
Note 6: Voltage below which, during a falling edge on I/O, a logic 0 is detected.
Note 7: The voltage on I/O must be less than or equal to VILMAX whenever the master drives the line low.
Note 8: Voltage above which, during a rising edge on I/O, a logic 1 is detected.
Note 9: After VTH is crossed during a rising edge on I/O, the voltage on I/O must drop by VHY to be detected as logic 0.
Note 10: The I-V characteristic is linear for voltages less than 1V.
Note 11: The earliest recognition of a negative edge is possible at tREH after VTH has been previously reached.
Note 12: Interval during the negative edge on I/O at the beginning of a presence-detect pulse between the time at which the voltage
is 90% of VPUP and the time at which the voltage is 10% of VPUP.
Note 13: ε in Figure 13 represents the time required for the pullup circuitry to pull the voltage on I/O up from VIL to VTH. The actual
maximum duration for the master to pull the line low is tW1LMAX + tF - ε and tW0LMAX + tF - ε, respectively.
Note 14: δ in Figure 13 represents the time required for the pullup circuitry to pull the voltage on I/O up from VIL to the input high
threshold of the bus master. The actual maximum duration for the master to pull the line low is tRLMAX + tF.
Note 15: To conserve battery power, use 8-bit temperature logging whenever possible.
Note 16: Includes +0.1°C/-0.2°C calibration chamber measurement uncertainty.
Note 17: Not for use outside of autoclave steam sterilizer applications. This product has not been tested to work with other types
of sterilizers including, but not limited to, chemiclaves or steam sterilizers that operate over 140°C and 2atm. As the prod-
uct does not record humidity or pressure, the user shall periodically assure that the autoclave is running properly and in
accordance with regulatory or trade group guidelines by using recommended tests that measure temperature, time, humid-
ity, and pressure. Per each sterilizer cycle, the user shall assure that redundant, or other primary, methods of testing and
determining the compliance of the sterilization cycle are implanted to mitigate risk. Data-logger products are 100% tested
and calibrated at time of manufacture by Maxim to ensure that they meet all data sheet parameters, including temperature
accuracy. User shall be responsible for proper use and storage of this product.
Note 18: Guaranteed by design and not production tested.
Note 19: Assumes using calibration memory with calibration equations for error compensation. Includes +0.1/-0.2°C calibration
chamber measurement uncertainty. Guaranteed by design.
Note 20: Devices leave the factory after having been run through a few cycles above +125°C. This is required for calibration of
the device but should not affect lifetime of the device as specified. However, this process results in a nonzero value in
the Device Samples Counter register (0223h–0225h), which provides evidence the device has been factory calibrated.
Operating lifetime is specified for sample rates up to 30s.
iButton is a registered trademarks of Maxim Integrated Products, Inc.

Physical Specification
SIZE See the Package Information section.
WEIGHT Ca. 16.9 grams
RTC Accuracy
RTC ACCURACY (TYPICAL)

2
-2
-4
DRIFT (MINUTES/MONTH)
-6
-8
-10
-12
-14
-16
-18
15 25 35 45 55 65 75 85 95 105 115 125 135
TEMPERATURE (°C)

Detailed Description a ROM function command is successfully executed, the

The DS1922F is well suited to monitor and record the memory and control functions become accessible and
temperature profile applied within an autoclave steam the master can provide any one of the eight available
sterilization oven. The watertight enclosure is designed, commands. The protocol for these memory and control
but not formally rated to IP68. Refer to Application Note function commands is described in Figure 9. All data is
4126: Understanding the IP (Ingress Protection) Ratings read and written least significant bit first.
of iButton Data Loggers and Capsules. Parasite Power
All iButton data loggers are calibrated/validated against The block diagram (Figure 1) shows the parasite-powered
NIST traceable reference devices. Maxim offers a web circuitry. This circuitry “steals” power whenever the I/O
application to generate validation certificates for all Maxim input is high. I/O provides sufficient power as long as
Integrated temperature data loggers. Input is the iButton the specified timing and voltage requirements are met.
device’s ROM code (or list of codes) and the output is a The advantages of parasite power are twofold: 1) By
validation certificate in PDF format. For more information, drawing from this input, battery power is not consumed
refer to Application Note 4629: iButton® Data-Logger for 1-Wire ROM function commands, and 2) if the bat-
Calibration and NIST Certificate FAQs. tery is exhausted for any reason, the ROM can still be
read normally. The remaining circuitry of the DS1922F is
Overview
solely operated by battery energy. As a consequence, if
The block diagram in Figure 1 shows the relationships the battery is exhausted, all memory data is lost including
between the major control and memory sections of the the data of the last mission, and no new mission can be
DS1922F. The device has six main data components: started. Refer to Application Note 5057: OneWireViewer
64-bit lasered ROM; 256-bit scratchpad; 512-byte gen- Tips and Tricks for how to check the battery status.
eral- purpose SRAM; two 256-bit register pages of
timekeeping, control, status, and counter registers, and 64-Bit Lasered ROM
passwords; 64 bytes of calibration memory; and 8192 Each DS1922F contains a unique ROM code that is 64
bytes of data-logging memory. Except for the ROM and bits long. The first 8 bits are a 1-Wire family code. The
the scratchpad, all other memory is arranged in a single next 48 bits are a unique serial number. The last 8 bits
linear address space. The data-logging memory, counter are a cyclic redundancy check (CRC) of the first 56 bits
registers, and several other registers are read only for the (see Figure 3 for details). The 1-Wire CRC is generated
user. Both register pages are write protected while the using a polynomial generator consisting of a shift register
device is programmed for a mission. The password regis- and XOR gates as shown in Figure 4. The polynomial is
ters, one for a read password and another one for a read/ X8 + X5 + X4 + 1. Additional information about the 1-Wire
write password, can only be written, never read. CRC is available in Application Note 27: Understanding
Figure 2 shows the hierarchical structure of the 1-Wire and Using Cyclic Redundancy Checks with Maxim 1-Wire
protocol. The bus master must first provide one of the and iButton Products.
eight ROM function commands: Read ROM, Match The shift register bits are initialized to 0. Then, starting
ROM, Search ROM, Conditional Search ROM, Skip with the least significant bit of the family code, one bit at
ROM, Overdrive-Skip ROM, Overdrive-Match ROM, or a time is shifted in. After the 8th bit of the family code has
Resume. Upon completion of an Overdrive ROM com- been entered, the serial number is entered. After the last
mand executed at standard speed, the device enters bit of the serial number has been entered, the shift regis-
overdrive mode, where all subsequent communication ter contains the CRC value. Shifting in the 8 bits of CRC
occurs at a higher speed. The protocol required for these returns the shift register to all 0s.
ROM function commands is described in Figure 11. After

ROM 64-BIT
PARASITE-POWERED
1-Wire PORT I/O FUNCTION LASERED
CIRCUITRY
CONTROL ROM
MEMORY 256-BIT
FUNCTION SCRATCHPAD
3V LITHIUM CONTROL
DS1922F
GENERAL-PURPOSE
SRAM (448 BYTES)
DEVICE-SIGNATURE
CONFIGURATON
(64 BYTES)
32.768kHz INTERNAL
OSCILLATOR TIMEKEEPING, REGISTER PAGES
CONTROL REGISTERS, (64 BYTES)
AND COUNTERS
THERMAL CALIBRATION MEMORY

ADC
SENSE (64 BYTES)
CONTROL DATA-LOG MEMORY

LOGIC 8KB
Figure 1. Block Diagram

BUS 1-Wire NET

OTHER DEVICES
MASTER
DS1922F
COMMAND LEVEL: AVAILABLE COMMANDS: DATA FIELD AFFECTED:

READ ROM 64-BIT ROM, RC-FLAG
MATCH ROM 64-BIT ROM, RC-FLAG
SEARCH ROM 64-BIT ROM, RC-FLAG
1-Wire ROM CONDITIONAL SEARCH ROM 64-BIT ROM, RC-FLAG, ALARM FLAGS, SEARCH CONDITIONS
FUNCTION COMMANDS SKIP ROM RC-FLAG
RESUME RC-FLAG
OVERDRIVE-SKIP ROM RC-FLAG, OD-FLAG
OVERDRIVE-MATCH ROM 64-BIT ROM, RC-FLAG, OD-FLAG
WRITE SCRATCHPAD 256-BIT SCRATCHPAD, FLAGS

READ SCRATCHPAD 256-BIT SCRATCHPAD
COPY SCRATCHPAD WITH PW 512-BYTE DATA MEMORY, REGISTERS, FLAGS, PASSWORDS
DS1922F-SPECIFIC READ MEMORY WITH PW AND CRC MEMORY, REGISTERS, PASSWORDS
MEMORY/CONTROL CLEAR MEMORY WITH PW MISSION TIMESTAMP, MISSION SAMPLES COUNTER,
FUNCTION COMMANDS START DELAY, ALARM FLAGS, PASSWORDS
FORCED CONVERSION MEMORY ADDRESSES 020Ch TO 020Dh
START MISSION WITH PW FLAGS, TIMESTAMP, MEMORY ADDRESSES
020Ch TO 020Dh (WHEN LOGGING)
STOP MISSION WITH PW FLAGS
Figure 2. Hierarchical Structure for 1-Wire Protocol
MSB LSB
8-BIT 8-BIT FAMILY CODE

48-BIT SERIAL NUMBER
CRC CODE (41h)
MSB LSB MSB LSB MSB LSB
Figure 3. 64-Bit Lasered ROM
POLYNOMIAL = X8 + X5 + X4 + 1
1ST 2ND 3RD 4TH 5TH 6TH 7TH 8TH

STAGE STAGE STAGE STAGE STAGE STAGE STAGE STAGE
X0 X1 X2 X3 X4 X5 X6 X7 X8
INPUT DATA
Figure 4. 1-Wire CRC Generator

Memory temperature readings. See the Software Correction

Figure 5 shows the DS1922F memory map. Pages 0 to 13 Algorithm for Temperature section for details. The last
contain 448 bytes of general-purpose SRAM. The device byte of the calibration memory page stores an 8-bit CRC
signature configuration is held in pages 14 and 15, called of the preceding 31 bytes. Page 19 is an exact copy of
device signature configuration pages 1 and 2. Contact the data in page 18. While calibration memory can be
factory for additional details. The various registers to set overwritten by the user, this is not recommended. See
up and control the device fill pages 16 and 17, called the Security by Password section for ways to protect
register pages 1 and 2 (see Figure 6 for details). Pages the memory. The access type for the register pages is
18 and 19 provide storage space for calibration data. register-specific and depends on whether the device is
The data-log logging memory starts at address 1000h programmed for a mission. Figure 6 shows the details.
(page 128) and extends over 256 pages. The memory The data-log memory is read only for the user. It is written
pages 20 to 127 are reserved for future extensions. The solely under supervision of the on-chip control logic. Due
scratchpad is an additional page that acts as a buffer to the special behavior of the write access logic (write
when writing to the SRAM memory or the register pages. scratchpad, copy scratchpad), it is recommended to only
The data memory can be written at any time. The calibra- write full pages at a time. This also applies to the regis-
tion memory holds data from the device calibration that ter pages and the calibration memory. See the Address
can be used to further improve the accuracy of 11-bit Registers and Transfer Status section for details.
32-BYTE INTERMEDIATE STORAGE

SCRATCHPAD
ADDRESS
32-BYTE GENERAL-PURPOSE SRAM
0000h TO 001Fh PAGE 0
(R/W)
0020h TO 01BFh GENERAL-PURPOSE SRAM (R/W) PAGES 1 TO 13
32-BYTE DEVICE SIGNATURE

01C0 TO 01DFh PAGE 14
CONFIGURATION PAGE 1
32-BYTE DEVICE SIGNATURE
01E0 TO 01FFh PAGE 15
CONFIGURATION PAGE 2
0200h TO 021Fh 32-BYTE REGISTER PAGE 1 PAGE 16
0220h TO 023Fh 32-BYTE REGISTER PAGE 2 PAGE 17
0240h TO 025Fh CALIBRATION MEMORY PAGE 1 (R/W) PAGE 18
0260h TO 027Fh CALIBRATION MEMORY PAGE 2 (R/W) PAGE 19
0280h TO 0FFFh (RESERVED FOR FUTURE EXTENSIONS) PAGES 20 TO 127
1000h TO 2FFFh DATA-LOG MEMORY (READ ONLY) PAGES 128 TO 383
Figure 5. Memory Map

ADDRESS BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 FUNCTION ACCESS*
0200h 0 10 Seconds Single Seconds
0201h 0 10 Minutes Single Minutes
20 Hour
0202h 0 12/24 10 Hour Single Hours Real-
AM/PM
Time Clock R/W R
0203h 0 0 10 Date Single Date Registers
10
0204h CENT 0 0 Single Months
Months
0205h 10 Years Single Years
0206h Low Byte Sample
R/W R
0207h 0 0 High Byte Rate
0208h Low Threshold Temperature
R/W R
0209h High Threshold Alarms
020Ah (No Function with the DS1922F)
— R/W R
020Bh (No Function with the DS1922F)
020Ch Low Byte 0 0 0 0 0 Latest
R R
020Dh High Byte Temperature
020Eh (No Function with the DS1922F)
— R R
020Fh (No Function with the DS1922F)
Temperature
0210h 0 0 0 0 0 0 ETHA ETLA R/W R
Alarm Enable
0211h 1 1 1 1 1 1 0 0 — R/W R
0212h 0 0 0 0 0 0 EHSS EOSC RTC Control R/W R
Mission
0213h 1 1 SUTA RO (X) TLFS 0 ETL R/W R
Control
0214h BOR 1 1 1 0 0 THF TLF Alarm Status R R
General
0215h 1 1 0 WFTA MEMCLR 0 MIP 0 R R
Status
0216h Low Byte Start
0217h Center Byte Delay R/W R
0218h High Byte Counter
*The left entry in the ACCESS column is valid between missions. The right entry shows the applicable access type while a
mission is in progress.
Figure 6. DS1922F Register Pages Map

ADDRESS BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 FUNCTION ACCESS*
021Ah 0 10 Minutes Single Minutes
20 Hour
021Bh 0 12/24 10 Hour Single Hours
AM/PM Mission
R R
021Ch 0 0 10 Date Single Date Timestamp
10
021Dh CENT 0 0 Single Months
Months
021Eh 10 Years Single Years
021Fh (No Function; Reads 00h) — R R
0220h Low Byte Mission
0221h Center Byte Samples R R
0223h Low Byte Device

0224h Center Byte Samples R R
0226h Configuration Code Flavor R R

0227h EPW PW Control R/W R
0228h First Byte Read
… … Access W —
022Fh Eighth Byte Password
0230h First Byte Full

… … Access W —
0237h Eighth Byte Password
0238h
… (No Function; All These Bytes Read 00h) — R R
023Fh
*The left entry in the ACCESS column is valid between missions. The right entry shows the applicable access type while a
mission is in progress.
Figure 6. DS1922F Register Pages Map (continued)

Detailed Register Descriptions Sample Rate

Timekeeping and Calendar The content of the Sample Rate register (addresses
0206h, 0207h) specifies the time elapse (in seconds if
The RTC and calendar information is accessed by read- EHSS = 1, or minutes if EHSS = 0) between two temper-
ing/writing the appropriate bytes in the register page, ature-logging events. The sample rate can be any value
address 0200h to 0205h. For readings to be valid, all RTC from 1 to 16,383, coded as an unsigned 14-bit binary
registers must be read sequentially starting at address number. If EHSS = 1, the shortest time between logging
0200h. Some of the RTC bits are set to 0. These bits events is 1s and the longest (sample rate = 3FFFh) is
always read 0 regardless of how they are written. The 4.55hr. If EHSS = 0, the shortest is 1min and the longest
number representation of the RTC registers is binary- time is 273.05hr (sample rate = 3FFFh). The EHSS bit is
coded decimal (BCD) format. located in the RTC Control register at address 0212h. It
The DS1922F’s RTC can run in either 12hr or 24hr mode. is important that the user sets the EHSS bit accordingly
Bit 6 of the Hours register (address 0202h) is defined as while setting the Sample Rate register. Writing a sample
the 12hr or 24hr mode select bit. When high, the 12hr rate of 0000h results in a sample rate = 0001h, caus-
mode is selected. In the 12hr mode, bit 5 is the AM/PM ing the DS1922F to log the temperature either every
bit with logic 1 being PM. In the 24hr mode, bit 5 is the minute or every second depending upon the state of
20hr bit (20hr to 23hr). The CENT bit, bit 7 of the Months the EHSS bit.
register, can be written by the user. This bit changes its
state when the years counter transitions from 99 to 00.
The calendar logic is designed to automatically compen-
sate for leap years. For every year value that is either 00
or a multiple of 4, the device adds a 29th of February. This
works correctly up to (but not including) the year 2100.
RTC Registers
ADDRESS BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
0201h 0 10 Minutes Single Minutes
20 Hour
0202h 0 12/24 10 Hour Single Hours
AM/PM
0203h 0 0 10 Date Single Date
0204h CENT 0 0 10 Months Single Months
0205h 10 Years Single Years
Note: During a mission, there is only read access to these registers. Bit cells marked “0” always read 0 and cannot be written to 1.
Sample Rate Register

0206h Sample Rate Low
0207h 0 0 Sample Rate High
Note: During a mission, there is only read access to these registers. Bit cells marked 0 always read 0 and cannot be written to 1.

Temperature Conversion This equation is valid for converting temperature readings

The DS1922F’s temperature range begins at +15°C and stored in the data-log memory as well as for data read
ends at +140°C. Temperature values are represented as from the Latest Temperature Conversion Result register.
an 8- or 16-bit unsigned binary number with a resolution To specify the temperature alarm thresholds, the previous
of 0.5°C in 8-bit mode and 0.0625°C in 16-bit mode. equations are resolved to:
The higher temperature byte TRH is always valid. In TALM = 2 x ϑ(°C) - 28
16-bit mode, only the three highest bits of the lower byte Because the temperature alarm threshold is only one
TRL are valid. The five lower bits all read 0. TRL is unde- byte, the resolution or temperature increment is limited
fined if the device is in 8-bit temperature mode. An out-of- to 0.5°C. The TALM value must be converted into hexa-
range temperature reading is indicated as 00h or 0000h decimal format before it can be written to one of the
when too cold and FFh or FFE0h when too hot. Temperature Alarm old registers (Low Alarm address
With TRH and TRL representing the decimal equivalent 0208h; High Alarm address 0209h). Independent of the
of a temperature reading, the temperature value is cal- conversion mode (8- or 16-bit), only the most significant
culated as: byte of a temperature conversion is used to determine
ϑ(°C) = TRH/2 + 14 + TRL/512 (16-bit mode, whether an alarm is generated.
TLFS = 1, see address 0213h)
ϑ(°C) = TRH/2 + 14 (8-bit mode, TLFS = 0,
see address 0213h)
Latest Temperature Conversion Result Register

ADDRESS BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 BYTE
020Ch T2 T1 T0 0 0 0 0 0 TRL
020Dh T10 T9 T8 T7 T6 T5 T4 T3 TRH
Table 1. Temperature Conversion Examples

TRH TRL
MODE ϑ(°C)
HEX DECIMAL HEX DECIMAL
8-Bit ECh 236 — — 132.0
8-Bit F5h 245 — — 136.5
16-Bit ECh 236 00h 0 132.0000
16-Bit F5h 245 60h 96 136.6875
Table 2. Temperature Alarm Threshold Examples

TALM
ϑ(°C)
HEX DECIMAL
135.5 F3h 243
131.0 EAh 234

Temperature Sensor Control Register

0210h 0 0 0 0 0 0 ETHA ETLA
Note: During a mission, there is only read access to this register. Bits 2 to 7 have no function. They always read 0 and cannot be
written to 1.
RTC Control Register

0212h 0 0 0 0 0 0 EHSS EOSC
Note: During a mission, there is only read access to this register. Bits 2 to 7 have no function. They always read 0 and cannot be
written to 1.
Temperature Sensor Alarm RTC Control

The DS1922F has two Temperature Alarm Threshold reg- To minimize the power consumption of a DS1922F, the
isters (address 0208h, 0209h) to store values that deter- RTC oscillator should be turned off when the device is
mine whether a critical temperature has been reached. A not in use. The oscillator on/off bit is located in the RTC
temperature alarm is generated if the device measures an Control register. This register also includes the EHSS bit,
alarming temperature and the alarm signaling is enabled. which determines whether the sample rate is specified in
The bits ETLA and ETHA that enable the temperature seconds or minutes.
alarm are located in the Temperature Sensor Control reg- Bit 1: Enable High-Speed Sample (EHSS). This bit con-
ister. The temperature alarm flags TLF and THF are found trols the speed of the sample rate counter. When set to
in the Alarm Status register at address 0214h. logic 0, the sample rate is specified in minutes. When set
Bit 1: Enable Temperature High Alarm (ETHA). This bit to logic 1, the sample rate is specified in seconds.
controls whether, during a mission, the temperature high Bit 0: Enable Oscillator (EOSC). This bit controls the
alarm flag (THF) may be set, if a temperature conversion crystal oscillator of the RTC. When set to logic 1, the
results in a value equal to or higher than the value in the oscillator starts. When written to logic 0, the oscillator
Temperature High Alarm Threshold register. If ETHA is 1, stops and the device is in a low-power data-retention
temperature high alarms are enabled. If ETHA is 0, tem- mode. This bit must be 1 for normal operation. A Forced
perature high alarms are not generated. Conversion or Start Mission command automatically
Bit 0: Enable Temperature Low Alarm (ETLA). This bit starts the RTC by changing the EOSC bit to logic 1.
controls whether, during a mission, the temperature low
alarm flag (TLF) may be set, if a temperature conversion
results in a value equal to or lower than the value in the
Temperature Low Alarm Threshold register. If ETLA is 1,
temperature low alarms are enabled. If ETLA is 0, tem-
perature low alarms are not generated.

Mission Control Register

0213h 1 1 SUTA RO (X) TLFS 0 ETL
Note: During a mission, there is only read access to this register. Bits 6 and 7 have no function. They always read 1 and cannot be
written to 0. Bits 1 and 3 control functions that are not available with the DS1922F. Bit 1 must be set to 0. Under this condition the
setting of bit 3 becomes a “don’t care.”
Mission Control Bit 4: Rollover Control (RO). This bit controls whether,
The DS1922F is set up for its operation by writing appro- during a mission, the data-log memory is overwritten
priate data to its special function registers, which are with new data or whether data logging is stopped once
located in the two register pages. The settings in the the data-log memory is full. Setting this bit to 1 enables
Mission Control register determine which format (8 or 16 the rollover and data logging continues at the beginning,
bits) applies and whether old data can be overwritten by overwriting previously collected data. If this bit is 0, the
new data once the data-log memory is full. An additional logging and conversions stop once the data-log memory
control bit can be set to tell the DS1922F to wait with log- is full. However, the RTC continues to run and the MIP bit
ging data until a temperature alarm is encountered. remains set until the Stop Mission command is performed.
Bit 5: Start Mission Upon Temperature Alarm (SUTA). Bit 2: Temperature Logging Format Selection (TLFS).
This bit specifies whether a mission begins immedi- This bit specifies the format used to store temperature
ately (includes delayed start) or if a temperature alarm readings in the data-log memory. If this bit is 0, the data
is required to start the mission. If this bit is 1, the device is stored in 8-bit format. If this bit is 1, the 16-bit format
performs an 8-bit temperature conversion at the selected is used (higher resolution). With 16-bit format, the most
sample rate and begins with data logging only if an alarm- significant byte is stored at the lower address.
ing temperature (high alarm or low alarm) was found. Bit 0: Enable Temperature Logging (ETL). To set up the
The first logged temperature is when the alarm occurred. device for a temperature-logging mission, this bit must be
However, the mission sample counter does not increment. set to logic 1. The recorded temperature values start at
This functionality is guaranteed by design and not produc- address 1000h.
tion tested.

Alarm Status Register

0214h BOR 1 1 1 0 0 THF TLF
Note: There is only read access to this register. Bits 4 to 6 have no function. They always read 1. Bits 2 and 3 have no function with
the DS1922F. They always read 0. The alarm status bits are cleared simultaneously when the Clear Memory Function is invoked.
See memory and control functions for details.
General Status Register

0215h 1 1 0 WFTA MEMCLR 0 MIP 0
Note: There is only read access to this register. Bits 0, 2, 5, 6, and 7 have no function.
Alarm Status General Status

The fastest way to determine whether a programmed The information in the General Status register tells
temperature threshold was exceeded during a mission the host computer whether a mission-related command
is through reading the Alarm Status register. In a net- was executed successfully. Individual status bits indicate
worked environment that contains multiple DS1922F ICs, whether the DS1922F is performing a mission, waiting
the devices that encountered an alarm can quickly be for a temperature alarm to trigger the logging of data or
identified by means of the Conditional Search command whether the data from the latest mission has been cleared.
(see the 1-Wire ROM Function Commands section). Bit 4: Waiting for Temperature Alarm (WFTA). If this bit
The temperature alarm only occurs if enabled (see the reads 1, the Mission Start Upon Temperature Alarm was
Temperature Sensor Alarm section). The BOR alarm is selected and the Start Mission command was success-
always enabled. fully executed, but the device has not yet experienced the
Bit 7: Battery-On Reset Alarm (BOR). If this bit reads 1, temperature alarm. This bit is cleared after a temperature
the device has performed a power-on reset. This indicates alarm event, but is not affected by the Clear Memory
that the device has experienced a shock big enough to command. Once set, WFTA remains set if a mission is
interrupt the internal battery power supply. The device stopped before a temperature alarm occurs. To clear
may still appear functional, but it has lost its factory cali- WFTA manually before starting a new mission, set the
bration. Any data found in the data-log memory should be high temperature alarm (address 0209h) to +15°C and
disregarded. perform a forced conversion.
Bit 1: Temperature High Alarm Flag (THF). If this bit Bit 3: Memory Cleared (MEMCLR). If this bit reads 1,
reads 1, there was at least one temperature conversion the Mission Timestamp, mission samples counter, and
during a mission revealing a temperature equal to or high- all the alarm flags of the Alarm Status register have been
er than the value in the Temperature High Alarm register. cleared in preparation of a new mission. Executing the
A forced conversion can affect the THF bit. This bit can Clear Memory command clears these memory sections.
also be set with the initial alarm in the SUTA = 1 mode. The MEMCLR bit returns to 0 as soon as a new mission is
Bit 0: Temperature Low Alarm Flag (TLF). If this bit started by using the Start Mission command. The memory
reads 1, there was at least one temperature conversion must be cleared for a mission to start.
during a mission revealing a temperature equal to or Bit 1: Mission in Progress (MIP). If this bit reads 1, the
lower than the value in the Temperature Low Alarm regis- device has been set up for a mission and this mission is
ter. A forced conversion can affect the TLF bit. This bit can still in progress. The MIP bit returns from logic 1 to logic 0
also be set with the initial alarm in the SUTA = 1 mode. when a mission is ended. See the Start Mission and Stop
Mission function commands.

Mission Start Delay Counter Register

0216h Delay Low Byte
0217h Delay Center Byte
0218h Delay High Byte
Note: During a mission, there is only read access to this register.
Mission Timestamp Register
021Ah 0 10 Minutes Single Minutes
20 Hours
021Bh 0 12/24 10 Hours Single Hours
AM/PM
021Ch 0 0 10 Date Single Date
021Dh CENT 0 0 10 Months Single Months
021Eh 10 Years Single Years
Note: There is only read access to this register.
Mission Samples Counter Register

0220h Low Byte
0221h Center Byte
0222h High Byte
Mission Start Delay Mission Timestamp

The content of the Mission Start Delay Counter register The Mission Timestamp register indicates the date and
tells how many minutes must expire from the time a mis- time of the first temperature sample of the mission. There
sion was started until the first measurement of the mission is only read access to the Mission Timestamp register.
takes place (SUTA = 0) or until the device starts testing
the temperature for a temperature alarm (SUTA = 1). Mission Progress Indicator
The Mission Start Delay is stored as an unsigned 24-bit Depending on settings in the Mission Control register
integer number. The maximum delay is 16,777,215min, (address 0213h), the DS1922F logs temperature in 8-bit
equivalent to 11,650 days or roughly 31yr. If the start or 16-bit format. The Mission Samples Counter together
delay is nonzero and the SUTA bit is set to 1, first the with the starting address and the logging format (8 or 16
delay must expire before the device starts testing for tem- bits) provide the information to identify valid blocks of
perature alarms to begin logging data. data that have been gathered during the current (MIP =
1) or latest mission (MIP = 0). See the Data-Log Memory
For a typical mission, the Mission Start Delay is 0. If a
Usage section for an illustration.
mission is too long for a single DS1922F to store all read-
ings at the selected sample rate, one can use several The number read from the mission samples counter indi-
devices and set the Mission Start Delay for the second cates how often the DS1922F woke up during a mission
device to start recording as soon as the memory of the to measure temperature. The number format is 24-bit
first device is full, and so on. The RO bit in the Mission unsigned integer. The mission samples counter is reset
Control register (address 0213h) must be set to 0 to through the Clear Memory command.
prevent overwriting of collected data once the data-log
memory is full.

Device Samples Counter Register

0223h Low Byte
0224h Center Byte
0225h High Byte
Device Configuration Register
ADDRESS BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 PART
0 0 0 0 0 0 0 0 DS2422
0 0 1 0 0 0 0 0 DS1923
0 1 0 0 0 0 0 0 DS1922L
0226h
0 1 1 0 0 0 0 0 DS1922T
1 0 0 0 0 0 0 0 DS1922E
1 1 0 0 0 0 0 0 DS1922F
Password Control Register

0227h EPW
Note: During a mission, there is only read access to this register.
Other Indicators Security by Password

The Device Samples Counter register is similar to the The DS1922F is preprogrammed with two set passwords
Mission Samples Counter register. During a mission this that control read access and full access. Reading from or
counter increments whenever the DS1922F wakes up to writing to the scratchpad as well as the forced conversion
measure and log data and when the device is testing for command does not require a password. The password
a temperature alarm in SUTA mode. Between missions must be transmitted immediately after the command code
the counter increments whenever the Forced Conversion of the memory or control function.
command is executed. This way the Device Samples By default, the DS1922F has password checking enabled.
Counter register functions like a gas gauge for the battery Consequently, the password transmitted is compared to
that powers the iButton device. the passwords stored in the device and the EPW bits
The Device Samples Counter register is reset to zero read AAh. If the current full-access password is known,
when the iButton device is assembled. The number for- then changing the passwords or disabling password
mat is 24-bit unsigned integer. The maximum number that checking is feasible. If the password is disabled, then the
can be represented in this format is 16,777,215. Due to EPW byte is different than AAh and any pattern is accept-
the calibration and tests at the factory, new devices can able as long as it has a length of exactly 64 bits. Contact
have a count value of up to 35,000. The typical value is the factory for additional details.
well below 10,000.
The code in the Device Configuration register allows the
master to distinguish between the DS2422 chip and differ-
ent versions of the DS1922 ICs. The Device Configuration
Register table shows the codes assigned to the various
devices.

Read Access Password Register

0228h RP7 RP6 RP5 RP4 RP3 RP2 RP1 RP0
0229h RP15 RP14 RP13 RP12 RP11 RP10 RP9 RP8
… …
022Eh RP55 RP54 RP53 RP52 RP51 RP50 RP49 RP48
022Fh RP63 RP62 RP61 RP60 RP59 RP58 RP57 RP56
Note: There is only write access to this register. Attempting to read the password reports all zeros. The password cannot be
changed while a mission is in progress.
Full Access Password Register

0230h FP7 FP6 FP5 FP4 FP3 FP2 FP1 FP0
… …
Note: There is only write access to this register. Attempting to read the password reports all zeros. The password cannot be
changed while a mission is in progress
Before reenabling password checking, passwords for The Full Access Password must be transmitted exactly in
read-only access as well as for full access (read/write/ the sequence FP0, FP1…FP62, FP63. It affects the func-
control) must be written to the password registers. Setting tions Read Memory with CRC, Copy Scratchpad, Clear
up a password or enabling/disabling the password check- Memory, Start Mission, and Stop Mission. The DS1922F
ing is done in the same way as writing data to a memory executes the command only if the password transmitted
location; only the address is different. Since they are by the master was correct or if password checking is not
located in the same memory page, both passwords can enabled.
be redefined at the same time. Due to the special behavior of the write-access logic,
The Read Access Password must be transmitted exactly the Password Control register and both passwords must
in the sequence RP0, RP1…RP62, RP63. This password be written at the same time. When setting up new pass-
only applies to the Read Memory with CRC function. The words, always verify (read back) the scratchpad before
DS1922F delivers the requested data only if the password sending the Copy Scratchpad command. After a new
transmitted by the master was correct or if password password is successfully copied from the scratchpad
checking is not enabled. to its memory location, erase the scratchpad by filling it
with new data (Write Scratchpad command). Otherwise,
a copy of the passwords remains in the scratchpad for
public read access.

enable the device for a mission, the ETL bit must be set
ETL = 1 ETL = 1
to 1. These are general settings that must be made in any
TLFS = 0 TLFS = 1 case, regardless of the type of object to be monitored and
1000h 1000h the duration of the mission.
WITH 16-BIT FORMAT, If alarm signaling is desired, the temperature alarm low
8192 4096
THE MOST SIGNIFICANT and high thresholds must be defined. See the Temperature
BYTE IS STORED AT THE Conversion section for how to convert a temperature value
8-BIT ENTRIES 16-BIT ENTRIES
LOWER ADDRESS.
into the binary code to be written to the threshold registers.
In addition, the temperature alarm must be enabled for the
2FFFh 2FFFh
low and/or high threshold. This makes the device respond
to a Conditional Search command (see the 1-Wire ROM
Figure 7. Temperature Logging Function Commands section), provided that an alarming
condition has been encountered.
Data-Log Memory Usage The setting of the RO bit (rollover enable) and sample
Once set up for a mission, the DS1922F logs the tem- rate depends on the duration of the mission and the
perature measurements at equidistant time points entry monitoring requirements. If the most recently logged data
after entry in its data-log memory. The data-log memory is important, the rollover should be enabled (RO = 1).
can store 8192 entries in 8-bit format or 4096 entries in Otherwise, one should estimate the duration of the mis-
16-bit format (Figure 7). In 16-bit format, the higher 8 bits sion in minutes and divide the number by 8192 (8-bit for-
of an entry are stored at the lower address. Knowing the mat) or 4096 (16-bit format) to calculate the value of the
starting time point (Mission Timestamp) and the interval sample rate (number of minutes between conversions).
between temperature measurements, one can recon- For example, if the estimated duration of a mission is 10
struct the time and date of each measurement. days (= 14400min), the 8192-byte capacity of the data-
There are two alternatives to the way the DS1922F log memory would be sufficient to store a new 8-bit value
behaves after the data-log memory is filled with data. The every 1.8min (110s). If the DS1922F’s data-log memory
user can program the device to either stop any further is not large enough to store all readings, one can use
recording (disable rollover) or overwrite the previously several devices and set the mission start delay to values
recorded data (enable rollover), one entry at a time, start- that make the second device start logging as soon as the
ing again at the beginning of the respective memory sec- memory of the first device is full, and so on. The RO bit
tion. The contents of the Mission Samples Counter in con- must be set to 0 to disable rollover that would otherwise
junction with the sample rate and the Mission Timestamp overwrite the logged data.
allow reconstructing the time points of all values stored After the RO bit and the mission start delay are set, the
in the data-log memory. This gives the exact history over sample rate must be written to the Sample Rate register.
time for the most recent measurements taken. Earlier The sample rate can be any value from 1 to 16,383, coded
measurements cannot be reconstructed. as an unsigned 14-bit binary number. The fastest sample
rate is one sample per second (EHSS = 1, sample rate
Missioning = 0001h) and the slowest is one sample every 273.05hr
The DS1922F’s typical task is recording temperature. (EHSS = 0, sample rate = 3FFFh). To get one sample
Before the device can perform this function, it needs to every 6min, for example, the sample rate value must be
be set up properly. This procedure is called missioning. set to 6 (EHSS = 0) or 360 decimal (equivalent to 0168h
First, the DS1922F must have its RTC set to a valid time at EHSS = 1).
and date. This reference time can be the local time, or, If there is a risk of unauthorized access to the DS1922F
when used inside of a mobile unit, UTC (also called GMT, or manipulation of data, one should define passwords
Greenwich Mean Time), or any other time standard that for read access and full access. Before the passwords
was agreed upon. The RTC oscillator must be running become effective, their use must be enabled. See the
(EOSC = 1). The memory assigned to store the mission Security by Password section for more details.
timestamp, mission samples counter, and alarm flags
must be cleared using the Memory Clear command. To

The last step to begin a mission is to issue the Start Memory Access
Mission command. As soon as it has received this com-
mand, the DS1922F sets the MIP flag and clears the Address Registers and Transfer Status
MEMCLR flag. With the Immediate/Delayed Start Mode Because of the serial data transfer, the DS1922F employs
(SUTA = 0), after as many minutes as specified by the three address registers called TA1, TA2, and E/S (Figure
mission start delay are over, the device wakes up, cop- 8). Registers TA1 and TA2 must be loaded with the target
ies the current date and time to the Mission Timestamp address to which the data is written or from which data
register, and logs the first entry of the mission. This is sent to the master upon a Read command. Register
increments both the mission samples counter and device E/S acts like a byte counter and transfer status register.
samples counter. All subsequent log entries are made as It is used to verify data integrity with Write commands.
specified by the value in the Sample Rate register and Therefore, the master only has read access to this reg-
the EHSS bit. ister. The lower 5 bits of the E/S register indicate the
address of the last byte that has been written to the
If the Start Upon Temperature Alarm mode is chosen
scratchpad. This address is called ending offset. The
(SUTA = 1) and temperature logging is enabled (ETL =
DS1922F requires that the ending offset is always
1), the DS1922F first waits until the start delay is over.
1Fh for a Copy Scratchpad to function. Bit 5 of the E/S
Then the device wakes up in intervals as specified by the
register, called PF or partial byte flag, is set if the number
sample rate and EHSS bit and measures the tempera-
of data bits sent by the master is not an integer multiple
ture. This increments the Device Samples Counter reg-
of 8. Bit 6 is always a 0. Note that the lowest 5 bits of
ister only. The first sample of the mission is logged when
the target address also determine the address within the
the temperature alarm occurred. However, the Mission
scratchpad, where intermediate storage of data begins.
Sample Counter does not increment. One sample period
This address is called byte offset. If the target address for
later the Mission Timestamp register is set. From then on,
a Write command is 13Ch, for example, the scratchpad
both the Mission Samples Counter and Device Samples
stores incoming data beginning at the byte offset 1Ch and
Counter registers increment at the same time. All subse-
is full after only 4 bytes. The corresponding ending offset
quent log entries are made as specified by the value in
in this example is 1Fh. For best economy of speed and
the Sample Rate register and the EHSS bit.
efficiency, the target address for writing should point to the
The general-purpose memory operates independently beginning of a page, i.e., the byte offset is 0. Thus, the full
of the other memory sections and is not write protected 32-byte capacity of the scratchpad is available, resulting
during a mission. All the DS1922F’s memory can be read also in the ending offset of 1Fh. The ending offset togeth-
at any time, e.g., to watch the progress of a mission. er with the PF flag are a means to support the master
Attempts to read the passwords read 00h bytes instead of checking the data integrity after a Write command. The
the data that is stored in the password registers. highest valued bit of the E/S register, called authorization
accepted (AA), indicates that a valid Copy command for
the scratchpad has been received and executed. Writing
data to the scratchpad clears this flag.
BIT NUMBER 7 6 5 4 3 2 1 0
TARGET ADDRESS (TA1) T7 T6 T5 T4 T3 T2 T1 T0
TARGET ADDRESS (TA2) T15 T14 T13 T12 T11 T10 T9 T8
ENDING ADDRESS WITH

DATA STATUS (E/S) AA 0 PF E4 E3 E2 E1 E0
(READ ONLY)
Figure 8. Address Registers

Writing with Verification section. The communication between the master and the
To write data to the DS1922F, the scratchpad must be DS1922F takes place either at standard speed (default,
used as intermediate storage. First, the master issues OD = 0) or at overdrive speed (OD = 1). If not explicitly
the Write Scratchpad command to specify the desired set into the overdrive mode the DS1922F assumes stan-
target address, followed by the data to be written to the dard speed. Internal memory access during a mission has
scratchpad. In the next step, the master sends the Read priority over external access through the 1-Wire interface.
Scratchpad command to read the scratchpad and to This affects several commands in this section. See the
verify data integrity. As preamble to the scratchpad data, Memory Access Conflicts section for details and solutions.
the DS1922F sends the requested target address TA1 Write Scratchpad Command [0Fh]
and TA2 and the contents of the E/S Register. If the PF
After issuing the Write Scratchpad command, the master
flag is set, data did not arrive correctly in the scratchpad.
must first provide the 2-byte target address, followed by
The master does not need to continue reading; it can
the data to be written to the scratchpad. The data is writ-
start a new trial to write data to the scratchpad. Similarly,
ten to the scratchpad starting at the byte offset T[4:0]. The
a set AA flag indicates that the Write command was not
master must send as many bytes as are needed to reach
recognized by the device. If everything went correctly,
the ending offset of 1Fh. If a data byte is incomplete, its
both flags are cleared and the ending offset indicates the
content is ignored and the partial byte flag PF is set.
address of the last byte written to the scratchpad. Now
the master can continue verifying every data bit. After When executing the Write Scratchpad command, the
the master has verified the data, it must send the Copy CRC generator inside the DS1922F calculates a CRC of
Scratchpad command. This command must be followed the entire data stream, starting at the command code and
exactly by the data of the three address registers TA1, ending at the last data byte sent by the master (Figure
TA2, and E/S, as the master has read them verifying the 15). This CRC is generated using the CRC-16 polynomial
scratchpad. As soon as the DS1922F has received these by first clearing the CRC generator and then shifting in
bytes, it copies the data to the requested location begin- the command code (0Fh) of the Write Scratchpad com-
ning at the target address. mand, the target addresses TA1 and TA2 as supplied
by the master, and all the data bytes. If the ending offset
Memory and Control is 11111b, the master can send 16 read time slots and
Function Commands receive the inverted CRC-16 generated by the DS1922F.
Figure 9 shows the protocols necessary for accessing Note that both register pages are write protected during a
the memory and the special function registers of the mission. Although the Write Scratchpad command works
DS1922F. An example on how to use these and other normally at any time, the subsequent copy scratchpad to
functions to set up the DS1922F for a mission is included a register page fails during a mission.
in the Mission Example: Prepare and Start a New Mission

Read Scratchpad Command [AAh] the register pages are not successful. The AA bit remain-
This command is used to verify scratchpad data and ing at 0 indicates this.
target address. After issuing the Read Scratchpad com- Read Memory with Password and CRC [69h]
mand, the master begins reading. The first 2 bytes are
The Read Memory with CRC command is the general
the target address. The next byte is the ending offset/
function to read from the device. This command gener-
data status byte (E/S) followed by the scratchpad data
ates and transmits a 16-bit CRC following the last data
beginning at the byte offset T[4:0], as shown in Figure 8.
byte of a memory page.
The master can continue reading data until the end of the
scratchpad after which it receives an inverted CRC-16 of After having sent the command code of the Read Memory
the command code, target addresses TA1 and TA2, the with CRC command, the bus master sends a 2-byte
E/S byte, and the scratchpad data starting at the target address that indicates a starting byte location. Next, the
address. After the CRC is read, the bus master reads master must transmit one of the 64-bit passwords. If pass-
logic 1s from the DS1922F until a reset pulse is issued. words are enabled and the transmitted password does
not match one of the stored passwords, the Read Memory
Copy Scratchpad with Password [99h] with Password and CRC command fails. The device stops
This command is used to copy data from the scratchpad communicating and waits for a reset pulse. If the pass-
to the writable memory sections. After issuing the Copy word was correct or if passwords were not enabled, the
Scratchpad command, the master must provide a 3-byte master reads data from the DS1922F beginning from the
authorization pattern, which can be obtained by reading starting address and continuing until the end of a 32-byte
the scratchpad for verification. This pattern must exactly page is reached. At that point the bus master sends 16
match the data contained in the three address registers additional read data time slots and receives the inverted
(TA1, TA2, E/S, in that order). Next, the master must 16-bit CRC. With subsequent read data time slots the
transmit the 64-bit full-access password. If passwords are master receives data starting at the beginning of the next
enabled and the transmitted password is different from memory page followed again by the CRC for that page.
the stored full-access password, the Copy Scratchpad This sequence continues until the bus master resets the
with Password command fails. The device stops commu- device. When trying to read the passwords or memory
nicating and waits for a reset pulse. If the password was areas that are marked as “reserved,” the DS1922F trans-
correct or if passwords were not enabled, the device tests mits 00h or FFh bytes, respectively. The CRC at the end
the 3-byte authorization code. If the authorization code of a 32-byte memory page is based on the data as it was
pattern matches, the AA flag is set and the copy begins. transmitted.
A pattern of alternating 1s and 0s is transmitted after the With the initial pass through the Read Memory with CRC
data has been copied until the master issues a reset flow, the 16-bit CRC value is the result of shifting the com-
pulse. While the copy is in progress, any attempt to reset mand byte into the cleared CRC generator followed by the
the part is ignored. Copy typically takes 2μs per byte. two address bytes and the contents of the data memory.
The data to be copied is determined by the three address Subsequent passes through the Read Memory with CRC
registers. The scratchpad data from the beginning offset flow generate a 16-bit CRC that is the result of clearing
through the ending offset are copied, starting at the target the CRC generator and then shifting in the contents of
address. The AA flag remains at logic 1 until it is cleared the data memory page. After the 16-bit CRC of the last
by the next Write Scratchpad command. With suitable page is read, the bus master receives logic 1s from the
password, the copy scratchpad always functions for the DS1922F until a reset pulse is issued. The Read Memory
16 pages of data memory and the 2 pages of calibration with CRC command sequence can be ended at any point
memory. While a mission is in progress, write attempts to by issuing a reset pulse.

MASTER Tx MEMORY OR FROM ROM FUNCTIONS

CONTROL FUNCTION COMMAND FLOWCHART (FIGURE 11)
0Fh AAh 99h TO FIGURE 9b

N N COPY SCRATCHPAD N
WRITE SCRATCHPAD? READ SCRATCHPAD?
[WITH PW]
Y Y Y
MASTER Tx MASTER Rx MASTER Tx

TA1 [T7:T0] TA1 [T7:T0] TA1 [T7:T0], TA2 [T15:T8]
AUTHORIZATION
CODE
MASTER Tx MASTER Rx MASTER Tx
TA2 [T15:T8] TA2 [T15:T8] E/S BYTE
DS1922F SETS MASTER Rx ENDING OFFSET MASTER Tx

SCRATCHPAD OFFSET = [T4:T0] WITH DATA STATUS 64 BITS [PASSWORD]
AND CLEARS (PF, AA) (E/S)
MASTER Tx DATA BYTE DS1922F SETS PASSWORD N

TO SCRATCHPAD OFFSET SCRATCHPAD OFFSET = [T4:T0] ACCEPTED?
Y
DS1922F DS1922F SETS [E4:E0] = DS1922F MASTER Rx DATA BYTE FROM
INCREMENTS SCRATCHPAD OFFSET INCREMENTS SCRATCHPAD OFFSET
SCRATCHPAD SCRATCHPAD AUTHORIZATION N
OFFSET OFFSET CODE MATCH?
Y
Y Y
MASTER Tx RESET? MASTER Tx RESET?
AA = 1
N N
DS1922F COPIES SCRATCHPAD

N SCRATCHPAD N SCRATCHPAD DATA TO MEMORY
OFFSET = 11111b? OFFSET = 11111b?
Y PARTIAL Y Y MASTER Rx "1"s MASTER Rx "1"s

BYTE WRITTEN?
N COPYING
MASTER Rx CRC-16 OF FINISHED
Y N COMMAND, ADDRESS DATA,
MASTER Tx RESET?
E/S BYTE, AND DATA STARTING N
AT THE TARGET ADDRESS Y MASTER Tx RESET?
N
PF = 1 DS1922F Tx "0"
Y
MASTER Rx CRC-16 OF
COMMAND, ADDRESS DATA Y
MASTER Tx RESET?
Y
MASTER Tx RESET?
N
Y
MASTER Tx RESET?
N
MASTER Rx "1"s
N DS1922F Tx "1"
MASTER Rx "1"s
N
MASTER Tx RESET?
FROM FIGURE 9b
TO ROM FUNCTIONS
FLOWCHART (FIGURE 11)
Figure 9a. Memory/Control Function Flowchart

FROM FIGURE 9a 69h 96h 55h TO FIGURE 9c

READ MEMORY [WITH N CLEAR MEMORY N N
FORCED CONVERSION?
PW] AND CRC [WITH PW]
Y Y Y
MASTER Tx MASTER Tx MASTER Tx

TA1 [T7:T0], TA2 [T15:T8] 64 BITS [PASSWORD] FFh DUMMY BYTE
MASTER Tx MASTER Tx
DECISION MADE 64 BITS [PASSWORD] FFh DUMMY BYTE MISSION IN Y
BY DS1922F PROGRESS?
N
PASSWORD N PASSWORD N
ACCEPTED? ACCEPTED? DS1922F PERFORMS A
TEMPERATURE CONVERSION
DECISION MADE Y Y
BY MASTER
DS1922F SETS DS1922F COPIES RESULT TO
MEMORY ADDRESS = [T15:T0] MISSION IN Y ADDRESS 020C/Dh
PROGRESS?
N
MASTER Rx DATA BYTE FROM
MEMORY ADDRESS N
MASTER Tx RESET?
DS1922F CLEARS
MISSION TIMESTAMP,
MISSION SAMPLES COUNTER, Y
DS1922F ALARM FLAGS
Y INCREMENTS
MASTER Tx RESET?
ADDRESS
COUNTER
DS1922F SETS
N
MEMCLR = 1
N
END OF PAGE?
N
MASTER Tx RESET?
Y
Y
MASTER Rx CRC-16 OF
COMMAND, ADDRESS, DATA
(1ST PASS); CRC-16 OF DATA
(SUBSEQUENT PASSES)
N
MASTER Tx RESET CRC OK?
N
END OF MEMORY?
Y
MASTER Rx "1"s
N
MASTER Tx RESET?
TO FIGURE 9a FROM FIGURE 9c
Figure 9b. Memory/Control Function Flowchart (continued)

FROM FIGURE 9b CCh 33h

START MISSION N STOP MISSION N
[WITH PW] [WITH PW]
MISSION START
Y DELAY PROCESS Y
MASTER Tx MASTER Tx
64 BITS [PASSWORD] 64 BITS [PASSWORD]
START DELAY Y
COUNTER = 0?
MASTER Tx MASTER Tx
FFh DUMMY BYTE N FFh DUMMY BYTE
DS1922F WAITS FOR 1 MINUTE
N PASSWORD PASSWORD N
DS1922F DECREMENTS
ACCEPTED? START DELAY COUNTER ACCEPTED?
Y Y
Y MISSION IN MISSION IN N
N
PROGRESS? SUTA = 1? PROGRESS?
N Y Y
DS1922F SETS WFTA = 1 DS1922F SETS

N MIP = 0,
MEMCLR = 1?
WFTA = 0
DS1922F WAITS ONE
Y SAMPLE PERIOD
DS1922F SETS
MIP = 1, N
MEMCLR = 0 Y MASTER Tx RESET?
MIP = 0?
N Y
DS1922F INITIATES MISSION
START DELAY PROCESS DS1922F PERFORMS 8-BIT
TEMPERATURE CONVERSION
N
MASTER Tx RESET? TEMPERATURE N
ALARM?
Y Y
DS1922F SETS WFTA = 0
DS1922F WAITS ONE

SAMPLE PERIOD
DS1922F COPIES RTC DATA TO

MISSION TIMESTAMP REGISTER
DS1922F STARTS LOGGING

TAKING FIRST SAMPLE
END OF PROCESS
TO FIGURE 9b
Figure 9c. Memory/Control Function Flowchart (continued)

Clear Memory with Password [96h] Start Mission with Password [CCh]
The Clear Memory with Password command is used to The DS1922F uses a control function command to start
prepare the device for another mission. This command is a mission. A new mission can only be started if the previ-
only executed if no mission is in progress. After the com- ous mission has been ended and the memory has been
mand code the master must transmit the 64-bit full-access cleared. After the command code, the master must trans-
password followed by an FFh dummy byte. If passwords mit the 64-bit full-access password followed by an FFh
are enabled and the transmitted password is different dummy byte. If passwords are enabled and the trans-
from the stored full-access password or a mission is in mitted password is different from the stored full-access
progress, the Clear Memory with Password command password or a mission is in progress, the Start Mission
fails. The device stops communicating and waits for with Password command fails. The device stops com-
a reset pulse. If the password was correct or if pass- municating and waits for a reset pulse. If the password
words were not enabled, the device clears the Mission was correct or if passwords were not enabled, the device
Timestamp register, Mission Samples Counter register, starts a mission. If SUTA = 0, the sampling begins as
and all alarm flags of the Alarm Status register. After these soon as the mission start delay is over. If SUTA = 1, the
cells are cleared, the MEMCLR bit of the General Status first sample is written to the datalog memory at the time
register reads 1 to indicate the successful execution of the the temperature alarm occurred. However, the mission
Clear Memory with Password command. Clearing of the sample counter does not increment. One sample period
data-log memory is not necessary because the mission later, the Mission Timestamp register is set and the regu-
samples counter indicates how many entries in the data- lar sampling and logging begins. While the device is wait-
log memory are valid. ing for a temperature alarm to occur, the WFTA flag in the
General Status register reads 1. During a mission there is
Forced Conversion [55h] only read access to the register pages.
The Forced Conversion command can be used to mea-
sure the temperature without starting a mission. After the Stop Mission with Password [33h]
command code, the master must send one FFh byte to The DS1922F uses a control function command to
get the conversion started. The conversion result is found stop a mission. Only a mission that is in progress can
as a 16-bit value in the Latest Temperature Conversion be stopped. After the command code, the master must
Result register. This command is only executed if no transmit the 64-bit full-access password followed by a
mission is in progress (MIP = 0). It cannot be interrupted FFh dummy byte. If passwords are enabled and the trans-
and takes maximum 600ms to complete. During this time mitted password is different from the stored full-access
memory access through the 1-Wire interface is blocked. password or a mission is not in progress, the Stop Mission
The device behaves the same way as during a mission with Password command fails. The device stops com-
when the sampling interferes with a memory/control func- municating and waits for a reset pulse. If the password
tion command. See the Memory Access Conflicts section was correct or if passwords were not enabled, the device
for details. clears the MIP bit in the General Status register and
restores write access to the register pages. The WFTA bit
is not cleared. See the description of the General Status
register for a method to clear the WFTA bit.

Memory Access Conflicts while the device is waiting for a temperature alarm. Table
While a mission is in progress or while the device is 3 explains how the remaining five commands are affected
waiting for a temperature alarm to start a mission, peri- by internal activity, how to detect this interference, and
odically a temperature sample is taken and logged. This how to work around it.
“internal activity” has priority over 1-Wire communication. The interference is more likely to be seen with a high
As a consequence, device-specific commands (excluding sample rate (one sample every second) and with high
ROM function commands and 1-Wire reset) do not per- resolution logging, which can last up to 600ms. With lower
form properly when internal and “external” activities inter- sample rates, interference may hardly be visible at all.
fere with each other. Not affected are the commands Start In any case, when writing driver software it is important
Mission, Forced Conversion, and Clear Memory, because to know about the possibility of interference and to take
they are not applicable while a mission is in progress or measures to work around it.
Table 3. Memory Access Conflicts and Solutions

COMMAND INDICATION OF INTERFERENCE SOLUTION
Wait 0.5s, 1-Wire reset, address the device, repeat

Write Scratchpad with the same data, and check the
The CRC-16 at the end of the command flow reads
Write Scratchpad validity of the CRC-16 at the end of the command
FFFFh.
flow. Alternatively, use Read Scratchpad to verify data
integrity.
The data read changes to FFh bytes or all bytes Wait 0.5s, 1-Wire reset, address the device, repeat
Read Scratchpad received are FFh, including the CRC at the end of the Read Scratchpad, and check the validity of the
command flow. CRC-16 at the end of the command flow.
The device behaves as if the authorization code or Wait 0.5s, 1-Wire reset, address the device, issue
Copy Scratchpad password was not valid, or as if the copy function Read Scratchpad, and check the AA bit of the E/S byte.
would not end. If the AA bit is set, Copy Scratchpad was successful.
The data read changes to all FFh bytes or all bytes Wait 0.5s, 1-Wire reset, address the device, repeat
Read Memory with
received are FFh, including the CRC at the end of the Read Memory with CRC, and check the validity of the
CRC
command flow, despite a valid password. CRC-16 at the end of the memory page.
Wait 0.5s, 1-Wire reset, address the device, and repeat

Stop Mission. Perform a 1-Wire reset, address the
The General Status register at address 0215h reads
Stop Mission device, read the General Status register at address
FFh or the MIP bit is 1 while bits 0, 2, and 5 are 0.
0215h, and check the MIP bit. If the MIP bit is 0, Stop
Mission was successful.

1-Wire Bus System The value of the pullup resistor primarily depends on the
The 1-Wire bus is a system that has a single bus master network size and load conditions. The DS1922F requires a
and one or more slaves. In all instances the DS1922F is pullup resistor of maximum 2.2kΩ at any speed.
a slave device. The bus master is typically a microcon- The idle state for the 1-Wire bus is high. If for any reason
troller. The discussion of this bus system is broken down a transaction needs to be suspended, the bus must be
into three topics: hardware configuration, transaction left in the idle state if the transaction is to resume. If this
sequence, and 1-Wire signaling (signal types and timing). does not occur and the bus is left low for more than 16μs
The 1-Wire protocol defines bus transactions in terms of (overdrive speed) or more than 120μs (standard speed),
the bus state during specific time slots that are initiated one or more devices on the bus may be reset. Note that
on the falling edge of sync pulses from the bus master. the DS1922F does not quite meet the full 16μs maximum
low time of the normal 1-Wire bus overdrive timing. With
Hardware Configuration the DS1922F the bus must be left low for no longer than
The 1-Wire bus has only a single line by definition; it is 12μs at overdrive to ensure that no DS1922F on the
important that each device on the bus be able to drive 1-Wire bus performs a reset. The DS1922F communi-
it at the appropriate time. To facilitate this, each device cates properly when used in conjunction with a DS2480B
attached to the 1-Wire bus must have open-drain or three- or DS2490 1-Wire driver and adapters that are based on
state outputs. The 1-Wire port of the DS1922F is open these driver chips.
drain with an internal circuit equivalent to that shown in
Figure 10. Transaction Sequence
A multidrop bus consists of a 1-Wire bus with multiple The protocol for accessing the DS1922F through the
slaves attached. At standard speed the 1-Wire bus has 1-Wire port is as follows:
a maximum data rate of 16.3kbps. The speed can be ●● Initialization
boosted to 142kbps by activating the overdrive mode. The ●● ROM Function Command
DS1922F is not guaranteed to be fully compliant to the
●● Memory/Control Function Command
iButton device standard. Its maximum data rate in stan-
dard speed is 15.4kbps and 125kbps in overdrive speed. ●● Transaction/Data
VPUP
BUS MASTER DS1922F 1-Wire PORT

RPUP
DATA
Rx Rx
Tx IL Tx
Rx = RECEIVE
Tx = TRANSMIT
OPEN-DRAIN
100Ω MOSFET
PORT PIN
Figure 10. Hardware Configuration

Initialization use a process of elimination to identify the registration

All transactions on the 1-Wire bus begin with an initializa- numbers of all slave devices. For each bit of the registra-
tion sequence. The initialization sequence consists of a tion number, starting with the least significant bit, the bus
reset pulse transmitted by the bus master followed by master issues a triplet of time slots. On the first slot, each
presence pulse(s) transmitted by the slave(s). The pres- slave device participating in the search outputs the true
ence pulse lets the bus master know that the DS1922F is value of its registration number bit. On the second slot,
on the bus and is ready to operate. For more details, see each slave device participating in the search outputs the
the 1-Wire Signaling section. complemented value of its registration number bit. On
the third slot, the master writes the true value of the bit
1-Wire ROM Function Commands to be selected. All slave devices that do not match the
bit written by the master stop participating in the search.
Once the bus master has detected a presence, it can
If both of the read bits are zero, the master knows that
issue one of the eight ROM function commands that the
slave devices exist with both states of the bit. By choosing
DS1922F supports. All ROM function commands are 8
which state to write, the bus master branches in the ROM
bits long. A list of these commands follows (see the flow-
code tree. After one complete pass, the bus master knows
chart in Figure 11).
the registration number of a single device. Additional
Read ROM [33h] passes identify the registration numbers of the remaining
This command allows the bus master to read the devices. Refer to Application Note 187: 1-Wire Search
DS1922F’s 8-bit family code, unique 48-bit serial number, Algorithm for a detailed discussion, including an example.
and 8-bit CRC. This command can only be used if there Conditional Search ROM [ECh]
is a single slave on the bus. If more than one slave is
The Conditional Search ROM command operates simi-
present on the bus, a data collision occurs when all slaves
larly to the Search ROM command except that only those
try to transmit at the same time (open drain produces a
devices that fulfill certain conditions participate in the
wired-AND result). The resultant family code and 48-bit
search. This function provides an efficient means for the
serial number results in a mismatch of the CRC.
bus master to identify devices on a multidrop system that
Match ROM [55h] have to signal an important event. After each pass of the
The Match ROM command, followed by a 64-bit ROM conditional search that successfully determined the 64-bit
sequence, allows the bus master to address a specific ROM code for a specific device on the multidrop bus,
DS1922F on a multidrop bus. Only the DS1922F that that particular device can be individually accessed as if
exactly matches the 64-bit ROM sequence responds to a Match ROM had been issued, since all other devices
the following memory function command. All other slaves have dropped out of the search process and are waiting
wait for a reset pulse. This command can be used with a for a reset pulse.
single device or multiple devices on the bus. The DS1922F responds to the Conditional Search ROM
command if one of the three alarm flags of the Alarm
Search ROM [F0h] Status register (address 0214h) reads 1. The temperature
When a system is initially brought up, the bus master alarm only occurs if enabled (see the Temperature Sensor
might not know the number of devices on the 1-Wire Alarm section). The BOR alarm is always enabled. The
bus or their registration numbers. By taking advantage first alarm that occurs makes the device respond to the
of the wired-AND property of the bus, the master can Conditional Search ROM command.

Skip ROM [CCh] command sets the DS1922F in the overdrive mode (OD =
This command can save time in a single-drop bus sys- 1). All communication following this command must occur
tem by allowing the bus master to access the memory at overdrive speed until a reset pulse of minimum 690μs
functions without providing the 64-bit ROM code. For duration resets all devices on the bus to standard speed
example, if more than one slave is present on the bus and (OD = 0).
a Read command is issued following the Skip ROM com- When issued on a multidrop bus, this command sets all
mand, data collision occurs on the bus as multiple slaves overdrive-supporting devices into overdrive mode. To
transmit simultaneously (open-drain pulldowns produce a subsequently address a specific overdrive-supporting
wired-AND result). device, a reset pulse at overdrive speed must be issued
followed by a Match ROM or Search ROM command
Resume [A5h] sequence. This speeds up the time for the search pro-
The DS1922F must be accessed several times before cess. If more than one slave supporting overdrive is pres-
a mission starts. In a multidrop environment this means ent on the bus and the Overdrive-Skip ROM command is
that the 64-bit ROM code after a Match ROM command followed by a Read command, data collision occurs on
must be repeated for every access. To maximize the the bus as multiple slaves transmit simultaneously (open-
data throughput in a multidrop environment, the Resume drain pulldowns produce a wired-AND result).
command was implemented. This command checks the
status of the RC bit and, if it is set, directly transfers Overdrive-Match ROM [69h]
control to the memory/control functions, similar to a Skip The Overdrive-Match ROM command followed by a
ROM command. The only way to set the RC bit is through 64-bit ROM sequence transmitted at overdrive speed
successfully executing the Match ROM, Search ROM, allows the bus master to address a specific DS1922F on
or Overdrive-Match ROM command. Once the RC bit is a multidrop bus and to simultaneously set it in overdrive
set, the device can repeatedly be accessed through the mode. Only the DS1922F that exactly matches the 64-bit
Resume command function. Accessing another device on ROM sequence responds to the subsequent memory/
the bus clears the RC bit, preventing two or more devices control function command. Slaves already in overdrive
from simultaneously responding to the Resume command. mode from a previous Overdrive-Skip ROM or success-
ful Overdrive-Match ROM command remain in overdrive
Overdrive-Skip ROM [3Ch] mode. All overdrive-capable slaves return to standard
On a single-drop bus this command can save time by speed at the next reset pulse of minimum 690μs duration.
allowing the bus master to access the memory/control The Overdrive-Match ROM command can be used with a
functions without providing the 64-bit ROM code. Unlike single or multiple devices on the bus.
the normal Skip ROM command, the Overdrive-Skip ROM

BUS MASTER Tx
RESET PULSE
FROM FIGURE 11b
FROM MEMORY FUNCTIONS
OD N
RESET PULSE? OD = 0
BUS MASTER Tx ROM DS1922F Tx

FUNCTION COMMAND PRESENCE PULSE
33h 55h F0h ECh

N N N N TO FIGURE 11b
READ ROM MATCH ROM SEARCH ROM CONDITIONAL SEARCH
COMMAND? COMMAND? COMMAND? COMMAND?
Y Y Y Y
RC = 0 RC = 0 RC = 0 RC = 0
N CONDITION
MET?
DS1922F Tx BIT 0 DS1922F Tx BIT 0

DS1922F Tx
FAMILY CODE MASTER Tx BIT 0 DS1922F Tx BIT 0 DS1922F Tx BIT 0
(1 BYTE) MASTER Tx BIT 0 MASTER Tx BIT 0
N N N
BIT 0 MATCH? BIT 0 MATCH? BIT 0 MATCH?
Y Y
Y
DS1922F Tx
SERIAL NUMBER MASTER Tx BIT 1 DS1922F Tx BIT 1 DS1922F Tx BIT 1
(6 BYTES) MASTER Tx BIT 1 MASTER Tx BIT 1
N N N
Y Y Y

DS1922F Tx
MASTER Tx BIT 63 DS1922F Tx BIT 63 DS1922F Tx BIT 63
CRC BYTE
MASTER Tx BIT 63 MASTER Tx BIT 63
N N N
Y Y Y
RC = 1 RC = 1 RC = 1
TO FIGURE 11b
FROM FIGURE 11b
TO MEMORY FUNCTIONS
Figure 11a. ROM Functions Flowchart

TO FIGURE 11a
FROM FIGURE 11a CCh A5h 3Ch 69h

SKIP ROM N RESUME N OVERDRIVE- N OVERDRIVE- N
COMMAND? COMMAND? SKIP ROM? MATCH ROM?
Y Y Y Y
RC = 0 RC = 0; OD = 1 RC = 0; OD = 1
N
RC = 1?
MASTER Tx Y MASTER Tx BIT 0

RESET?
(SEE NOTE)
MASTER Tx Y N
BIT 0 MATCH? OD = 0
RESET?
N
Y
MASTER Tx BIT 1
(SEE NOTE)
N
BIT 1 MATCH? OD = 0
MASTER Tx BIT 63
(SEE NOTE)
N
BIT 63 MATCH? OD = 0
RC = 1
FROM FIGURE 11a
TO FIGURE 11a
NOTE: THE OD FLAG REMAINS AT 1 IF THE DEVICE WAS ALREADY AT OVERDRIVE SPEED BEFORE THE OVERDRIVE-MATCH ROM COMMAND WAS ISSUED.
Figure 11b. ROM Functions Flowchart (continued)

1-Wire Signaling in overdrive mode and tRSTL is no longer than 80μs, the
The DS1922F requires strict protocols to ensure data device remains in overdrive mode.
integrity. The protocol consists of four types of signaling After the bus master has released the line, it goes into
on one line: reset sequence with reset pulse and pres- receive mode (Rx). Now the 1-Wire bus is pulled to VPUP
ence pulse, write-zero, write-one, and read-data. Except through the pullup resistor or, in the case of a DS2480B
for the presence pulse, the bus master initiates all these driver, through active circuitry. When the threshold VTH is
signals. The DS1922F can communicate at two differ- crossed, the DS1922F waits for tPDH and then transmits
ent speeds: standard speed and overdrive speed. If not a presence pulse by pulling the line low for tPDL. To detect
explicitly set into the overdrive mode, the DS1922F com- a presence pulse, the master must test the logical state of
municates at standard speed. While in overdrive mode the 1-Wire line at tMSP.
the fast timing applies to all waveforms. The tRSTH window must be at least the sum of tPDH-
To get from idle to active, the voltage on the 1-Wire line MAX, tPDLMAX, and tRECMIN. Immediately after tRSTH is
needs to fall from VPUP below the threshold VTL. To get expired, the DS1922F is ready for data communication. In
from active to idle, the voltage needs to rise from VILMAX a mixed population network, tRSTH should be extended to
past the threshold VTH. The time it takes for the voltage minimum 480μs at standard speed and 48μs at overdrive
to make this rise is seen in Figure 12 as “ε” and its dura- speed to accommodate other 1-Wire devices.
tion depends on the pullup resistor (RPUP) used and the
capacitance of the 1-Wire network attached. The voltage
Read/Write Time Slots
VILMAX is relevant for the DS1922F when determining a Data communication with the DS1922F takes place in
logical level, not triggering any events. time slots that carry a single bit each. Write time slots
transport data from bus master to slave. Read time slots
The initialization sequence required to begin any com-
transfer data from slave to master. The definitions of the
munication with the DS1922F is shown in Figure 12. A
write and read time slots are illustrated in Figure 13.
reset pulse followed by a presence pulse indicates the
DS1922F is ready to receive data, given the correct ROM All communication begins with the master pulling the data
and memory function command. If the bus master uses line low. As the voltage on the 1-Wire line falls below
slew-rate control on the falling edge, it must pull down the the threshold VTL, the DS1922F starts its internal timing
line for tRSTL + tF to compensate for the edge. A tRSTL generator that determines when the data line is sampled
duration of 690μs or longer exits the overdrive mode, during a write time slot and how long data is valid during
returning the device to standard speed. If the DS1922F is a read time slot.
MASTER Tx "RESET PULSE" MASTER Rx "PRESENCE PULSE"

ε
tMSP
VPUP
VIHMASTER
VTH
VTL
VILMAX
0V
tPDH
tRSTL tPDL tREC
tF
tRSTH
RESISTOR MASTER DS1922F
Figure 12. Initialization Procedure: Reset and Presence Pulse

Master-to-Slave and branch points can add up or cancel each other to

For a write-one time slot, the voltage on the data line some extent. Such reflections are visible as glitches or
must have crossed the VTH threshold before the write- ringing on the 1-Wire communication line. Noise coupled
one low time tW1LMAX is expired. For a write-zero time onto the 1-Wire line from external sources can also result
slot, the voltage on the data line must stay below the in signal glitching. A glitch during the rising edge of a
VTH threshold until the write-zero low time tW0LMIN is time slot can cause a slave device to lose synchroniza-
expired. The voltage on the data line should not exceed tion with the master and, as a consequence, result in a
VILMAX during the entire tW0L or tW1L window. After the Search ROM command coming to a dead end or cause
VTH threshold has been crossed, the DS1922F needs a a device-specific function command to abort. For better
recovery time tREC before it is ready for the next time slot. performance in network applications, the DS1922F uses
a new 1-Wire front-end, which makes it less sensitive to
Slave-to-Master noise and also reduces the magnitude of noise injected by
A read-data time slot begins like a write-one time slot. the slave device itself.
The voltage on the data line must remain below VTL until The DS1922F’s 1-Wire front-end differs from traditional
the read low time tRL is expired. During the tRL window, slave devices in four characteristics:
when responding with a 0, the DS1922F starts pulling
the data line low; its internal timing generator determines 1) The falling edge of the presence pulse has a con-
when this pulldown ends and the voltage starts rising trolled slew rate. This provides a better match to the
again. When responding with a 1, the DS1922F does not line impedance than a digitally switched transistor,
hold the data line low at all, and the voltage starts rising converting the high-frequency ringing known from
as soon as tRL is over. traditional devices into a smoother low-bandwidth tran-
sition. The slew-rate control is specified by the param-
The sum of tRL + δ (rise time) on one side and the internal eter tFPD, which has different values for standard and
timing generator of the DS1922F on the other side define overdrive speed.
the master sampling window (tMSRMIN to tMSRMAX) in
which the master must perform a read from the data line. 2) There is additional lowpass filtering in the circuit that
For most reliable communication, tRL should be as short detects the falling edge at the beginning of a time slot.
as permissible and the master should read close to but This reduces the sensitivity to high-frequency noise.
no later than tMSRMAX. After reading from the data line, This additional filtering does not apply at overdrive
the master must wait until tSLOT is expired. This guaran- speed.
tees sufficient recovery time tREC for the DS1922F to get 3) There is a hysteresis at the low-to-high switching
ready for the next time slot. Note that tREC specified here- threshold VTH. If a negative glitch crosses VTH but
in applies only to a single DS1922F attached to a 1-Wire does not go below VTH - VHY, it is not recognized
line. For multiple device configurations, tREC must be (Figure 14, Case A). The hysteresis is effective at any
extended to accommodate the additional 1-Wire device 1-Wire speed.
input capacitance. Alternatively, an interface that performs 4) There is a time window specified by the rising edge
active pullup during the 1-Wire recovery time such as the hold-off time tREH during which glitches are ignored,
DS2482-x00 or DS2480B 1-Wire line drivers can be used. even if they extend below VTH - VHY threshold (Figure
14, Case B, tGL < tREH). Deep voltage droops or
Improved Network Behavior glitches that appear late after crossing the VTH thresh-
(Switchpoint Hysteresis) old and extend beyond the tREH window cannot be
In a 1-Wire environment line termination is possible only filtered out and are taken as the beginning of a new
during transients controlled by the bus master (1-Wire time slot (Figure 14, Case C, tGL ≥ tREH).
driver). 1-Wire networks, therefore, are susceptible to Devices that have the parameters tFPD, VHY, and
noise of various origins. Depending on the physical size tREH specified in their electrical characteristics use the
and topology of the network, reflections from end points improved 1-Wire front-end.

WRITE-ONE TIME SLOT
tW1L
VPUP
VIHMASTER
VTH
VTL
VILMAX
0V
ε
tF
tSLOT
RESISTOR MASTER
WRITE-ZERO TIME SLOT
tW0L
VPUP
VIHMASTER
VTH
VTL
VILMAX
0V
ε
tF tREC
tSLOT
RESISTOR MASTER
READ-DATA TIME SLOT

tMSR
tRL
VPUP
VIHMASTER
VTH MASTER
SAMPLING
VTL WINDOW
VILMAX
0V
δ
tF tREC
tSLOT
RESISTOR MASTER DS1922F
Figure 13. Read/Write Timing Diagrams

tREH tREH
VPUP
VTH
VHY
CASE A CASE B CASE C

0V
tGL tGL
Figure 14. Noise Suppression Scheme
POLYNOMIAL = X16 + X15 + X2 + 1
1ST 2ND 3RD 4TH 5TH 6TH 7TH 8TH

X0 X1 X2 X3 X4 X5 X6 X7
9TH 10TH 11TH 12TH 13TH 14TH 15TH 16TH

X8 X9 X10 X11 X12 X13 X14 X15 X16 CRC OUTPUT
INPUT DATA
Figure 15. CRC-16 Hardware Description and Polynomial
CRC Generation is always communicated in the inverted form. A CRC gen-

The DS1922F uses two types of CRCs. One CRC is an erator inside the DS1922F (Figure 15) calculates a new
8-bit type and is stored in the most significant byte of the 16-bit CRC as shown in the command flowchart of Figure
64-bit ROM. The bus master can compute a CRC value 9. The bus master compares the CRC value read from the
from the first 56 bits of the 64-bit ROM and compare it to device to the one it calculates from the data and decides
the value stored within the DS1922F to determine if the whether to continue with an operation or to reread the por-
ROM data has been received error-free. The equivalent tion of the data with the CRC error. With the initial pass
polynomial function of this CRC is X8 + X5 + X4 + 1. This through the Read Memory with CRC flowchart, the 16-bit
8-bit CRC is received in the true (noninverted) form, and CRC value is the result of shifting the command byte into
it is computed at the factory and lasered into the ROM. the cleared CRC generator, followed by the two address
bytes and the data bytes. The password is excluded from
The other CRC is a 16-bit type, generated according the CRC calculation. Subsequent passes through the
to the standardized CRC-16 polynomial function x16 + Read Memory with CRC flowchart generate a 16-bit CRC
x15 + x2 + 1. This CRC is used for error detection when that is the result of clearing the CRC generator and then
reading register pages or the data-log memory using the shifting in the data bytes.
Read Memory with CRC command and for fast verifica-
tion of a data transfer when writing to or reading from the With the Write Scratchpad command, the CRC is gener-
scratchpad. In contrast to the 8-bit CRC, the 16-bit CRC ated by first clearing the CRC generator and then shifting

in the command code, the target addresses TA1 and TA2, in the command code, the target addresses TA1 and TA2,
and all the data bytes. The DS1922F transmits this CRC the E/S byte, and the scratchpad data starting at the target
only if the data bytes written to the scratchpad include address. The DS1922F transmits this CRC only if the read-
scratchpad ending offset 11111b. The data can start at ing continues through the end of the scratchpad, regard-
any location within the scratchpad. less of the actual ending offset. For more information on
With the Read Scratchpad command, the CRC is gener- generating CRC values, refer to Application Note 27.
ated by first clearing the CRC generator and then shifting
Command-Specific 1-Wire Communication Protocol—Legend

SYMBOL DESCRIPTION
RST 1-Wire reset pulse generated by master.
PD 1-Wire presence pulse generated by slave.
Select Command and data to satisfy the ROM function protocol.
WS Command “Write Scratchpad.”
RS Command “Read Scratchpad.”
CPS Command “Copy Scratchpad with Password.”
RMC Command “Read Memory with Password and CRC.”
CM Command “Clear Memory with Password.”
FC Command “Forced Conversion.”
SM Command “Start Mission with Password.”
STP Command “Stop Mission with Password.”
TA Target Address TA1, TA2.
TA–E/S Target Address TA1, TA2 with E/S byte.
<Data to EOS> Transfer of as many data bytes as are needed to reach the scratchpad offset 1Fh.
<Data to EOP> Transfer of as many data bytes as are needed to reach the end of a memory page.
<PW/Dummy> Transfer of 8 bytes that either represent a valid password or acceptable dummy data.
<32 Bytes> Transfer of 32 bytes.
<Data> Transfer of an undetermined amount of data.
FFh Transmission of one FFh byte.
CRC-16 Transfer of an inverted CRC-16.
FF Loop Indefinite loop where the master reads FF bytes.
AA Loop Indefinite loop where the master reads AA bytes.

Command-Specific 1-Wire Communication Protocol—Color Codes

Master-to-Slave Slave-to-Master
1-Wire Communication Examples
Write Scratchpad, Reaching the End of the Scratchpad (Cannot Fail)

RST PD Select WS TA <Data to EOS> CRC-16 FF Loop
Read Scratchpad (Cannot Fail)

RST PD Select RS TA-E/S <Data to EOS> CRC-16 FF Loop
Copy Scratchpad with Password (Success)

RST PD Select CPS TA-E/S <PW/Dummy> FF Loop
Copy Scratchpad with Password (Fail TA-E/S or Password)

RST PD Select CPS TA-E/S <PW/Dummy> FF Loop
Read Memory with Password and CRC (Success)

RST PD Select RMC TA <PW/Dummy> <Data to EOP> CRC-16
<32 Bytes> CRC-16 FF Loop
Loop
Read Memory with Password and CRC (Fail Password or Address)
RST PD Select RMC TA <PW/Dummy> FF Loop
Clear Memory with Password

RST PD Select CM <PW/Dummy> FFh FF Loop
To verify success, read the General Status register at address 0215h. If MEMCLR is 1, the command was
executed successfully.

1-Wire Communication Examples (continued)
Forced Conversion
RST PD Select FC FFh FF Loop
To read the result and to verify success, read the addresses 020Ch to 020Fh (results) and the device samples
counter at address 0223h to 0225h. If the count has incremented, the command was executed successfully.
Start Mission with Password

RST PD Select SM <PW/Dummy> FFh FF Loop
To verify success, read the General Status register at address 0215h. If MIP is 1 and MEMCLR is 0, the command
was executed successfully.
Stop Mission with Password

RST PD Select STP <PW/Dummy> FFh FF Loop
To verify success, read the General Status register at address 0215h. If MIP is 0, the command was executed
successfully.
Mission Example: Prepare Step 1: Clear the data of the previous mission.
and Start a New Mission Step 2: Write the setup data to register page 1.
Assumption: The previous mission has been ended by Step 3: Start the new mission.
using the Stop Mission command. Passwords are not Step 1: Clear the data of the previous mission.
enabled.
With only a single device connected to the bus master, the
Starting a mission requires three steps: communication of step 1 looks like this:
MASTER MODE DATA (LSB FIRST) COMMENTS

Tx (Reset) Reset pulse
Rx (Presence) Presence pulse
Tx CCh Issue “Skip ROM” command
Tx 96h Issue “Clear Memory” command
Tx <8 FFh bytes> Send dummy password
Tx FFh Send dummy byte

Step 2: Write the setup data to register page 1. • Alarm Controls (Response to Conditional Search)
During the setup, the device needs to learn the following • General Mission Parameters (e.g., Channels to Log
information: and Logging Format, Rollover, Start Mode)
• Time and Date • Mission Start Delay
• Sample Rate The following data sets up the DS1922F for a mission that
• Alarm Thresholds logs temperature using 8-bit format.
ADDRESS DATA EXAMPLE VALUES FUNCTION

0200h 00h
0201h 30h 15:30:00 hours Time
0202h 15h
0203h 01h
0204h 04h 1st of April in 2008 Date
0205h 08h
0206h 0Ah
Every 30 seconds (EHSS = 1) Sample rate
0207h 00h
0208h 08h 18°C low
Temperature alarm thresholds
0209h F2h 135°C high
020Ah 00h
(Don’t care) (Not applicable with DS1922F)
020Bh FFh
020Ch FFh
020Dh FFh
(Don’t care) Clock through read-only registers
020Eh FFh
020Fh FFh
0210h 02h Enable high alarm Temperature alarm control
0211h FCh Disabled (Not applicable with DS1922F)
0212h 01h On (enabled), EHSS = 1 (high sample rate) RTC oscillator control, sample rate selection
0213h C1h Normal start; no rollover; 8-bit temperature log General mission control
0214h FFh
(Don’t care) Clock through read-only registers
0215h FFh
0216h 5Ah
0217h 00h 90 minutes Mission start delay
0218h 00h

With only a single device connected to the bus master, the

communication of step 2 looks like this:

Tx 0Fh Issue “Write Scratchpad” command
Tx 00h TA1, beginning offset = 00h
Tx 02h TA2, address = 0200h
Tx <25 Data Bytes> Write 25 bytes of data to scratchpad
Tx <7 FFh Bytes> Write through the end of the scratchpad
Tx AAh Issue “Read Scratchpad” command
Rx 00h Read TA1, beginning offset = 00h
Rx 02h Read TA2, address = 0200h
Rx 1Fh Read E/S, ending offset = 1Fh, flags = 0h
Rx <32 Data Bytes> Read scratchpad data and verify
Tx 99h Issue “Copy Scratchpad” command
Tx 00h TA1
Tx 02h TA2 (AUTHORIZATION CODE)
Tx 1Fh E/S
Tx <8 FFh Bytes> Send dummy password
Step 3: Start the new mission. If step 3 was successful, the MIP bit in the General Status
With only a single device connected to the bus master, the register is 1, the MEMCLR bit is 0, and the mission start
communication of step 3 looks like this: delay counts down.

Tx CCh Issue “Start Mission” command
Tx <8 FFh Bytes> Send dummy password
Tx FFh Send dummy byte

Software Correction Algorithm The correction algorithm consists of two steps: prepa-
ration and execution. By means of the family code the
for Temperature preparation step verifies whether the device actually is
The accuracy of high-resolution temperature conversion a DS1922. Then the configuration byte is checked to
results (forced conversion as well as temperature logs) identify the type of DS1922 (L, T or F). If it is the cor-
can be improved through a correction algorithm. The rect device, the data for software correction is read and
data needed for this software correction is stored in the converted from binary to decimal °C format. Next, three
calibration memory (memory page 18, duplicated in page coefficients A, B, and C are computed. In the execution
19). This data consists of reference temperature (Tr) and step, the temperature reading as delivered by the DS1922
conversion result (Tc) for two different temperatures. See is first converted from the low-byte/high-byte format (TcL,
the Temperature Conversion section for the binary num- TcH) to °C (Tc) and then corrected to TCORR. Once step
ber format. 1 is performed, the three coefficients can be used repeat-
The software correction algorithm requires two addi- edly to correct any temperature reading and temperature
tional values, which are not stored in the device. These log of the same device.
values, Tr1 and Offset, are derived from the device
configuration byte.
ADDRESS DESIGNATOR DESCRIPTION

0240h Tr2H Cold-reference temperature, high byte
0241h Tr2L Cold-reference temperature, low byte
0242h Tc2H Conversion result at cold-reference temperature, high byte
0243h Tc2L Conversion result at cold-reference temperature, low byte
0244h Tr3H Hot-reference temperature, high byte
0245h Tr3L Hot-reference temperature, low byte
0246h Tc3H Conversion result at hot-reference temperature, high byte
0247h Tc3L Conversion result at hot-reference temperature, low byte
Step 1. Preparation
Read the 64-bit ROM to obtain the family code. If family code ≠ 41h, then stop (wrong device).
Read the configuration byte at address 0226h.
If code = 40h, then Tr1 = 60, Offset = 41 (DS1922L)
If code = 60h, then Tr1 = 90, Offset = 1 (DS1922T)
If code = C0h, then Tr1 = 130, Offset = -14 (DS1922F)
For all other codes, stop (wrong device).
Tr2 = Tr2H/2 + Tr2L/512 - Offset (convert from binary to °C)
Tr3 = Tr3H/2 + Tr3L/512 - Offset (convert from binary to °C)
Tc2 = Tc2H/2 + Tc2L/512 - Offset (convert from binary to °C)
Tc3 = Tc3H/2 + Tc3L/512 - Offset (convert from binary to °C)
Err2 = Tc2 - Tr2
Err3 = Tc3 - Tr3
Err1 = Err2
B = (Tr22 - Tr12) x (Err3 - Err1)/[(Tr22 - Tr12) x (Tr3 - Tr1) + (Tr32 - Tr12) x (Tr1 - Tr2)]
A = B x (Tr1 - Tr2) / (Tr22 - Tr12)
C = Err1 - A x Tr12 - B x Tr1
Step 2. Execution
TC = TcH/2 + TcL/512 - Offset (convert from binary to °C)
TCORR = Tc - (A x Tc2 + B x Tc + C) (the actual correction)
Numerical Correction Example Ordering Information

CONVERTED DATA FROM PART TEMP RANGE PIN-PACKAGE
ERROR VALUES
CALIBRATION MEMORY DS1922F# +15°C to +140°C F6 Can
Tr1 = 130°C — #Denotes a RoHS-compliant device that may include lead(Pb)
Tr2 = 135.694°C Err2 = -0.0690°C that is exempt under the RoHS requirements.
Tr3 = 139.9765°C Err3 = -0.0390°C
Tc2 = 135.625°C Err1 = -0.0690°C Accessories
Tc3 = 139.9375°C — PART DESCRIPTION
DS9490R# USB to 1-Wire/iButton Can Adapter
APPLICATION OF DS9481R-3C7+ USB to 1-Wire/iButton Can 3.3V Adapter
RESULTING CORRECTION CORRECTION DS1402-RC3+ Reader for DS1922F
COEFFICIENTS COEFFICIENTS TO SAMPLE
READING
B = -0.186564 — Package Information

A = 0.000702/°C TC = 133.75°C For the latest package outline information and land patterns
(footprints), go to www.maximintegrated.com/packages. Note
C = 12.317530°C TCORR= 133.824°C that a “+”, “#”, or “-” in the package code indicates RoHS status
Note: For accuracy reasons, if the TCORR result is below only. Package drawings may show a different suffix character, but
+130°C, discard TCORR and use the uncorrected TC value the drawing pertains to the package regardless of RoHS status.
instead. The software correction requires floating-point
arithmetic (24-bit or better). Suitable math libraries for PACKAGE PACKAGE OUTLINE LAND
microcontrollers are found on various websites and are TYPE CODE NO. PATTERN NO.
included in cross-compilers.
F6 Can IB#CLV 21-0750 —
Pin Configuration

Revision History
REVISION REVISION PAGES
DESCRIPTION
NUMBER DATE CHANGED
0 4/15 Initial release —
Conditions for parameter “Conversion With Software Correction” corrected from “+130°C
1 5/15 3
to +140°C” to “+115°C to +140°C”.
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim Integrated’s website at www.maximintegrated.com.
Maxim Integrated cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim Integrated product. No circuit patent licenses
are implied. Maxim Integrated reserves the right to change the circuitry and specifications without notice at any time. The parametric values (min and max limits)
shown in the Electrical Characteristics table are guaranteed. Other parametric values quoted in this data sheet are provided for guidance.
Maxim Integrated and the Maxim Integrated logo are trademarks of Maxim Integrated Products, Inc. © 2015 Maxim Integrated Products, Inc. │ 45

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DS1922F Autoclave Temperature Logger

with 8KB Data-Log Memory Developer Guide

General Description Benefits and Features

iButton and 1-Wire are registered trademarks of Maxim Integrated

19-7599; Rev 1; 5/15

Absolute Maximum Ratings

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

www.maximintegrated.com Maxim Integrated │ 2

Electrical Characteristics (continued)

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

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Electrical Characteristics (continued)

iButton is a registered trademarks of Maxim Integrated Products, Inc.

www.maximintegrated.com Maxim Integrated │ 4

RTC ACCURACY (TYPICAL)

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Detailed Description a ROM function command is successfully executed, the

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THERMAL CALIBRATION MEMORY

CONTROL DATA-LOG MEMORY

Figure 1. Block Diagram

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BUS 1-Wire NET

COMMAND LEVEL: AVAILABLE COMMANDS: DATA FIELD AFFECTED:

WRITE SCRATCHPAD 256-BIT SCRATCHPAD, FLAGS

Figure 2. Hierarchical Structure for 1-Wire Protocol

8-BIT 8-BIT FAMILY CODE

MSB LSB MSB LSB MSB LSB

Figure 3. 64-Bit Lasered ROM

1ST 2ND 3RD 4TH 5TH 6TH 7TH 8TH

Figure 4. 1-Wire CRC Generator

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Memory temperature readings. See the Software Correction

32-BYTE INTERMEDIATE STORAGE

0020h TO 01BFh GENERAL-PURPOSE SRAM (R/W) PAGES 1 TO 13

32-BYTE DEVICE SIGNATURE

0200h TO 021Fh 32-BYTE REGISTER PAGE 1 PAGE 16

0220h TO 023Fh 32-BYTE REGISTER PAGE 2 PAGE 17

0240h TO 025Fh CALIBRATION MEMORY PAGE 1 (R/W) PAGE 18

0260h TO 027Fh CALIBRATION MEMORY PAGE 2 (R/W) PAGE 19

0280h TO 0FFFh (RESERVED FOR FUTURE EXTENSIONS) PAGES 20 TO 127

1000h TO 2FFFh DATA-LOG MEMORY (READ ONLY) PAGES 128 TO 383

Figure 5. Memory Map

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Figure 6. DS1922F Register Pages Map

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0223h Low Byte Device

0226h Configuration Code Flavor R R

0230h First Byte Full

Figure 6. DS1922F Register Pages Map (continued)

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Detailed Register Descriptions Sample Rate

Sample Rate Register

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Temperature Conversion This equation is valid for converting temperature readings

Latest Temperature Conversion Result Register

Table 1. Temperature Conversion Examples

Table 2. Temperature Alarm Threshold Examples