1 Unit Es Printed

IV B.Tech.
I Sem (R13) ECE : Embedded Systems : UNIT -1 1
UNIT – 1
1. Embedded Systems – Introduction (Definition, Applications and Classification) - 1

2. Elements of Embedded systems ---------------------------------------------------------- 5
3. RISC Vs CISC --------------------------------------------------------------------------------- 8
4. Harvard Architecture & Von-Neumann ----------------------------------------------- 9
5. Memory mapped I/O and Isolated I/O ----------------------------------------------- 10
6. Little-Endian and Big-Endian -------------------------------------------------------------- 11
7. Low Power RISC- MSP 430 : Introduction & Variants of MSP 430 family ------ 12
8. MSP430F2013 - Block diagram & features --------------------------------------------- 18
9. Memory map of MSP430 -------------------------------------------------------------------- 20
10. MSP430 –CPU architecture & registers -------------------------------------------------- 23
11. Addressing modes of MSP430 ------------------------------------------------------------ 28
12. Instruction formats & Instruction Timings of MSP430 ----------------------------- 31
13. Instruction set of MSP430 ------------------------------------------------------------------ 33
14. Sample Embedded system on MSP430 -------------------------------------------------- 39
1. EMBEDDED SYSTEMS - INTRODUCTION
1.1. Definition :
• An embedded system is an electronic/electro-mechanical system designed to perform a
specific function and is combination of both hardware and firmware (software). The
program instructions written for embedded systems are referred to as firmware, and are
stored in Read-Only-Memory or Flash memory.
• Every ES is unique, and the hardware as well as software is highly specialized to the
application domain. Embedded systems are designed to do some specific task, rather than
be a general purpose computer for multiple tasks.
1.2 . Characteristics of Embedded System

Unlike general purpose computing system, embedded systems have certain specific
characteristics. These characteristics are unique to each embedded system.
1. Application and Domain Specific
2. Reactive and Real Time
3. Operates in harsh environments
4. Distributed
5. Small size and weight
6. Power concerns
1.3. Quality attributes of Embedded Systems
(a) Operational Quality Attributes : These are related to the embedded system when it is in
the operational mode (or) online mode.
1. Response
2. Throughput
3. Reliability
4. Maintainability
5. Security
6. Safety
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IV B.Tech. I Sem (R13) ECE : Embedded Systems : UNIT -1 2
(b) Non-Operational Quality Attributes: These attributes are addressed for the product.
1. Testability and Debug ability
2. Evolvability – can be modified to take advantage of new technology
3. Portability
4. Time to prototype and market
5. Per Unit & Total cost
1.4. Application of Embedded Systems
The embedded systems are used in various domains. Within the domain itself, according to
the application, they may have different functionalities. Each embedded system is designed to
serve the purpose of any one or a combination of the following tasks:
Purpose of Embedded System

 Data Collection/Storage/Representation
 Data communication
 Data signal processing
 Monitoring
 Control
 Application specific user interface
The different applications/Examples of Embedded systems are given below
1. Consumer Electronics: Camcorders, Cameras.

2. Household appliances: Digital TVs, DVD players, Set top boxes, Washing machine,
Refrigerator.
3. Automotive industry: Anti-lock breaking system (ABS), engine control, automatic
navigation system, engine control
4. Home automation & security systems: Air conditioners, sprinklers, fire alarms, closed
circuit television cameras, home security system
5. Telecom: Cellular phones, telephone switches, handset multimedia applications
6. Computer peripherals: Printers, scanners, fax machines
7. Computer networking systems: Network routers, switches, hubs, firewalls
8. Healthcare: EEG, ECG machines.
9. Banking & Retail: Automatic teller machines(ATM), currency counters, point of sales.
10. Card Readers: Barcode, smart card readers.
11. Measurements & Instrumentation : Logic Analyzers, Spectrum analyzers, PLC systems,
Electronic data acquisition and supervisory control system,
industrial process controller, digital meters
12. Missiles and Satellites : Defense, Aerospace, Communication, tracking system

13. Robotics : stepper motor controllers for a robotic system
14. Motor control systems : accurate control of speed and position of dc motor
15. Entertainment systems : video games, music system
16. Signal & Image processing : speech processing, pattern recognizer, video processing

1.5. General Purpose Computing System Vs Embedded System :
General Purpose Computing system Embedded system
It is combination of generic hardware and a It is combination of special purpose hardware

general purpose OS for executing a variety and embedded OS for executing specific set of
of applications. applications
It contains general It may or may not contain an operating system
purpose operating system for functioning.
Applications are alterable (programmable) Applications are non-alterable
by the user. by the user.
Application specific Requirements
Performance is the key deciding factor in
(performance, power requirements, memory
the selection of the system. Always ‘faster
usage, size, design and manufacturing cost, etc)
is better’.
are the key deciding factors.
Less tailored towards reduced operating Highly tailored to take the advantage of the
power requirements, options for different power saving modes supported by the
levels of power management. hardware and the operating system.
For certain category of embedded systems like
Response requirements are not time-critical. mission critical systems, the response time
requirement is highly critical.
Execution behavior is deterministic for certain
Need not be deterministic in execution
types of Embedded systems like ‘Hard Real
behavior.
Time’ systems.
1.6. Classification of Embedded Systems
The classification of embedded system is based on following criteria's:

(a) On generation
(b) On complexity & performance
(c) On deterministic behaviour
(d) On triggering
(a) Classification based on generation
1. First generation(1G):
 Built around 8-bit microprocessors like 8085, Z80 and 4-bit microcontrollers.
 Simple in hardware circuit with firmware developed in Assembly code.
 Examples: Digital telephone keypads, stepper motor control units
2. Second generation(2G):
 Built around 16-bit μp and 8-bit μc.
 They are more complex & powerful than 1G μp & μc.
 Examples: Data Acquisition system (DAS), Supervisory Control and Data
Acquisition systems (SCADA)

3. Third generation(3G):
 Built around 32-bit μp & 16-bit μc.
 A new concept of application and domain specific processors / controllers like
Digital Signal Processors(DSPs), Application Specific Integrated Circuits(ASICs).
 Examples: Robotics, Media, Industrial process control, networking, etc.
4. Fourth generation:
 Built around 64-bit μp & 32-bit μc.
 The concept of System on Chips (SoC), reconfigurable processors, multi-core
processors
 High performance, tight integration, miniaturization, and very powerful.
 Examples: Smart Phones, Mobile Internet Devices
(b) Classification based on Complexity and performance
1. Small-scale:
 Simple applications where the performance requirements are not time-critical.
 Built around low performance and low cost 8 or 16 bit μp/μc.
 Example: an electronic toy
2. Medium-scale:
 Slightly complex in hardware and firmware requirement.
 Built around medium performance and low cost 16 or 32 bit μp/μc.
 Usually contain embedded operating system ( either general purpose / RTOS) for
functioning
 Examples: Industrial machines.
3. Large-scale:
 Highly complex hardware & firmware.
 Built around 32 or 64 bit RISC μp/μc or PLDs or SoC or multi-core processors.
 Response is time-critical.
 Examples: Mission critical applications.
(c) Classification based on deterministic behavior
 This classification is applicable for “Real Time” systems.

 The task execution behavior for an embedded system may be deterministic or non-
deterministic.
 Based on execution behavior Real Time embedded systems are divided into Hard
and Soft.
(d) Classification based on triggering
 Embedded systems which are “Reactive” in nature can be based on triggering.

 Reactive systems can be Event triggered (or) Time triggered

2. ELEMENTS OF EMBEDDED SYSTEM :
Embedded systems are basically designed to regulate a physical variable (or) to

manipulate the state of some devices by sending some signals to the actuators or devices
connected to the output ports of the system, in response to the input signals provided by the end
users or sensors which are connected to the input ports. Hence the embedded systems can be
viewed as a reactive system. The control is achieved by processing the information coming from
the sensors and user interfaces and controlling some actuators that regulate the physical variable.
Common user interface input devices : Keyboards, push button, switches, etc.
Common user interface output devices : LEDs, LCD, Buzzers…etc
Note that it is not necessary that all ES should incorporate these I/O user interfaces. It
depends on the type of application in which the ES is designed. For ex., if the ES is designed for
any handheld application such as a mobile handset, the system should contain user interfaces like
keyboard, display unit, speakers, microphone etc. Some Embedded Systems do not require any
manual intervention for their operation. They automatically sense the variations in the input
parameters using sensors which are connected to the input port, and the processor performs some
pre-defined operations with the help of firmware embedded in the system and sends some
actuating signals to the actuators connected to the output port of the Embedded system.
Sensors  connected to the input port  to sense/detect the changes in the input variables
 converts input variables into electrical signals for any measurements/ control purpose
Actuators  connected at the output port

 converts electrical signals into corresponding physical action .
Figure .1 : Elements of an Embedded System
The memory of the system is responsible for holding the control algorithm and other
important configuration details. Memory for implementing the code may be present on the
processor or may be implemented as a separate chip interfacing the processor. In a controller
based embedded system, the controller may contain internal memory for storing code.

Embedded systems are domain and application specific and are built around a central core.
The core of the embedded system falls into any of the following categories:
1. General purpose and Domain Specific Processors

2. Microprocessors
3. Microcontrollers
4. Digital Signal Processors
5. Application Specific Integrated Circuits (ASIC)
6. Complex Programmable Logic Devices (CPLD’s)
7. Field Programmable Gate Arrays (FPGA)
8. Commercial off-the-shelf components (COTS)
Almost 80% of the embedded systems are processor/ controller based. The processor may be
microprocessor or a microcontroller or digital signal processor, depending on the domain and
application. Most of the ES in industrial control and monitoring applications make use of the
commonly available microprocessors and microcontrollers whereas domains which require signal
processing such as speech coding, speech recognition..etc make use of special kind of digital signal
processors supplied by manufacturers like Analog Devices, Texas Instruments,..etc
Microprocessors
 A microprocessor is a silicon chip representing a central processing unit (CPU), which is
capable of performing arithmetic and logic operations according to a pre-defined set of
instructions.
 In general, the CPU contains ALU, Control Unit and working registers.
 A microprocessor is a dependent unit and it requires the combination of other hardware
like memory, timers, interrupt controller and I/O ports, etc. for proper functioning.
 Microprocessors are used in general purpose applications.
Microcontrollers
 A microcontroller is an integrated chip that contains CPU, data and program memory (
RAM and ROM), special and general purpose registers, Timers, Interrupt control unit and
dedicated I/O ports.
 Since a microcontroller contains all the necessary functional blocks for independent
working, they found greater place in embedded domain.
 Microcontrollers are application oriented and used in domain-specific applications.
Digital Signal Processors

 DSPs are powerful special purpose 8/16/32 bit processors, designed specifically to meet
the computational demands and power constraints of today’s embedded audio, video and
communication applications.
 DSP are 2 to 3 times faster than general purpose microprocessors in signal processing
applications. This is because of the architectural difference between DSP and general
purpose microprocessors.
 DSPs implement algorithms in hardware which speeds up the execution whereas general
purpose processor implement the algorithm in software and the speed of execution
depends primarily on the clock for the processors.
 DSP performs large amount of real-time calculations like FFT(Fast Fourier Transform),
DFT(Discrete Fourier Transform), Convolution, SOP(Sum of Products) calculation etc.
 Audio video signal processing, telecommunication and multimedia applications are typical
examples where DSPs are employed.

Application Specific Integrated Circuit (ASIC)
 ASIC is a microchip designed to perform a specific or unique application.

 It integrates several functions into a single chip there by reduces the system development
cost.
CPLD and FPGA
 The PLDs consists of a large no. of programmable gates on a VLSI chip

 With programmable logic devices like CPLDs and FPGAs, the designs can be quickly
simulated, tested and programmed into devices and immediately tested in live circuits.
 During the design phase, the circuit can be changed by programming the device to get the
desired outputs, because these devices are based on re-writable memory technology.
 These devices are used in Network routers, DSL modem, an automotive navigation system
Commercial off-the-shelf components (COTS)
 Commercial off-the-shelf (COTS) product is one which is used ‘as-is’

 COTS products are designed in such a way to provide easy integration with existing
system components.
 The COTS component itself may be developed around a general purpose or domain
specific processor or ASIC or PLDs.
 The example for COTS product is TCP/IP plug-in module

3. RISC Vs CISC :
RISC and CISC are the two common Instruction Set Architectures (ISA) available for processor
design.
RISC (Reduced Instruction Set Computer)) CISC (Complex Instruction Set Computer)
1 Supports lesser number of instructions. Supports greater number of instructions.
Supports few addressing modes for Supports many addressing modes for
2 memory access and data transfer memory access and data transfer
instructions. instructions.
3 Single, fixed length instructions Variable length instructions
Instructions take fixed amounts of time for Instructions take varying amounts of time
4
execution for execution
Instruction pipelining concept is not
Instruction pipelining works effectively
5 effectively works as different sizes and
and increases the execution speed.
different execution times of instructions.
Orthogonal instruction set (allows each Non-orthogonal set (all instructions are not
6 instruction to operate on any register and allowed to operate on any register and use
use any addressing mode.) any addressing mode.
More silicon usage since more additional
Less silicon usage and decoding logic is not
7 decoder logic is required to implement the
complex.
complex instruction decoding.
Because of large amount of different and
Because of the simple instructions, the
8 complex instructions, the design of compiler
design of compiler is easy.
is complex.
9 A larger number of registers are available. Limited no. of general purpose registers
Operations are performed on registers only. Operations are performed either on registers
10
Memory operations are load and store only. or memory depending on instruction.
Can be Harvard or Von-Neumann
11 With Harvard Architecture.
Architecture.
Programmer needs to write more code to The programmer can achieve the desired
12 execute a task since instructions are simpler functionality with a single instruction.
ones. ( large code sizes) (small code sizes)

4. HARVARD ARCHITECTURE Vs VON-NEUMANN ARCHITECTURE :
Architectures used for processor design are Harvard or Von- Neumann.
Harvard architecture Von-Neumann architecture
It shares single common bus for instruction

It has separate buses for instruction as well as and data fetching. This means that only one
data fetching. This means that, the data memory set of addresses covers both data memory
and program memory are separated. and program memory. The memory map
shows the addresses at which each type of
memory is located.
Low performance as compared to Harvard

Easier to pipeline, so high performance can be
architecture
achieve.
First fetches the instruction and then fetches
It allows simultaneous access to the program and
the data. The two separate fetches slows
data memories. For instance, the CPU can read an
down the controller’s operation.
operand from the data memory at the same time
Because several memory cycles are needed
as it reads the next instruction from the program
to extract a full instruction from memory,
memory.
this architecture is intrinsically less efficient.
Since data memory and program memory are Accidental corruption of program memory
stored physically in different locations, no may occur if data memory and program
chances exist for accidental corruption of memory are stored physically in the same
program memory chip.
A problem with the Harvard architecture is that
constant data (often lookup tables) must be
stored in the program memory because it is
The system is simpler and there is no
nonvolatile. This means that constants cannot be
difference between access to constant and
read in the same way as volatile values from the
variable data.
data memory. Special “table read” instructions
must therefore be provided or part of the
program memory is mapped into data memory
No additional logic is required because,

Separate decoding logic is required, because
Same bus and control signals are used for
separate buses and control signals are used for
accessing for both data memory and
accessing data memory and program memory
program memory.
Comparatively high cost Low cost

5. MEMORY MAPPED I/O & I/O MAPPED I/O :
Memory mapped I/O Port mapped I/O
I/O devices are mapped into the system I/O devices are mapped into a separate
memory map. i.e Common address space for address space. i.e., there is separate
memory and I/O ports (The I/O ports are address space for memory and I/O ports.
viewed as memory locations and are addressed
likewise)
The control signals used for memory operation Different control signals are used for
and I/O operation are same. memory and I/O operations.
2
M/IO = 1 for both Memory and I/O M/IO =1 for memory operation
operations M/IO =0 for I/O operation
Less no. of instructions are for I/O access.

3 All instruction which can access memory can ( only IN and OUT instructions)
be used to access I/O ports.
The data transfer takes place between

4 The data can be moved from any register to Accumulator and I/O port only
I/O port and vice-versa.
The arithmetic, logic and bit manipulation
No instructions are available for direct
instructions which are available for data in
manipulation of I/O data. First the
5 memory can also be used for I/O operations.
processor reads data from I/O port and
Hence the processor can directly manipulate
then manipulates.
data from I/O port.
6 Large number of I/O devices can be interfaced Less no. of I/O devices can be interfaced
Full address space can’t be used for addressing Full address space can be used for
7 Memory, because some locations are allotted addressing Memory, because I/O
for I/O ports. locations are separated from memory.
The entire address bus must be fully decoded Less logic is needed to decode a discrete
8
for every device, which increases the cost address and therefore less cost

5. LITTLE-ENDIAN & BIG-ENDIAN PROCESSORS
 Endianness specifies the order which the data is stored in the memory by processor
operations in a multi byte system.
 Little-endian means lower order data byte is stored in memory at the lowest address and
the higher order data byte at the highest address.
For ex., 4 byte long integer Byte3, Byte2, Byte1, Byte0 will be stored in memory as follows:
Base address 2000 H
Base address+1 2001H
Base address+2 2002 H
 Big-endian means the higher order data byte is stored in memory at the lowest and the
lower order data byte at the highest address.
For ex., 4 byte long integer Byte3, Byte2, Byte1, Byte0 will be stored in memory as follows:
Base address 2000 H

7. INTRODUCTION TO MSP430 MICROCONTROLLERS:
Introduction :
1. The MSP430 microcontroller from Texas Instruments (TI) is a 16-bit RISC based Mixed
Signal Processor with Von-Neumann architecture, designed for low power and portable
applications.
2. The architecture supports different low-power modes, and it is optimized to achieve

extended battery life in portable measurement applications. The digitally controlled
oscillator (DCO) allows wake-up from low-power modes to active mode in less than 1
micro second.
3. It is extremely easy to put the device into a low-power mode. No special instruction is
needed: The mode is controlled by bits in the status register. The MSP430 is awakened by
an interrupt and returns automatically to its low-power mode after handling the interrupt.
4. The address and data buses are 16-bits wide and the registers in CPU are also 16-bits wide.
Hence the registers can be used for either data (or) addresses.
5. Since it has 16-bit address bus, it can address 64KB of memory (RAM/ROM/Flash/Reg).
The amount of on-chip memory varies for different families of MSP430.
6. A wide range of peripherals are available, many of which can run autonomously without
the CPU for most of the time.
7. Many portable devices include liquid crystal displays, which the MSP430 can drive
directly.
8. Some MSP430 devices are classed as application-specific standard products (ASSPs) and
contain specialized analog hardware for various types of measurements.
9. The MSP430 family consists of several devices featuring different sets of peripherals
targeted for various applications : Internal oscillator, Timer including PWM, WDT, Serial
communication interface (USART, I2C, SPI), ADC, DAC, Comparators, Multipliers,
Brownout reset circuitry, Op-Amps for signal conditioning, LCD driver, DMA, built-in
bootstrap loader (BSL) using UART such as RS232 or USB, JTAG interface.. etc.

MAIN CHARACTERISTICS OF MSP430 MICROCONTROLLER
Although there are variants in devices in the family, a MSP430 microcontroller can be
characterized by:
Flash (or) ROM-based low-power MCUs

CPU clock : 8/16 MHz
Operating voltage : 1.8–3.6 V
Power specification overview, as low as:
 0.1 μA RAM retention
 0.7 μA real-time clock mode peration
 160 - 250 µA/MIPS at active operation
 Fast wake-up from standby mode in less than 1 µs.
Device parameters
 Flash/ ROM options: 1 KB – 60 KB
 RAM options: 128 B– 8 KB
 GPIO options: 14 - 80 pins
Other integrated peripherals:
 10/12/16-bit Analogue-to-Digital Converter (ADC);
 12-bit dual Digital-to-Analogue Converter (DAC);
 Comparator-gated Timers;
 Watch Dog Timer
 SPI, I2C, UART
 Operational Amplifiers (OP Amps)
 16×16 multiplier
 Comparator_A
 Temp. sensor
 LCD driver
 Supply Voltage Supervisor (SVS)
 Brown out Reset
16 bit RISC CPU:
 Instructions processing on either bits, bytes or words;
 Compact core design reduces power consumption and cost;
 Compiler efficient;
 27 core instructions;
 7 addressing modes;
 Extensive vectored-interrupt capability.
MSP430X :
There is a new extended version of original MSP430 architecture, called MSP430X, which can
address extra memory with other improvements as well.
 If CPU is MSP430, it has 16-bit address bus and it can address 64 KB of memory
(0x0000 – 0xFFFF)
 If the CPU is MSP430X, it has 20-bit address bus and it can address 1 MB of memory.
The bottom 64 KB of memory from 0x0000 to 0xFFFF is same way as in the original
MSP430. The additional memory from 0x10000 to 0xFFFFF, is available for additional
ROM. This allows larger programs and tables to be stored.

VARIANTS OF MSP430 FAMILY

MSP430 part numbering:
The letters MSP stand for mixed signal processor, which is a reminder that many
MSP 430 practical applications require analog inputs. MSP430 indicates the member of
the 430 MCU platforms.
The letter after MSP430 shows the type of memory.
F
F : flash memory, C : masked ROM
There is a second letter for ASSPs (Application Specific Standard Products) to
show the type of measurement for which they are intended.
G (optional)
E : for electricity (Energy meters), W : for water (flow meters), and
G : for signals that require gain stage (Medical), provided by Op-Amps.
It indicates the generation of the device
1 series : upto 8 MHz,
2 series : upto 16 MHz
4 3 series : Legacy OTP (one time programmable)
4 series : upto 16 MHz with w/LCD
5 series : upto 25 MHz
6 series : upto 25 MHz with w/LCD
6 Model within generation (Various levels of integration within a series)
Memory size and peripheral configuration

19 03 : 128 byes RAM & 1 KB ROM
13 : 128 byes RAM & 2 KB ROM
Temperature range
I
I : -40 to 85 oC, T : -40 to 105 oC, S : 0 to 50 oC
QZW Package (Ball Grid Array/ Pin Grid Array/ Dual In-line Package)
Tape and Reel
R (optional) T = Small Reel (7 –in)
R = Large Reel (11 –in)

MSP430x1xx :
MSP430x1xx Provides a wide range of general-purpose devices from simple versions to complete
systems for processing signals. There is a broad selection of peripherals and some include a
hardware multiplier, which can be used as a basic digital signal processor.
Flash- or ROM-based low-power MCUs
8 MHz Clock, 1.8–3.6 V operation
 0.1 μA RAM retention
 0.7 μA real-time clock mode
 200 μA / MIPS active
 Features fast wake-up from standby mode in less than 6 µs.
Device parameters
 Flash/ROM options: 1–60 KB
 RAM options: 128 B– 2 KB
 GPIO options: 14/22/48 pins
 ADC options: Slope, 10 & 12-bit SAR
Other integrated peripherals: 12-bit DAC, up to 2 16-bit timers, WDT, brown-out reset,
SVS, USART module (UART, SPI), DMA, 16×16 multiplier, Comparator_A, Temp. sensor
MSP430F2xx :
The MSP430F2xx Series are similar to the '1xx generation, but operate at even lower power,
support up to 16 MHz operation, double the speed of earlier devices, while consuming only half
the current at the same speed. It has On-chip clock (VLO) that makes it easier to operate without
an external crystal. Pull-up or pull-down resistors are provided on the inputs to reduce the
number of external components needed. Some come in 14-pin package with PDIP option, which is
attractive for anybody who has to build circuits by hand.
Flash- or ROM-based low-power MCUs
 0.3 μA standby mode (VLO)
 Feature ultra-fast wake-up from standby mode in less than 1 μs
Device parameters
 Flash/ROM options: 1 KB–60 KB
 RAM options: 128 B – 8 KB
 GPIO options: 10/16/24/32/48 pins
 ADC options: Slope, 10 & 12-bit SAR, 16 & 24-bit Sigma Delta
Other integrated peripherals: operational amplifiers, 12-bit DAC, up to 2 16-bit timers,
watchdog timer, brown-out reset, SVS, USI module (I²C, SPI), USCI module, DMA, 16×16
multiplier, Comparator_A+, Temperature sensor

MSP430x3xx :
The MSP430x3xx Series is the oldest generation, designed for portable instrumentation with an
embedded LCD controller. This also includes a frequency-locked loop oscillator that can
automatically synchronize to a low-speed (32 kHz) crystal.
This generation does not support EEPROM memory, only mask ROM and UV- eraseable and one-
time programmable EPROM.
UV erasable and One Time Programmable ROM
16 MHz Clock, 2.5 – 5.5 V operation
Device parameters:
 ROM options: 2–32 KB
 RAM options: 512 B–1 KB
 GPIO options: 14/40 pins
 ADC options: Slope, 14-bit SAR
Other integrated peripherals: LCD controller, multiplier
MSP430x4xx :
MSP430x4xx series can drive LCDs with up to 160 segments. Many of them are ASSPs, but there
are general-purpose devices as well. These devices are used for low power metering and medical
applications.
Flash- or ROM-based ultra-low-power MCUs
FLL and SVS
Device parameters:
 Flash/ROM options: 4 KB– 60 KB
 RAM options: 256 B – 8 KB
 GPIO options: 14/32/48/56/68/72/80 pins
 ADC options: Slope, 10 & 12-bit SAR, 16-bit Sigma Delta
Other integrated peripherals: 12-bit DAC, Op Amps, RTC, up to two 16-bit timers,
watchdog timer, basic timer, brown-out reset, SVS, USART module (UART, SPI), USCI
module, LCD Controller, DMA, 16×16 & 32x32 multiplier, Comparator_A, Temp. sensor

MSP430x5xx series :
The MSP430x5xx Series are able to run up to 25 MHz, have up to 512 KB flash memory and up to
66 KB RAM. Includes an innovative power management module for optimal power consumption
and integrated USB.

Device parameters:
 Flash options: up to 512 KB
 RAM options: up to 66 KB
 ADC options: 10 & 12-bit SAR
 GPIO options: 29/31/47/48/63/67/74/87 pins
Other integrated peripherals: High resolution PWM, 5 V I/O's, USB, backup battery
switch, up to 4 16-bit timers, watchdog timer, Real-Time Clock, brown-out reset, SVS, USCI
module, DMA, 32x32 multiplier, Comp B, temperature sensor
MSP430x6xx series
The MSP430x6xx Series are able to run up to 25 MHz, have up to 512 KB flash memory and up to
66 KB RAM. It includes an innovative power management module for optimal power
consumption and integrated USB.

Device parameters:
 Flash options: up to 512 KB
 RAM options: up to 66 KB
 ADC options: 10 & 12-bit SAR
 GPIO options: 74/90 pins
Other integrated peripherals: USB, LCD, DAC, Comparator_B, DMA, 32x32 multiplier,
power management module (BOR, SVS, SVM, LDO), watchdog timer, RTC, Temp sensor

8. BLOCK DIAGRAM OF MSP430 F2013/ F2003 MICROCONTROLLER
The MSP430 microcontroller from Texas Instruments (TI) is a 16-bit RISC based Mixed
Signal Processor with Von-Neumann architecture, designed for low power and portable
applications.
It is extremely easy to put the device into a low-power mode. No special instruction is
needed: The mode is controlled by bits in the status register. The MSP430 is awakened by
an interrupt and returns automatically to its low-power mode after handling the interrupt.
The address and data buses are 16-bits wide and the registers in CPU are also 16-bits wide.
Hence the registers can be used for either data (or) addresses.
The functional block diagram of the MSP430 F2003/F2013 consists of the following blocks :
On the left is the 16-bit CPU and its supporting hardware, including the clock generator.
The emulation, JTAG interface and Spy-Bi-Wire are used to communicate with a desktop
computer when downloading a program and for debugging.
The main blocks are linked by the memory address bus (MAB) and memory data bus (MDB).
It has flash memory, 1KB in the F2003 or 2KB in the F2013, and 128 bytes of RAM.

Six blocks are shown for peripheral functions (there are many more in larger devices).
Input/output ports, Timer_A, and a watchdog timer, Universal serial interface (USI) and
sigma–delta analog-to-digital converter (SD16_A) are particular features of this device.
The brownout protection comes into action if the supply voltage drops to a dangerous
level. Most devices include this but not some of the MSP430x1xx family.
There are ground and power supply connections. Ground is labeled VSS and is taken to
define 0V. The supply connection is VCC. For many years, the standard for logic was VCC
=+5V but most devices now work from lower voltages and a range of 1.8–3.6V is specified
for the F2013. The performance of the device depends on VCC. For ex., it is unable to
program the flash memory if VCC < 2.2V and the maximum clock frequency of 16MHz is
available only if VCC ≥ 3.3V.
The brownout reset circuit detects low supply voltages such as when a supply voltage is
applied to (or) removed from the VCC terminal. The brownout reset circuit resets the
device by triggering a POR (Power on Reset) signal when power is applied (or) removed.
The brownout circuit is used to provide the proper internal reset signal to the device
during power ON and power OFF.)
The Watchdog Timer (WDT) module restarts the system on occurrence of a software
problem (or) if a selected time interval expires. It is used to detect and recover from
computer malfunction.
During normal operation, the system regularly restarts the watchdog timer to prevent it
from elapsing, or "timing out". If the system fails to restart the watchdog due to a hardware
fault or program error,, the timer will elapse and generate a timeout signal. The timeout
signal is used to initiate corrective actions like placing the system in a safe state and
restoring normal system operation. Remember that the watchdog is active by default and
must either be disabled or regularly cleared before it rolls over. The WDT can also be used
to generate timely interrupts for an application.
The Supply Voltage Supervisor (SVS) is used to monitor the supply voltage or an external
voltage. The SVS can be configured to set a flag or generate a POR reset when the supply
voltage or external voltage drops below a user selected threshold.
The SVS features include:

• Supply voltage VCC monitoring
• Selectable generation of POR
• Output of SVS comparator accessible by software
• Low-voltage condition latched and accessible by software
• 14 selectable threshold levels
• External channel to monitor external voltage

9. MEMORY MAP OF MSP430 :
The MSP430 von-Neumann architecture has address space shared with special function registers
(SFRs), peripherals, RAM, and Flash/ROM memory. The following shows the memory map of the
F2013. Most MSP430 devices have a similar memory map, differing only in the size of the regions
for RAM and ROM.
Figure : Memory map of the MSP430F2013
0000 – 000F Special Function Registers (byte access)
0010 – 00FF Peripheral registers with Byte access
0100 – 01FF Peripheral registers with Word access
0200 – xxxx RAM ( upper boundary varies)
0C00 – 0FFF Bootstrap loader ( not in F20xx)
1000 – 10FF Flash Information memory ( available in Flash devices only)
xxxx - FFBF Flash / ROM ( lower boundary varies)
FFC0 - FFFF Interrupt & Reset Vector Table

Special function registers :

The SFRs are located in the lower 16 bytes of the address space. Some peripheral functions are
configured in the SFRs for enabling and signaling interrupts from peripherals. SFRs must be
accessed using byte instructions only.
Peripheral registers with byte access and peripheral registers with word access:
Provide the main communication between the CPU and peripherals. Some must be accessed as
words and others as bytes. They are grouped in this way to avoid wasting addresses.
The address space from 010h to 0FFh is reserved for 8-bit peripheral modules. These modules
should be accessed with byte instructions.
The address space from 0x0100 to 0x01FF is reserved for 16-bit peripheral modules. These
modules should be accessed with word instructions.
Random access memory:

Used for variables. RAM always starts at address 0x0200 and the end address of RAM depends on
the amount of RAM present on the device. The F2013 has 128 Bytes of RAM.
Bootstrap loader (Flash devices only) :

The MSP430 flash devices contain an address space for boot memory, located between addresses
0xC00 through to 0x0FFF. The “bootstrap loader” is located in this memory space, which is an
external interface that can be used to program the flash memory in addition to the JTAG. This
memory region is not accessible by other applications, so it cannot be overwritten accidentally.
Information memory (Flash devices only) :

A 256B block of flash memory that is intended for storage of nonvolatile data. This might include
serial numbers to identify equipment—an address for a network, for instance—or variables that
should be retained even when power is removed. (It is like an onboard EEPROM, where variables
needed for the next power up can be stored during power down.)
For example, a printer might remember the settings from when it was last used and keep a count
of the total number of pages printed.
Flash memory may be written one byte or word at a time, but must be erased in segments. The
information memory is divided into 2 segments (of 128-bytes each) in 4xx devices, and 4 segments
(of 64 bytes each) in 2xx devices. Segment A contains factory calibration data for the DCO in the
MSP430F2xx family and is protected by default.
Flash/ROM /Code memory:

Holds the program, including the executable code itself and any constant data. The start address
of Flash/ROM depends on the amount of Flash/ROM present on the device. The end address for
Flash/ROM is 0x0FFFF for devices with less that 60KB of Flash/ROM. The F2013 has 2 KB but the
F2003 only 1KB.
Flash can be used for both code and data. Word or byte tables can be stored and used in
Flash/ROM without the need to copy the tables to RAM before using them. The interrupt vector
table is mapped into the upper 16 words of Flash/ROM address space, with the highest priority
interrupt vector at the highest Flash/ROM word address (0x0FFFE).

Interrupt and reset vectors :

Used to handle “exceptions,” when normal operation of the processor is interrupted or when the
device is reset. This table was smaller and started at 0xFFE0 in earlier devices.
The range of addresses has been extended from 64KB to 1MB in the MSP430X. This means
that addresses require 20 bits rather than 16 and the MAB is therefore 20- bits wider. The bottom
64KB of memory from 0x00000 to 0x0FFFF is laid out in exactly the same way as in the original
MSP430. The additional memory, from 0x10000 to 0xFFFFF, is available for additional ROM. This
permits larger programs and tables to be stored.
 The above figure shows - Bits, Bytes, and Words in a Byte-Organized Memory.
 For all devices, each memory location is formed by 1 data byte. The CPU is capable of
addressing data values either as bytes (8 bits) or words (16 bits).
 Bytes are located at even or odd addresses.
 Words are always addressed at an even address, which contain the least significant byte,
followed by the next odd address, which contains the most significant byte.
 For 8-bit operations, the data can be accessed from either odd or even addresses, but for 16-bit
operations, the data values can only be accessed from even addresses.
 For example, if a data word is located at address 0x0200, then the low byte of that data word is
located at address 0x0200, and the high byte of that word is located at address 0x0201.
 This is called as Little-endian ordering, in which the low-order byte is stored at lower memory
address and high-order byte is at the higher address. For example, if a word contains the
hexadecimal value 0x1234. Its less significant (low-order) byte is 0x34 and it is stored at lower
memory address 0x0200 and the most significant (high-order) byte 0x12 is store at higher
memory address 0x0201.

10. CPU ARCHITECTURE & REGISTERS OF MSP430
The central processing unit (CPU) executes the instructions stored in memory. It steps
through the instructions in the sequence in which they are stored in memory until it encounters a
branch or when an exception occurs (interrupt or reset).
The CPU can run at a maximum clock frequency fMCLK of 16MHz in the MSP430F2xx family
and some newer MSP430x4xx devices, and 8MHz in the others. It is built using static logic, which
means that there is no minimum frequency of operation: The CPU can be stopped and will retain
its state until it is restarted. This is essential for low-power operation to be straightforward.

The CPU features include:

 16-bit RISC architecture with 27 instructions and 7 addressing modes.
 Orthogonal architecture with every instruction usable with every addressing mode.
 Full register access including program counter, status registers, and stack pointer.
 Single-cycle registers operations
 Large 16-bit register file reduces fetches to memory.
 16-bit address bus allows direct access and branching throughout entire memory range.
 16-bit data bus allows direct manipulation of word-wide arguments.
 Constant generator provides six most used immediate values and reduces code size.
 Word and byte addressing and instruction formats.
 It can address the complete address range without paging
 It includes the arithmetic logic unit (ALU), which performs computation, a set of 16
registers designated R0–R15 and the logic needed to decode the instructions and
implement them.
Figure : CPU Registers of MSP430
MSP430 CPU registers
The CPU incorporates sixteen 16-bit registers:

 Four registers (R0, R1, R2 and R3) have dedicated functions;
 12 working registers (R4 to R15) for general use.
R0: Program Counter (PC) :

 The 16-bit Program Counter (PC/R0) points to the next instruction to be fetched from
memory and executed by the CPU.
 The Program counter is incremented by the number of bytes used by the instruction (2, 4,
or 6 bytes, always even).
 It is important to remember that the PC is aligned at even addresses, because the
instructions are composed of 1-3 words. Hence the LSB of PC is hard-wired to 0.
R1: Stack Pointer (SP)

 The stack memory is a memory block where the data is stored in LIFO manner.
 The Stack Pointer (SP/R1) holds the address of the stack-top.
 In the MSP430, as in many other processors, the stack is allocated at the top of the RAM
and grows down towards low addresses.
 The LSB of of the stack pointer is hardwired to 0 in the MSP430, which guarantees
that it always points to valid words. A byte is therefore wasted to preserve the
alignment to words if a single byte is placed on the stack.

Operation of the Stack :
The operation of the stack is illustrated in the following figure. The specific addresses are for
MSO430F2013 with 128 Bytes of RAM are from 0x0200 to 0x027F. Hence, Before the execution,
the initially the value of SP = 0x0280
The purpose of the stack :
 It used by subroutine calls to store the program counter value for return at the end of
subroutine (RET). When a subroutine is called, the CPU jumps to the subroutine, executes
the code there, then returns to the instruction after the call. It must therefore keep track of
the contents of the PC before jumping to the subroutine, so that it can return afterward.
This is the primary purpose of the stack.
 It is used by interrupt - system stores the actual PC value first, then the actual status
register content on top of the stack. After servicing the interrupt, the system get the same
status as just before the interrupt happened by executing the instruction return from
interrupt (RETI).
 It can be used by compiler for subroutine parameters
 It can be used by user to store data for later use (store by PUSH, retrieve by POP).

R2: Status Register (SR)
The Status Register (SR/R2) stores the status bits and control bits.
Status Flags: Indicate some condition produced by an instruction execution.

The system flags are changed automatically by the CPU depending on the result of
an operation.
C : Carry Flag : It is set to 1 , if a carry is generated in an Addition (or) borrow in Subtraction.
Z : Zero Flag : It is set to 1, if the result of an operation is ZERO.

A common application of Zero flag is to check whether two values are equal or not
N : Negative Flag : It is made equal to the MSB of the result.

It is used with signed numbers only.
N=1 for negative results and N =0 for positive results.
V: Signed overflow flag :

It is set to 1, when the result of a signed operation has overflowed, even though a
carry may not be generated.
For ex., the sum of 0x75 + 0x67 = 0xDC. There is no problem if the variables are
unsigned. But, if they are signed, the overflow flag will be set.
Enable Interrupts : Setting the general interrupt enable (GIE) bit enables maskable interrupts.
Clearing the bit disables all maskable interrupts.
There are also nonmaskable interrupts, which cannot be disabled with GIE.
Control of Low-Power Modes :
The CPUOFF, OSCOFF, SCG0, and SCG1 bits control the mode of operation of the MSP430MCU.
All systems are fully operational when all bits are clear. Setting combinations of these bits puts the
device into one of its low-power modes.
SCG1 (System clock generator 1) : When set, turns off the SMCLK.
SCG0 (System clock generator 0) : When set, turns off the DCO DC generator for DCO.
if DCO-CLK is not used for MCLK or SMCLK.
OSCOFF (Oscillator OFF ) : When set, turns off the VLO and LF XT1 crystal oscillator
if LFXT1-CLK is not used for MCLK or SMCLK.
CPUOFF : When set, turns off the MCLK, which stops the CPU.

R2/R3: Constant Generator Registers (CG1/CG2)
Depending of the source-register addressing modes (As) value, six commonly used
constants can be generated without a code word or code memory access to retrieve them.
This is a very powerful feature, which allows the implementation of emulated instructions,
for example, instead of implementing a core instruction for an increment, the constant
generator is used.
The registers R2 and R3 can be used to generate six different constants commonly used in
programming, without the need to add an extra 16-bit word of code to the instruction.
The constants below are chosen based on the bit (As) of the instruction that selects the
addressing mode.
Register Addressing mode Constant

R2 10 +4
R2 11 +8
R3 00 0
R3 01 +1
R3 10 +2
R3 11 -1 (FFFF)
The constant generator advantages are:

• No special instructions required
• No additional code word for the six constants
• No code memory access required to retrieve the constant
The assembler uses the constant generator automatically if one of the 6- constants is used
as an immediate source operand.
Registers R2 and R3, used in the constant mode, cannot be addressed explicitly; they act as
source-only registers.
Constant Generator - Expanded Instruction Set
The RISC instruction set of the MSP430 has only 27 instructions. However, the constant
generator allows the MSP430 assembler to support 24 additional, emulated instructions.
For example, the single-operand instruction
clr.w dst is replaced by : mov.w R3,dst

where the #0 is replaced by the assembler, and R3 is used with As = 00
inc.w dst is replaced by : add.w 0(R3), dst
R4 - R15: General–Purpose Registers :

These general-purpose registers are used to store data values, address pointers, or index values
and can be accessed with byte or word instructions.

11. ADDRESSING MODES :
 The method of specifying data to be operated by an instruction is called as addressing

mode. The different ways that a processor can access the data are referred to as addressing
mode.
 For MSP430, Seven addressing modes for the source operand and four addressing modes
for the destination operand can address the complete address space with no exceptions.
S.No. Addressing Mode Syntax Description As / Ad
1 Register mode Rn Register contents are operand 00 / 0
2 Indexed mode X(Rn) (Rn + X) points to the operand.

(PC + X) points to the operand.
Symbolic mode / X = Offset address =
3 LABLE
PC relative Address of LABLE - PC 01 / 1
Indexed mode X(PC) is used
The word following the instruction
contains the absolute address.
4 Absolute mode &ADDR
Indexed mode X(SR) is used,
where X= ADDR, SR =0.
Indirect register
5 @Rn Rn is used as a pointer to the operand. 10 / --
mode
Rn is used as a pointer to the operand.
Indirect
6 @Rn+ Rn is incremented afterwards by 1 for .B
autoincrement
instructions and by 2 for .W instructions. 11 / --
The word following the instruction
7 Immediate mode #N
contains the immediate constant N.
1. Register mode :
 In this addressing mode, the data is available in any one of the registers in the CPU.
 This is available for both source and destination
Ex: mov.w R5, R6 ; copies word from R5 to R6
2. Indexed mode :
 In this addressing mode, the address of data is the sum of constant base address and the
contents of a CPU register.
 This mode is available for both source and destination
Ex: mov.b 3(R5), R6 ; load byte from address (3+R5) into R6

If R5 = 0004 then, the content of memory address 0007 is moved to R6

3. Symbolic mode / PC Relative :
 In this addressing mode, PC is used as the base address. So the address of data is the sum
of PC and relative offset address of data.
 The assembler calculates the relative offset address of the data
Ex: mov.w LABLE, R6 ; load word LABLE into R6
The assembler replaces the above instruction by the indexed form
mov.w X(PC), R6 ; load word LABLE into R6
where X = relative offset = LABLE – PC
4. Absolute mode :
 In this addressing mode, the absolute address of the data is available in the instruction.
 This is already the complete address required, so that it should be added to a register that
contains ZERO. Hence, in indexed addressing, the Status Register is used as constant
generator (CG1) and it contains 0 when it is used as the base for indexed addressing.
 Absolute addressing is shown by the prefix “ & ”
Ex: mov.b &P1IN, R6 ; load byte from port address P1IN into R6
The assembler replaces the above instruction by the indexed form
mov.b P1IN(SR), R6 ; load byte from port address P1IN into R6
The above instruction moves the content of source address to the register R6
5. Indirect Register mode :
 In this addressing mode, the address of the data is available in the register.
 Indirect register addressing is shown by the symbol @ in front of a register such as @R5.
In other words, R5 is used as a pointer.
 This mode is available for only source operand.
Ex: mov.w @R5, R6 ; load word from address (R5) into R6
If R5 = 0004 then, the content of memory address 0004 is moved to R6

6. Indirect Auto-increment Register mode :
 In this addressing mode, the address of the data is available in the register.
 This addressing mode is shown by the symbol @ in front of a register with + sign after it
such as @R5+ . In other words, R5 is used as a pointer and it is automatically incremented
by 1 for BYTE operation and 2 by WORD operation.
Ex: mov.w @R5+, R6 ; load word from address (R5) into R6 and increment R5 by 2
If R5 = 0004 then, the content of memory address 0004 is moved to R6 and

the pointer R5 is incremented by 2.
7. Immediate mode :
 In this addressing mode, the data is available immediately after the instruction.
 The PC is automatically incremented after the instruction is fetched and therefore points to
the following word. Hence it is a special case of Indirect auto-increment register
addressing mode.
Ex: mov.b #45, R6 ; move the immediate constant into R6.
mov.b @PC+, R6 ;

12. INSTRUCTION FORMATS OF MSP430 :
 An instruction is a command given to the processor/controller to perform a given task on

specified data. Each instruction has 2- parts:
(a) The task to be performed – called as Operation code (Opcode)
(b) The data to be operated on – called as Operand.
Instruction
OPCODE OPERAND
 There are three core-instruction formats:
(i) Dual-operand
(ii) Single-operand
(iii) Jump
The source and destination of an instruction are defined by the following fields:
src : The source operand defined by As and S-reg
dst : The destination operand defined by Ad and D-reg
As : Addressing bits responsible for the addressing mode used for the source (src)
Ad : Addressing mode used for the destination (dst)
S-reg : The working register used for the source (src)
D-reg : The working register used for the destination (dst)
B/W : Byte or word operation:
0: word operation 1: byte operation
 All single-operand and dual-operand instructions can be byte or word instructions by using .B
or .W extensions. Byte instructions are used to access byte data (or) byte peripherals. Word
instructions are used to access word data (or) word peripherals. If no extension is used, the
instruction is a word instruction.

INSTRUCTION TIMINGS:
 The number of CPU clock cycles required for an instruction depends on the instruction format
and the addressing modes used - not the instruction itself.
 The number of clock cycles refers to the MCLK.
 The number of MCLK cycles required for most instructions is limited by access to memory.

The general principle for Format-I instructions (Two operands) is as follows :
(i) It takes one cycle to fetch the instruction word itself. This is all if both source and
destination are in CPU registers.
Ex: mov.w R5, R6
(ii) One more cycle is needed to fetch the source if it is given indirectly as @Rn or @Rn+,
in which case the address is already in the CPU. This includes immediate data.
Ex: mov.w @R5, R6
(iii) Alternatively, two more cycles are needed if one of the indexed modes is used. The
first is to fetch the base address, which is added to the value in a CPU register to get
the address of the source. A second cycle is necessary to fetch the operand itself. This
includes absolute and symbolic modes.
Ex: mov.w 25(R5), R6
(iv) Two more cycle are needed to fetch the destination in the same way, if it is indexed.
Ex: mov.w @R5, 25(R6)
(v) A final cycle is needed to write the destination back to memory if required; no
allowance is needed for a register in the CPU.
13. INSTRUCTION SET OF MSP430
 The complete MSP430 instruction set consists of 27 core instructions & 24 emulated
instructions.
 The core instructions are instructions that have unique op-codes decoded by the CPU.
 The emulated instructions are instructions that make code easier to write and read, but do not
have op-codes themselves; instead they are replaced automatically by the assembler with an
equivalent core instruction.
 For the emulated instructions, the operand is always a destination.
(i) Movement Instructions (Data Transfer)

(ii) Arithmetic and Logic Instructions
(iii) Shift and Rotate Instructions
(iv) Control Transfer instructions (Branch/Subroutine/Interrupt)

(i) Movement Instructions
Instruction Operation Example
Copies data from source to destination mov.w R5, R6

1 mov.w src, dst
dst  src R6  R5
Push data onto stack

push.w R5
( first the SP is decremented by 2 and the source
2 push.w src SP  SP-2
content is stored at stacktop)
@ SP  R5
@ --SP = src
Pop data from stack

push.w R6
( first the content of stacktop is moved to destination
3 pop.w dst R6  @ SP
and SP is incremented by 2)
SP  SP+2
dst = @SP + +
(ii) Arithmetic and Logic Instructions
(a) Binary Arithmetic Instructions with Two operands

Add the content of source to destination

1 add.w src, dst add.w R5, R6
dst  dst + src
Add with carry

2 addc.w src, dst addc.w R5, R6
dst  dst + (src + C)
Add carry bit to the destination

3 adc.w dst adc.w R6
dst  dst + C
Subtract the content of source from destination

4 sub.w src, dst sub.w R5, R6
dst  dst - src
Subtract with borrow

5 subc.w src, dst subc.w R5, R6
dst  dst –( src + C)
Subtract borrow bit from the destination

6 sbc.w dst sbc.w R6
dst  dst – C
Compares source and destination.

Performs ( dst – src), but Only flags are changed
7 cmp.w src,dst cmp.w R5,R6
If dst > src : C=0, Z=0
If dst < src : C=1, Z=0
If dst = src : C=0, Z=1

(b) Arithmetic Instructions with One operand :
All these instructions are emulated, which means that the operand is always a destination
Clear destination clr.w R6

1 clr.w dst
dst  0 R6  0
The content of destination is decremented by 1 dec.w R6

2 dec.w dst
dst  dst – 1 R6  R6 - 1
Double decrement
decd.w R6
3 decd.w dst The content of destination is decremented by 2
R6  R6 – 2
dst  dst – 2
The content of destination is inccremented by 1 inc.w R6

4 inc.w dst
dst  dst + 1 R6  R6 + 1
Double increment
incd.w R6
5 incd.w dst The content of destination is inccremented by 2
R6  R6 + 2
dst  dst + 2
Test ( compare with zero)

Performs ( dst – 0), but Only flags are changed
6 tst.w dst tsd.w R6
If dst > 0 : C=0, Z=0
If dst < 0 : C=1, Z=0
If dst = 0 : C=0, Z=1
(c) Decimal Arithmetic Instructions :
These instructions are used to perform BCD addition
Perfroms the decimal addtion of destination and

dadd.w R5, R6
1 dadd.w src, dst source with carry
R6  R6 + R5+C
dst  dst + src + C
Performs the decimal addition of destination and

dadc.w R6
2 dadc.w dst carry.
R6  R6 + C
dst  dst + C

(d) Logic Instructions with Two operands
Performs bit-wise logic AND operation

1 and.w src, dst and.w R5, R6
dst  dst AND src
Performs bit-wise logic Ex-OR operation

2 xor.w src, dst xor.w R5, R6
dst  dst XOR src
Performs bit-wise Test operation

3 bit.w src, dst It performs Logic AND operation, But Only bit.w R5, R6
flags are affected
Set bits in destination

The source operand and the destination operand
4 bis.w src, dst are logically ORed. The result is placed into the bis.w R5, R6
destination. The source operand is not affected.
dst  dst OR src
Clear bits in destination

The inverted source operand and the destination
operand are logically ANDed. The result is
5 bic.w src, dst bic.w R5, R6
placed into the destination. The source operand
is not affected
dst  dst AND ~src
(e) Logic Instructions with ONE operand

Invert destination
1 inv.w dst Performs bit-wise NOT operation (1’s complement) inv.w R6
dst  ~dst
(f) Byte manipulation

Swap upper and lower bytes
The high and the low byte of the operand are
1 swpb dst swpb R6
exchanged
dst.15:8 ↔ dst.7:0
Extend sign of lower byte
The sign of the low byte of the operand is extended
into the high byte
2 sxt dst sxt R6
dst. 15:8  dst.7
If dst.7 = 0: high byte = 00 H afterwards
If dst.7 = 1: high byte = FF H afterwards

(g) Operations on Bits in Status Register
These instructions are used to set orclear the falgs in Status Register. All these instructions
are emulated instructions.
Instruction Operation Flag affected
1 clrc Clear Carry bit C=0
2 clrn Clear Negative bit N=0
3 clrz Clear Zero bit Z=0
4 setc Set Carry bit C=1
5 setn Set Negative bit N=1
6 setz Set Zero bit Z=1
7 dint Disable General Interrupts GIE = 0
8 eint Enable General Interrupts GIE = 1
(iii) Shift and Rotate Instructions
Instruction Description Operation
rla dst Arithmetic shift Left
rra dst Arithmetic shift Right
Rotate Left through

rlc dst
Carry
Rotate Right through

rrc dst
Carry

(iii) Control Trasnfer Instructions
Instruction Description Operation
1 br src Branch ( go to) PC  src
SP  SP-2
2 call src Call Subroutine @ SP  PC
PC  src
PC  @ SP
3 ret Return from Subroutine
SP  SP+2
SR  @ SP
Return from Interrupt SP  SP+2
4 reti
PC  @ SP
SP  SP+2
No operation
5 nop
( consumes single cycle )
JUMP Instructions Condition
1 jmp label Unconditional Jump
2 jc / jlo label Jump if carry / Jump if lower Jump if C =1
3 jnc / jhs label Jump if not carry / Jump higher or same Jump if C =0
4 Jz / jeq label Jump if zero / Jump if equal Jump if Z =1
5 Jnz / jne label Jump if not zero / Jump if not equal Jump if Z =0
6 jn label Jumpif negative Jump if N =1
7 jge label Jump if greater or equal (signed values) Jump if (N xor V) =0
8 jl label Jump if less than (signed values) Jump if (N xor V) =1

14. SAMPLE EMBEDDED SYSTEM ON MSP 430 :
Note : Write about the introduction to MSP430
The letters MSP stand for mixed signal processor, which is a reminder that many practical
applications require analog inputs. There is a selection of analog-to-digital converters with a
resolution of up to 16 bits. An example of a system where this choice is important is the weighing
machine shown in above Figure. It includes the following functional blocks:
The sensor has four resistive elements arranged as a Wheatstone bridge. Ideally, this is
balanced when there is no load, giving V+ = V− . Two of the resistances increase and two
decrease when a weight is placed on the scale pan, driving the bridge out of balance.
A differential amplifier magnifies the difference in voltage between its input terminals,
giving Vout = A(V+ −V−), where A is the gain.
The analog output of the amplifier is converted to a binary value by A/D converter.
The microcontroller multiplies the input by an appropriate factor so that the display gives
the weight in grams or ounces and subtracts an offset so that the display reads zero when
no weight is present. It also reads the buttons and supervises the complete system.
There is a serial interface between the microcontroller and the liquid crystal display, which
has a built-in controller.
This system clearly needs a lot of components, including several integrated circuits. In
contrast, the whole system can be constructed from a sensor, an MSP430F42x, a simple LCD
without a controller, and a couple of decoupling capacitors. The MSP430x4xx family drives
segmented LCDs directly, which eliminates the need for a controller. Several devices contain
ADCs with high-resolution, differential inputs, which would work directly from the sensor
without the need for an amplifier. The microcontroller can also manage the power drawn by the
circuit so that the processor would be switched off when it was not needed and the whole system
shut down after a period of inactivity.

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IV B.Tech.

I Sem (R13) ECE : Embedded Systems : UNIT -1 1

1. Embedded Systems – Introduction (Definition, Applications and Classification) - 1

1. EMBEDDED SYSTEMS - INTRODUCTION

1.2 . Characteristics of Embedded System

1.3. Quality attributes of Embedded Systems

VISVODAYA TECHNICAL ACADEMY :: KAVALI

1.4. Application of Embedded Systems

Purpose of Embedded System

The different applications/Examples of Embedded systems are given below

1. Consumer Electronics: Camcorders, Cameras.

12. Missiles and Satellites : Defense, Aerospace, Communication, tracking system

VISVODAYA TECHNICAL ACADEMY :: KAVALI

1.5. General Purpose Computing System Vs Embedded System :

General Purpose Computing system Embedded system

It is combination of generic hardware and a It is combination of special purpose hardware

1.6. Classification of Embedded Systems

The classification of embedded system is based on following criteria's:

(a) Classification based on generation

VISVODAYA TECHNICAL ACADEMY :: KAVALI

(b) Classification based on Complexity and performance

(c) Classification based on deterministic behavior

 This classification is applicable for “Real Time” systems.

(d) Classification based on triggering

 Embedded systems which are “Reactive” in nature can be based on triggering.

VISVODAYA TECHNICAL ACADEMY :: KAVALI

2. ELEMENTS OF EMBEDDED SYSTEM :

Embedded systems are basically designed to regulate a physical variable (or) to

Actuators  connected at the output port

Figure .1 : Elements of an Embedded System

VISVODAYA TECHNICAL ACADEMY :: KAVALI

1. General purpose and Domain Specific Processors

Digital Signal Processors

VISVODAYA TECHNICAL ACADEMY :: KAVALI

Application Specific Integrated Circuit (ASIC)

 ASIC is a microchip designed to perform a specific or unique application.

CPLD and FPGA

 The PLDs consists of a large no. of programmable gates on a VLSI chip

Commercial off-the-shelf components (COTS)

 Commercial off-the-shelf (COTS) product is one which is used ‘as-is’

VISVODAYA TECHNICAL ACADEMY :: KAVALI

1 Supports lesser number of instructions. Supports greater number of instructions.

3 Single, fixed length instructions Variable length instructions

VISVODAYA TECHNICAL ACADEMY :: KAVALI

4. HARVARD ARCHITECTURE Vs VON-NEUMANN ARCHITECTURE :

Architectures used for processor design are Harvard or Von- Neumann.

Harvard architecture Von-Neumann architecture

It shares single common bus for instruction

Low performance as compared to Harvard

No additional logic is required because,

Comparatively high cost Low cost

VISVODAYA TECHNICAL ACADEMY :: KAVALI

5. MEMORY MAPPED I/O & I/O MAPPED I/O :

Memory mapped I/O Port mapped I/O

Less no. of instructions are for I/O access.

The data transfer takes place between

VISVODAYA TECHNICAL ACADEMY :: KAVALI

5. LITTLE-ENDIAN & BIG-ENDIAN PROCESSORS

Base address 2000 H

Base address+1 2001H

Base address+2 2002 H

Base address+3 2003 H

Base address 2000 H

Base address+1 2001 H