International conference on Communication and Signal Processing, April 3-5, 2013, India
Hardware Implementation of Truncated
Multiplier Based on Multiplexer Using FPGA
Yogesh M. Motey, Tejaswini G. Panse
 obtain the final result. Although there are many algorithms for
Abstract— The paper is about the implementation of PCT
multiplier whose design is based on multiplexer using Field
Programmable Gate Array (FPGA). Multiplier is such an
important element f r om t he poi nt of power consumption and
area occupied in the system. Multiplication using truncated
scheme provides an efficient method for reducing the power and
area as compared to that of full width multipliers. There are
many schemes for truncation in multiplier among them an
adaptive pseudo-carry compensation truncation (PCT) scheme
gives result with low error. This scheme is suitable to array
multiplier designed using multiplexer based technique. The
comparative result between the two multipliers in this paper,
PCT multiplier occupies just about 34% more area with
approximately 38% less power consumption and with low error
probability. The designed PCT multiplier is power efficient and
faster than the compared one in terms of propagation delay. The
future scope is it can be used for image compression by
implementation on Field Programmable Gate Array (FPGA).
Index Terms— Digital multiplier, PCT truncated multiplier,
Computer arithmetic, FPGA, VLSI Design.
I. INTRODUCTION
A N eminence multiplier is always being a need of
electronics industry for applications in DSP, image
processing. A truncated multiplier is a p × p multiplier with p
bits output. In a truncated multiplier the p less significant bits
of the full-width product are discarded to compensate it some
of the partial products are removed and replaced by a suit- able
compensation function, to trade-off accuracy with hardware
cost. A system’s performance is generally depending on the
performance of the multiplier because the multiplier operation
is time consuming which makes it slowest clement in the
system. Moreover, it is generally the large area consuming.
That's why; optimizing both the speed and area of the
multiplier is a key design issue. Conversely, area and speed are
usually conflicting constraints so that improving one result in
affecting other. Most algorithms involve a shift and an add
technique where the multiplicand is conditionally added to
Yogesh M. Motey, Yashvantrao Chavan College of Engineering, Nagpur,
INDIA (e-mail: yogesh.motey@gmail.com).
Tejaswini G. Panse, Yashvantrao Chavan College of Engineering, Nagpur,
INDIA (e-mail: tejaswini.deshmukh@gmail.com).
978-1-4673-1622-4/12/$31.00 ©2013 IEEE
accomplishing this, there is no reduction in the height of
partial products that need to be summed to produce the final
result. The problem of more area and power consumption with
fast operation can be overcome using truncation schemes for
multiplier. Truncated multiplication is significantly reducing
the power over standard parallel multiplier for different
operand sizes, is shown in different research papers. Many
truncation schemes are proposed for array multipliers, few of
them are Constant Correction Truncated (CCT) [12], Variable
Correction Truncated (VCT) [9], and a pseudo-carry
compensation truncation (PCT) scheme [1]. In constant
correction truncation (CCT) the correction constant is fixed for
specific values of n and k regardless of the value of the
multiplicand and multiplier. A non-zero DC component of the
resulting product is incurred by this fixed correction constant.
A non-zero dc component is added based on specific values of
n and k to Columns (n-1) to (k-1) of the pp matrix. To adapt
the correction to the input values, a variable correction
truncation (VCT) scheme was proposed. A data-dependent
variable correction truncation scheme (VCT) is proposed
where the most significant pp bits from the (n-k-1)th column
are stacked over the (n-k)th column and a constant bias of ‘C’
is added in Columns (n-1) to (n-k). The PCT technique takes
account of correction to the input values and caries generated
in each stage. In this paper pseudo-carry compensation
truncation (PCT) scheme is used and architecture of a
multiplier is designed in verilog HDL language using
structural modeling and simulated on Xilinx and finally
Implemented on FPGA Spartan 3 kit.
II. TRUNCATED MULTIPLIERS
Most existing schemes target both array and tree multipliers.
The design of high-speed, area-efficient multipliers is essential
for VLSI implementations of digital signal processing systems.
Use of truncations schemes gives significant reduction in
complexities of design. Truncation is best suited where exact
result is not always required and a rounded product is used for
further computation.
401

Fig. 1. RTL view of Truncated Multiplier.
A. Truncated Multiplier
The truncated multiplier is an array multiplier. The
architecture consists of AND gates and two types of fixed
input multiplexers. One is with inputs 0, 0, 0, Ci, where Ci is
carry bit input of multiplexer which will take care of carry
generated in the previous column in architecture or from inputs
by ANDing them and other with 0, xi, yi, si where xi,yi are the
input bits of 8 bit numbers and si is the sum bit taking
summation result coming from the previous column of
multiplexer. The figure 1 shows The RTL view for Truncated
multiplexer matrix multiplier for an 8*8-bit multiplier; n=8
most significant columns and k=2 additional columns of
multiplexers. This view is obtained in Xilinx 9.1 gives idea
about the basic building blocks in the design.
B. A Pseudo-Carry Compensation Truncation (PCT)
Multiplier
A novel truncation scheme for the multiplexer based array
multiplier was propose in [7]. A brief antecedent of this work
was presented in [13]. The proposed method achieves lower
average and spread of errors by means of adaptive pseudo
carry compensation and a simple deterministic constant bias
that is independent of k [1]. By exploiting the symmetry of the
multiplexer-based array multiplier, the pp bits generated by the
multiplexers in our truncated multiplier can be accumulated in
a carry-save format to further reduce the area and improve the
speed over other truncated array multipliers [1].
1) NEW TRUNCATED MULTIPLICATION SCHEME
The product of two n-bit positive integers X=xn−1 , xn−2 ,….
, x1 , x0 And Y= yn−1 , yn−2 ,…. , y1 , y0 is a 2n-bit product
P=XY. The numbers are assumed to be fractional in their error
analysis and the inputs and output are scaled by a factor of 2−n
and 2−2n , respectively [1].
P= {Xn−1 + 2n−1 xn−1}{Yn−1 + 2n−1 yn−1} (1)
402
n 1 n 1
P ¦ (x i ˜ yi )22i  ¦ M i 2i
i 0 i 1 (2)
Where Mi = Xi * yi + xi * Yi , Mi can be implemented
as a multiplexer With xi and yi as select signals. Mi = 0, Xi, Yi
and Xi + Yi when xi , yi = 00 ", “01”, “10” and “11”,
respectively. Without loss of generality, our proposed
truncated scheme can be explained with the help of a truncated
multiplexer matrix of Fig. 1 with n = 8 and k = 2, where k is
the number of partial product (pp) columns to be kept beyond
the width, n of the truncated product. Using VCT scheme, the
multiplexers from Column 5 (i.e., n−k−1) will be stacked on
Column 6 (i.e., n−k). However, the product bit in Column 6 is
dependent on the carry’s generated from Column 5 into
Column 6 rather than the sum of its pp bits. Directly stacking
the pp bits of Column 5 onto Column 6 can also create
excessive error due to the carry. Propagated into Column 7
(i.e., n−k+1). From the definition of Mi , if both xi and yi are
1’s, then the sum of Xi and Yi is selected. If the select signals
of all the multiplexers in Column 5 are 1’s, then the sums of
the multiplexer inputs, i.e. s0 , s1, and s2, are selected. In the
worst case, the carry signals, c0 = x0 * y0, c1 = x1 * y1 and c2 =
x2 * y2 are obtained. Our idea is to add the carry signals
generated from the inputs to the multiplexers in the (n−k−1)th
column to the (n−k)th column. The error is reduced as only the
necessary carry’s from the (n−k−1)th column are added to the
(n−k)th column. The error is still present, though, because of
the assumption that all select signals of the multiplexers in the
(n−k−1)th are “1”. This approach is, however, closer to the
carry propagation in full-width multiplier as opposed to VCT.
To minimize the truncation error for an unsigned integer
multiplication, a new pseudo-carry compensated truncation
(PCT) scheme consisting of an adaptive compensation circuit
and a fixed bias is proposed. Finally, the n-bit truncated
product, Pt , with its least significant bit weighted 20 , is given
by
n 1 r 1 n 1
P ¦M
i r
i 2i  n  ¦ r 1
M ti 2r  n  ¦ r 1
( xi ˜ yi )22i n
i [ ] i [ ]
2 2
r 1
 ¦ ( xi ˜ yi )2r  n  21
i 0 (3)
In this architecture the building blocks are again
multiplexers but they are designed by combining full adders
and half adders with 4-to-1 multiplexer gives FMUX and
HMUX. Therefore HMUX are placed at the boundary and
FMUX at the interior of the array. A Fixed correction bias of 1
is used as input to the leftmost HMUX in array for adaptive
compensation of error. The ripple carry adders (RCA) are used
at the bottom of the array to add the outputs of FMUX and to
get the final product bit, for MSB instead of RCA logical
ORing block is used. The figure 2 shows RTL view of a PCT
Truncated multiplexer matrix multiplier for an 8*8-bit
multiplier; it is again an array multiplier.
 Particularly, the Spartan-3AN is used as a target technology in
this paper. Spartan-3AN combines all the feature of Spartan-
3A FPGA family plus leading technology in-system flash
memory for configuration and nonvolatile data storage [15].
The programming is done by using Verilog HDL language
using a structural modeling in place of behavioral or data flow
modeling to get a known structure or size of design which is
not possible with other two modeling’s. Each building block
i.e. gates and different multiplexers are designed and using
port mapping or entity called in programming.

IV. RESULTS
Simulations are performed on Xilinx 9.1 for spartan 3
FPGA kit. The number slices occupied by Truncated
Fig. 2. RTL view of PCT Truncated Multiplier Multiplier is 38 and by PCT Truncated Multiplier is 51 which
is relatively just about 34% more area than Truncated
Multiplier shown in Table I with approximately 38% less
III. FIELD PROGRAMMABLE GATE ARRAY (FPGA) power consumption with respect to area consumed. The power
The Spartan-3 FPGA belongs to the fifth generation Xilinx is calculated at the constant ambient temperature of 25C and
family. It is specifically designed to meet the needs of high the constant values of dc load current, load capacitance and
different voltages as shown in Table II.
volume, low unit cost electronic systems. The family consists
of eight member offering densities ranging from 50,000 to five
million system gates. The Spartan-3 FPGA consists of five Available Truncated PCT
fundamental programmable functional elements: CLBs, IOBs,
Block RAMs, dedicated multipliers (18×18) and digital clock
managers (DCMs), Spartan-3 family includes Spartan- 3L, No.of 3584 38 51
Spartan-3E, Spartan-3A, Spartan-3A DSP, Spartan-3AN and Slices
the extended Spartan-3A FPGAs [15]. occupied

% Area 100% 1% 1%

Table I: Area Comparison

Idc=10mA Load Vccint = Vccaux Vcco=

cap.= 2.50V = 2.50V
1000fF 3.30V

Truncated PCT

Power 360 346

(mW)

Table II: Power Consumption

There is no propagation delay in PCT multiplier which is

present in truncated multiplier.
For Truncated Multiplier
1. Minimum input arrival time before clock: 3.578ns
2. Maximum output required time after clock: 6.141ns
3. Maximum combinational path delay: No path found
For PCT Multiplier
1. Minimum input arrival time before clock: No path
found.
2. Maximum output required time after clock: No path
Fig. 3. FPGA KIT found

403
 3. Maximum combinational path delay: 25.157ns

V. CONCLUSION
A conclusion from the results obtained is that PCT
Truncated Multiplier is occupying more area but its power
consumption is better than Truncated Multiplier with less
delay in terms of a propagation delay. The future work on this
is to implement this multiplier for the application of image
compression using microcontroller coding for controlling and
data or image transfer in or from FPGA.

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