W83304D/W83304G

Winbond
ACPI Controller
W83304D
W83304G
TM
For AMD Claw Hammer CPU

Publication Release Date: April, 2006

-1- Revision 0.51
 W83304D/W83304G

W83304D
Data Sheet Revision History

VERSION
PAGES DATES VERSION MAIN CONTENTS
ON WEB

1 June/04 0.50 N/A Preliminary Version

2 April/06 0.51 N/A Add Pb-free part no of W83304G

Please note that all data and specifications are subject to change without notice. All the
trademarks of products and companies mentioned in this data sheet belong to their respective
owners.

LIFE SUPPORT APPLICATIONS

These products are not designed for use in life support appliances, devices, or systems where
malfunction of these products can reasonably be expected to result in personal injury. Winbond
customers using or selling these products for use in such applications do so at their own risk and
agree to fully indemnify Winbond for any damages resulting from such improper use or sales.

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 W83304D/W83304G

Table of Content-

1. GENERAL FUNCTION DESCRIPTION...................................................................................... 4

2. PIN-OUT...................................................................................................................................... 5
3. PIN DESCRIPTIONS .................................................................................................................. 6
4. BLOCK DIAGRAM ...................................................................................................................... 9
5. ELECTRICAL SPECIFICATION ............................................................................................... 10
5.1 AC CHARACTERISTICS.............................................................................................. 10
6. APPLICATION CIRCUIT........................................................................................................... 12
7. POWER SEQUENCE ............................................................................................................... 13
8. ORDERING INSTRUCTION ..................................................................................................... 14
9. HOW TO READ THE TOP MARKING...................................................................................... 14
10. PACKAGE DIMENSION ........................................................................................................... 15

Publication Release Date: April, 2006

-3- Revision 0.51
 W83304D/W83304G

1. GENERAL FUNCTION DESCRIPTION

y Provides Powers
- 5V Active/Sleep (5VDL)
- Provide a switch 5VDLEN pin to enable/disable 5VDL output in S5 state for USB application.
- 3.3V Active/Sleep (3.3VDUAL)
- Dual-Channel 2.5V Active/Sleep (2.5VSTR) for DDR
- 1.5V for AGP 4X/8X Voltage
- Two 1.25V~5V Linear Voltage Regulators Support VCC/VSTR/VDL/VSB Voltages
- 1.25V DDR Bus Termination Regulated Voltage
- 1.2V VLDT for AMD_K8 CPU Hyper transport.
- 2.5VDDA for AMD_K8 PLL.
- 1.25VREF for AMD_K8 reference.
- Up to 0.3V/0.1V incremental voltage on DDR RAM for over-clocking application.
y Provides Signals for ATX Power Supply PS_ON# Control
y Support AMD K8 Claw Hammer Specific Power Up/Down Sequence
y Provides fault signal control.
y Internal Charge Pump Support Up to 9.5VSB
y Drive All N-Channel MOSFET
y Soft Start
y Under-Voltage Monitoring for VAGP, VRAM, VLDT, 3.3VDUAL Channels

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 W83304D/W83304G

2. PIN-OUT

5VDRV/3VDRV

3VSB_DRV

VAGP_DRV
3VSB_SEN

VAGP_SEN

VLDT_DRV

VLDT_SEN
LR1_DRV

LR2_DRV
LR1_SEN

LR2_SEN

5VSB
36 35 34 33 32 31 30 29 28 27 26 25

5VUSB_DRV 37 24 GND
C1 38 23 VDDIO_DRV1
C2 39 22 ISEN1
CHR_PMP 40 21 VDDIO_DRV2
5VSB 41 20 ISEN2
GND 42 19 VDDIO_SEN
RSMRST# 43 W83304D 18 VTT_DRV
5VDL_EN 44 17 VTT_SEN
MISC_EN 45 16 VTT_SINK
PWR_OK 46 15 ISET
S3# 47 SS
14
S5# 48 1.25VREF
13

1 2 3 4 5 6 7 8 9 10 11 12
VDDIO_SET0

VDDIO_SET1

PS_ON_OUT#

VDD_EN

GND
VCC3
Fault#

2.5VDDA
ALL_PWR_OK

OV_CLK#

PS_ON_IN#

VDD_GD

Publication Release Date: April, 2006

-5- Revision 0.51
 W83304D/W83304G

3. PIN DESCRIPTIONS
I/O12t - TTL level bi-directional pin with 12 mA source-sink capability,open drain output
I/O12ts - TTL level and schmitt trigger
O12 - Output pin with 12 mA source-sink capability
AO12 - Output pin(Analog) with 12mA capability
OD12 - Open-drain output pin with 12 mA sink capability
INt - TTL level input pin
INts - TTL level input pin and schmitt trigger
AIN - Input pin(Analog)

POWER
NO NAME I/O FUNCTION DESCRIPTION
SOURCE
Power OK Signal. The signal is drove high to indicate all
1 ALL_PWR_OK OD24 5VSB
power ready.
H/W Trapping Pin for Over-Clocking Application.
1: Normal
2 OV_CLK# I 5VSB
0: +50mV is added on All regulated powers (VDDIO, VDDA,
VAGP, VLDT, 1.25VREF ).
VDDIO Output Voltage Setting Pin.
VDDIO output with OV_CLK# = High
VDDIO_SET1 VDDIO_SET0
3 VDDIO_SET0 Its 5VSB 2.5V 0 0
2.6V 0 1
2.7V 1 0
2.8V 1 1
VDDIO output with OV_CLK# = Low
VRAMSET1 VRAMSET0

4 VDDIO_SET1 Its 5VSB 2.55V 0 0

2.65V 0 1
2.75V 1 0
2.85V 1 1
System Fault Input Signal.
5 Fault# Its Pull the pin low when any critical event alerted; the chip
will shut the system down when the signal pulled low.

6 PS_ON_IN# Its ATX PS_ON# Signal Input.

The PS_ON# signal of ATX power supply is routed through
7 PS_ON_OUT# OD12 the chip for power fault control.

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 W83304D/W83304G

Pin Descriptions, continued

POWER
NO NAME I/O FUNCTION DESCRIPTION
SOURCE
CPU Power Good Signal.
8 VDD_GD I 5VSB
The signal is inputted for power sequence control.
Signal Output to Enable CPU Power.
9 VDD_EN OD24 5VSB
The signal output to enable CPU power for sequence control.
10 VCC3 P Power VCC.
11 2.5VDDA AO200mA VCC3 2.5V Power for CPU PLL Core.
12 GND P Power Ground.
13 1.25VREF AO5mA 3VSB 1.25V Reference Voltage.
Soft-Start Pin.
14 SS AI/AO 5VSB A capacitor (0.1u) is attached in this pin for soft-start slope
rate adjustment.
Reference Current Input.
15 ISET AI/AO 5VSB
An input current for internal circuit reference.
16 VTT_SINK AO 5VSB
Power VTT.
17 VTT_SEN AI 5VSB A bi-direction linear regulator is provided to regulate voltage
for DDR bus terminator.
18 VTT_DRV AO 9VSB
19 VDDIO_SEN AI
20 ISEN2 AI Power VDDIO.
21 VDDIO_DRV2 AO 9VSB A dual-channels linear regulator with current balancing
architecture is provided for higher current DDR SDRAM
22 ISEN1 AI application.
23 VDDIO_DRV1 AO
24 GND P Power Ground.
25 VLDT_SEN AI 5VSB Power VLDT.
26 VLDT_DRV AO 9VSB 1.2V power for LDT bus.

27 5VSB P Standby Power Pin.

28 LR2_SEN AI 5VSB Linear Regulator 1.
A general purpose linear regulator is provided to generate
29 LR2_DRV AO 9VSB 1.2V~5.0V power for specific device.
30 LR1_SEN AI 5VSB Linear Regulator 2.
A general purpose linear regulator is provided to generate
31 LR1_DRV AO 9VSB 1.2V~5.0V power for specific device.

Publication Release Date: April, 2006

-7- Revision 0.51
 W83304D/W83304G

Pin Descriptions, continued

POWER
NO NAME I/O FUNCTION DESCRIPTION
SOURCE
32 VAGP_SEN AI 5VSB Power for AGP Core.
33 VAGP_DRV AO 9VSB 1.5V power is regulated for AGP core.

34 3VSB_DRV AO 9VSB
Power 3.3VDL.
35 3VSB_SEN AI 5VSB A linear regulator and switch is combined to generate 3V
dual power.
36 5VDRV/3VDRV AO 9VSB
36 5VDRV/3VDRV AO 9VSB Power for USB Device.
A 5V switch power is provided for USB device and can be
37 5VUSB_DRV AO 9VSB programmed for various USB application with configuration
of pin 44.
38 C1 I 5VSB
Charge Pump Pins.
39 C2 I 5VSB It supports achieve 10mA driving current and insures
output voltage 9.5V or above.
40 CHR_PMP P 5VSB
41 5VSB P Standby Power Pin.
42 GND Power Ground.
Signal to Indicate Status of Standby Power.
43 RSMRST# OD12 The signal will be pulled high to indicate the standby power
stable.
5VUSB Power Type Setting Pin.
5VUSB_EN=Low, support power for USB device in S0, S3
44 5VDL_EN I 5VSB state.
5VUSB_EN =High, support power for USB device in S0, S3,
S5 state.
45 MISC_EN OD24 5VSB Signal to Enable Miscellaneous Power.
46 PWR_OK Its 5VSB Power OK Signal form ATX Power Supply.
47 S3# I
ACPI Control Signals.
48 S5# I

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 W83304D/W83304G

4. BLOCK DIAGRAM

ALL_PWR_OK

PS_ON_OUT#
PS_ON_IN#
VDDIO_SET0
VDDIO_SET1
PWR_OK#

RSMRST#

5VUSB_EN
MISC_EN
OV_CLK

VDD_GD
VDD_EN

Fault#
S3#
S5#

CHR_PMP 3VDRV
C1 Charge 3.3VDL 3.3VSB_DRV
C2 Pump 3.3VSB_SEN
VTT_DRV
1.25VTT VTT_SEN
VLDT_DRV 1.2VLDT VTT SINK
VLDT_SEN
Control Logic 1.25VREF 1.25VREF
SS Soft
Start
5VDRV
5VUSB 5VSB_DRV
5VUSB_EN
ISET Ref.
Current
VDDIO_DRV1
2.5VRAM ISEN1
VDDIO_SEN
VAGP_DRV Linear Linear VDDIO_DRV2
1.5VAGP 2.5VDDA
VAGP_SEN Regulator Regulator ISEN2
VDDA_DRV
LR1_DRV

LR2_DRV
LR1_SEN

LR2_SEN

Publication Release Date: April, 2006

-9- Revision 0.51
 W83304D/W83304G

5. ELECTRICAL SPECIFICATION
5.1 AC CHARACTERISTICS
Vcc=5V ± 5 %, TA = 0°C to +70°C
PARAMETER SYMBOL MIN TYP MAX UNITS TEST CONDITIONS
VAGP Linear Regulator
Nominal Output Voltage 1.5 V OVA#=1
Nominal Output Voltage 1.55 V OVA#=0
Regulation 5 %
Under-Voltage Falling
86.67 %
Threshold
1.25VREF
Nominal Output Voltage 1.25 Iload < 5mA; OVA#=1
Nominal Output Voltage 1.3 Iload < 5mA; OVA#=0
1.2VLDT Linear Regulator
Nominal Output Voltage 1.2 V OVA#=1
Nominal Output Voltage 1.25 V OVA#=0
Regulation 5 %
Under-Voltage Falling
87.5 %
Threshold
VDDIO Regulator
VRAMSET0 VDDIO VOLTAGE SETTING OVA#=1
VRAMSET1 VRAMSET0
2.5V 0 0
2.6V 0 1
2.7V 1 0
2.8V 1 1
VRAMSET1 VDDIO VOLTAGE SETTING OVA#=0
VRAMSET1 VRAMSET0
2.55V 0 0
2.65V 0 1
2.75V 1 0
2.85V 1 1
Under-Voltage Falling
84 %
Threshold
Regulation 5 %

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 W83304D/W83304G

AC CHARACTERISTICS, continued

Vcc=5V ± 5 %, TA = 0°C to +70°C

PARAMETER SYMBOL MIN TYP MAX UNITS TEST CONDITIONS
2.5VDDA
Iload < 200mA;
Nominal Output Voltage 2.5
OVA#=1
Iload < 200mA;
Nominal Output Voltage 2.55
OVA#=0
Bus Terminator
Regulate a 1.25V for
Nominal Output Voltage / DDR bus termination
50 %
V(VRAM2.5_SEN) Half of VDDIO
voltage
Nominal Output Voltage 1.25 V
5VDUAL Switch Controller
5VDRV Output High
9 Cap Loading
Voltage
5VSBDRV Output High
9 Cap Loading
Voltage
5VUSB SS Sourcing
2.5 uA @ Soft-start
Current
3.3VDual
Under-Voltage Falling
78.79 %
Threshold
5VDRV Output High
9 V
Voltage
3VSBDRV 3.3 Regulation
Charge Pump
Charge Pump Frequency 180 KHz
Charge Pump Voltage 9.5
Two linear regulator
Nominal Output Voltage Linear regulator from1.2V~5V

Publication Release Date: April, 2006

- 11 - Revision 0.51
 W83304D/W83304G

6. APPLICATION CIRCUIT
5VSB VCC3 DUAL/VSB/STR/VCC DUAL/VSB/STR/VCC

3
C1 VLR1=1.2/R3*(R1+R3)
C2 Q1 100U Q2 C3 Q3 C4
1000U 1 1 47U 1 47U VLR2=1.2/R4*(R2+R4)
VCC3
VAGP
2

3
VLR1 VLR2

2
1 C5 C6 R1 R R2 R
1000U Q5 1500U
Q4 1 R3 C7 R4 C8
C C
R R
3VDUAL
3

3VDUAL
C9 VCC3
1500U W5VSB

3
C10
1000U
Q6

3
1
VCC5 5VSB
Q7 Q8
2

C11 1 1
36
35
34
33
32
31
30
29
28
27
26
25

2
U1 1.2VLDT VDDIO_DRV1 VDDIO_DRV2
1
100U Q10 C12
5VSB

Q9 1 2000U
LR1_SEN
LR2_SEN

C13
LR1_DRV
LR2_DRV
3VSB_SEN

VAGP_SEN
3VSB_DRV
VAGP_DRV

VLDT_SEN
VLDT_DRV

2
5VDRV/3VDRV

C14 R5 4m R6 4m
0.1U ISEN1 ISEN2
2200p
37 24
3

38 5VUSB_DRV GND 23
C1 VDDIO_DRV1 VDDIO_DRV1 VDDIO
5VUSB 39 22
C16 40 C2 ISEN1 21 ISEN1 C17 R7 4.7K
1500U C15 0.1U 41 CHR_PMP VDDIO_DRV2 20 VDDIO_DRV2 3000U 5VSB
W5VSB 5VSB ISEN2 ISEN2 VDDIO_SET0
42 W83304D 19 R8 4.7K
GND VDDIO_SEN VDDIO_SET1 5VSB
43 18
RSMRST#(to SB) RSMRST# VTT_DRV

3
44 17 VDDIO_SET1 VDDIO_SET0 VDDIO
5VDL_EN 5VDL_EN VTT_SEN 0 0 2.5V
45 16 R9 R10
MISC_EN MISC_EN VTT_SINK 0 1 2.6V
46 15 Q11 4.7K 4.7K
PWR_OK(from ATX) PWR_OK ISET (OPT) (OPT) 1 0 2.7V
47 14 1
S3# S3# SS 1 1 2.8V
C18 48 13
ALL_PWR_OK

PS_ON_OUT#

S5#
VDDIO_SET0
VDDIO_SET1

R11 4.7K S5# 1.25VREF 1.25VREF(S0,S3) C19

PS_ON_IN#

5VSB
OV_CLK#

0.1U R12
VDD_GD

2.5VDDA
VDD_EN

2
R13 4.7K 0.1U 100K VTT
Fault#

VCC3

5VSB
GND

3
C20 R14
1500U OV_CLK# 5VSB
C21 4.7K
Q12
0.1U
10
11
12

1 R15 OV_CLK#
1
2
3
4
5
6
7
8
9

4.7K 0 2.5VDDA,VDDIO,VLDT,AGP,1.25VREF ADD

C22 C23 (OPT) 5OmV
ALL_PWR_OK 1 Normal
1n 1n

2
OV_CLK#
VDDIO_SET0 (OPT) (OPT)
VDDIO_SET1
Fault#
R16
PS_ON_IN#(connect to MB) 2.5VDDA 5VDL_EN 5VSB
4.7K
PS_ON_OUT#(to ATX)
C24 R17 5
VDD_GD CAP 5VDL_EN 5VUSB
C25 R18
VDD_EN 1U 5VSB W5VSB 0 STR
4.7K
R19 4.7K (OPT) 1 DUAL
VCC3
C26 C27
R20 4.7K VCC3
5VSB 1U 1U
R21 4.7K
5VSB
R22 4.7K
5VSB
R23 4.7K
VCC3

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 W83304D/W83304G

7. POWER SEQUENCE

4.3
W83304D power sequence(RUN_MISC default) 3.7
5VSB
82mS

RSMRST#

PSIN#

S3#

S5#

PSOUT#

VCC

AGP

2.5VDDA

PWROK

RUN_MISC

V TT &V RAM &

1.25VREF

V CORE _EN

V CORE _PG

1.2VLDT

1.2VLDT_PG

ALLPWR_OK

Note:
1. When at power up sequence, the delay time between adjacent power planes is 5ms after the
previous power plane is power-good.
2. When at power down sequence, the delay time between adjacent power planes is 20ms
after the previous power plane is power-down.
3. After 1.2VLDT_PG=H and delay 20ms, the ALLPWR_OK will be High(ALLPWR_OK=H).

4. All “LUV” detect is enabled after the power plane have power-good.

Publication Release Date: April, 2006

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 W83304D/W83304G

8. ORDERING INSTRUCTION
PART NO. PACKAGE REMARKS
W83304D 48-pin LQFP
W83304G 48-pin LQFP Pb-free package

9. HOW TO READ THE TOP MARKING

inbond
W83304D
214658302
310GBRA

inbond
W83304G
214658302
310GBRA
1st Line: Winbond Logo
2nd Line: Part_No W83304D, W83304G (Pb-free package)
3rd Line: lot no
4th Line: tracking code 310GBRA
310：date code,310 means package was made in ’03 week 10
G：Assembly ID, G means GR, A means ASE…etc.
B：Chip Version, A means version A, B means version B
RA：Winbond internal use

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 W83304D/W83304G

10. PACKAGE DIMENSION

HD
D A
A2 A1
36 25

37 24

HE E

48 13

1 e b 12

c
SEATING PLANE

Y L θ
L1

Controlling dimension : Millimeters

Dimension in inch Dimension in mm

Symbol
Min Nom Max Min Nom Max
A
A1 0.002 0.004 0.006 0.05 0.10 0.15
A2 0.053 0.055 0.057 1.35 1.40 1.45

b 0.006 0.008 0.010 0.15 0.20 0.25

c 0.004 0.006 0.008 0.10 0.15 0.20

D 0.272 0.276 0.280 6.90 7.00 7.10

E 0.272 0.276 0.280 6.90 7.00 7.10

e 0.014 0.020 0.026 0.35 0.50 0.65
HD 0.350 0.354 0.358 8.90 9.00 9.10
HE 0.350 0.354 0.358 8.90 9.00 9.10
L 0.018 0.024 0.030 0.45 0.60 0.75

L1 0.039 1.00
Y 0.004 0.10
0 0 7 0 7

Publication Release Date: April, 2006

- 15 - Revision 0.51
 W83304D/W83304G

Please note that all data and specifications are subject to change without notice. All the
trademarks of products and companies mentioned in this data sheet belong to their respective
owners.

Important Notice
Winbond products are not designed, intended, authorized or warranted for use as components
in systems or equipment intended for surgical implantation, atomic energy control instruments,
airplane or spaceship instruments, transportation instruments, traffic signal instruments,
combustion control instruments, or for other applications intended to support or sustain life.
Further more, Winbond products are not intended for applications wherein failure of Winbond
products could result or lead to a situation wherein personal injury, death or severe property
or environmental damage could occur.
Winbond customers using or selling these products for use in such applications do so at their
own risk and agree to fully indemnify Winbond for any damages resulting from such improper
use or sales.

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