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IEEE 802.3bp 1000BASE-T1 PHY Task Force 16 March 2015
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Draft Amendment to IEEE Std 802.3-2012 IEEE Draft P802.3bp/D1.4
IEEE 802.3bp 1000BASE-T1 PHY Task Force 16 March 2015
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31 Figure 97–1—Relationship of 1000BASE-T1 PHY
32 to the ISO/IEC OSI reference model and the IEEE 802.3 CSMA/CD LAN Model
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35 MDI = MEDIUM DEPENDENT INTERFACE
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37 GMII = GIGABIT MEDIA INDEPENDENT INTERFACE
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39 AUTONEG = AUTO-NEGOTIATION
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41 PCS = PHYSICAL CODING SUBLAYER
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43 PMA = PHYSICAL MEDIUM ATTACHMENT
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45 PHY = PHYSICAL LAYER DEVICE
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47 PMD = PHYSICAL MEDIUM DEPENDENT
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51 * GMII is optional
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53 ** AUTONEG is optional
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Draft Amendment to IEEE Std 802.3-2012 IEEE Draft P802.3bp/D1.4
IEEE 802.3bp 1000BASE-T1 PHY Task Force 16 March 2015
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Draft Amendment to IEEE Std 802.3-2012 IEEE Draft P802.3bp/D1.4
IEEE 802.3bp 1000BASE-T1 PHY Task Force 16 March 2015
In Data Mode, the PCS Transmit function data path starts with the GMII interface, where TXD, TX_EN, and 1
TX_ER input data to the PCS every 8 ns (as clocked by GTX_CLK). Data and control from ten GTX_CLK 2
cycles are encoded into an 81 bit “81B block” that encodes every possible combination of data and control 3
(control signals include error propagation, assert low power idle, and inter-frame signaling). Each set of 4
forty-five 81B blocks along with 9 bits of OAM data (see 97.7) processed by a Reed Solomon FEC encoder 5
(RS FEC). The RS encoder adds 396 bits of FEC data and the 4050 bits (forty-five 81B blocks = 3645 bits, 6
9 bits of OAM, and 396 bits of FEC data) are scrambled using a 15-bit side-stream scrambler. Each 3 bits of 7
the scrambled data is converted to 2 ternary PAM3 symbols by the 3B2T mapper (the 4050 bits in the RS 8
frame become 2700 PAM3 symbols) and passed to the PMA. PCS transmit functions are described in 9
97.3.2.2. 10
11
In Data Mode, the PCS Receive function data path operates in the opposite order as the transmit path. The 12
incoming PAM3 symbols are synchronized to frame boundaries. Within each frame, each two PAM3 sym- 13
bols are de-mapped to 3 bits by the 3B2T demapper (the 2700 PAM3 symbols are converted to 4050 bits). 14
The data is then descrambled and passed to the RS FEC decoder for data validation and correction. Finally, 15
each of the forty-five 81B blocks is decoded into GMII data or control. PCS data mode receive is described 16
in 97.3.2.3. 17
18
In Training Mode (see 97.4.2.5), the PCS transmits and receives data sequences to synchronize the RS FEC 19
blocks, learn the Data Mode scrambler seed, and exchange EEE and OAM capabilities. The training mode 20
uses PAM2 encoding. 21
22
97.1.2.2 Physical Medium Attachment (PMA) sublayer 23
24
The 1000BASE-T1 PMA transmits/receives symbol streams to/from the PCS onto the single balanced 25
twisted pair and provides the clock recovery, link monitor and the 1000BASE-T1 PHY Control function. 26
The PMA provides full duplex communications at 750 MBd. 27
28
The PMA PHY Control function generates signals that control the PCS and PMA sublayer operations. PHY 29
Control is enabled following the completion of Auto-Negotiation or PHY Link Synchronization and pro- 30
vides the start-up functions required for successful 1000BASE-T1 operation. It determines whether the PHY 31
operates in a disabled state, a training state, or a data state where MAC frames can be exchanged between 32
the link partners. 33
34
The Link Monitor determines the status of the underlying link channel and communicates this status to other 35
functional blocks. A failure of the receive channel causes data mode operation to stop and Auto-Negotiation 36
or Link Synchronization to restart. 37
38
97.1.2.3 Physical Medium Dependent (PMD) sublayer 39
40
The1000BASE-T1 PMD (see 97.5) defines the transmit and receive electrical characteristics. The PMD also 41
specifies the minimum link segment characteristics, EMC requirements, and test modes. 42
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Draft Amendment to IEEE Std 802.3-2012 IEEE Draft P802.3bp/D1.4
IEEE 802.3bp 1000BASE-T1 PHY Task Force 16 March 2015
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Technology Dependent Interface (Clause 97.6 and 2
3
PMA_Link.indication
4
PMA_Link.request
(link_control)
5
(link_status)
PMA_UNITDATA.request
(tx_symb) 6
tx_lpi_active
7
GTX_CLK PCS 8
TRANSMIT 9
TXD<7:0>
10
11
tx_mode
TX_EN 12
TX_ER
13
14
PHY
config CONTROL 15
16
17
18
19
20
LINK
MONITOR 21
22
23
PMA 24
link_status
TRANSMIT 25
26
27
recovered_clock
28
MDI +
MDI - 29
30
RX_CLK
31
RXD<7:0> 32
PCS
rx_lpi_active
33
RX_DV RECEIVE
rem_rcvr_status
PMA
34
RX_ER loc_rcvr_status
RECEIVE 35
pcs_status / scr_status
PMA_UNITDATA.indication
36
(rx_symb) 37
38
received_clock
39
40
CLOCK 41
GIGABIT MEDIA MEDIUM
INDEPENDENT
PMA SERVICE RECOVERY
DEPENDENT
42
INTERFACE
INTERFACE INTERFACE 43
(GMII) (MDI)
44
PCS PMA 45
PHY 46
(INCLUDES PCS AND PMA)
47
48
NOTE—The recovered_clock arc is shown to indicate delivery of the received clock signal back the PMA TRANSMIT for loop timing
49
NOTE—Signals and functions shown with dashed lines are optional. 50
Figure 97–2—Functional block diagram 51
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Draft Amendment to IEEE Std 802.3-2012 IEEE Draft P802.3bp/D1.4
IEEE 802.3bp 1000BASE-T1 PHY Task Force 16 March 2015
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Draft Amendment to IEEE Std 802.3-2012 IEEE Draft P802.3bp/D1.4
IEEE 802.3bp 1000BASE-T1 PHY Task Force 16 March 2015
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Draft Amendment to IEEE Std 802.3-2012 IEEE Draft P802.3bp/D1.4
IEEE 802.3bp 1000BASE-T1 PHY Task Force 16 March 2015
PMA_LINK.request (link_control) 1
2
PMA_LINK.indication (link_status) 3
4
97.2.1.1 PMA_LINK.request 5
6
This primitive allows the Auto-Negotiation or the PHY Link Synchronization algorithm to enable and 7
disable operation of the PMA, as specified in 98.4.2 or 97.6, respectively. 8
9
97.2.1.1.1 Semantics of the primitive 10
11
PMA_LINK.request (link_control) 12
13
The link_control parameter can take on one of two values: DISABLE, or ENABLE. 14
15
DISABLE Used by the Auto-Negotiation or PHY Link Synchronization process to 16
disable the PHY. 17
ENABLE Used by the Auto-Negotiation or PHY Link Synchronization process to 18
enable the PHY. 19
20
97.2.1.1.2 When generated 21
22
Auto-Negotiation or PHY Link Synchronization generates this primitive to indicate a change in link_control 23
as described in 97.6 or Clause 98. 24
25
97.2.1.1.3 Effect of receipt 26
27
This primitive affects the operation of the PMA Link Monitor function as defined in 97.4.2.6 and the PMA 28
PHY Control function as defined in 97.4.2.5. 29
30
97.2.1.2 PMA_LINK.indication 31
32
This primitive is generated by the PMA to indicate the status of the underlying medium as specified in 33
98.4.1. This primitive informs the PCS, PMA PHY Control function, and the Auto-Negotiation or PHY Link 34
Synchronization process about the status of the underlying link. 35
36
97.2.1.2.1 Semantics of the primitive 37
38
PMA_LINK.indication (link_status) 39
40
The link_status parameter can take on one of two values: FAIL or OK. 41
42
FAIL No valid link established. 43
44
OK The Link Monitor function indicates that a valid 1000BASE-T1 link is established. 45
Reliable reception of signals transmitted from the remote PHY is possible. 46
47
97.2.1.2.2 When generated 48
49
The PMA generates this primitive to indicate a change in link_status in compliance with the state diagram 50
given in Figure 97–21. 51
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Draft Amendment to IEEE Std 802.3-2012 IEEE Draft P802.3bp/D1.4
IEEE 802.3bp 1000BASE-T1 PHY Task Force 16 March 2015
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Draft Amendment to IEEE Std 802.3-2012 IEEE Draft P802.3bp/D1.4
IEEE 802.3bp 1000BASE-T1 PHY Task Force 16 March 2015
PMA_LINK.indication
MDC 8
PMA_LINK.request
MANAGEMENT 9
MDIO
10
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GTX_CLK PMA_TXMODE.indication 12
TXD<7:0> 13
PMA_CONFIG.indication
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TX_EN 15
PMA_UNITDATA.indication
TX_ER 16
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PMA_UNITDATA.request 18
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PMA_RXSTATUS.indication
PCS PMA 20
PMA_REMRXSTATUS.request 21
RX_CLK
MDI + 22
MDI -
RXD<7:0> PMA_SCRSTATUS.request 23
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RX_DV PMA_RESET.indication
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RX_ER PMA_PCSSTATUS.request(pcs_status) 26
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PMA_PCS_RX_LPI_STATUS.request 28
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PMA_PCS_TX_LPI_STATUS.request 30
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GIGABIT MEDIA PMA SERVICE MEDIUM
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INDEPENDENT INTERFACE DEPENDENT 37
INTERFACE INTERFACE
(GMII) (MDI) 38
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PHY 40
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NOTE—Service interface primitives shown with dashed lines are optional.
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Figure 97–3—1000BASE-T service interfaces 45
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97.2.2.2 PMA_CONFIG.indication 47
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Each PHY in a 1000BASE-T1 link is capable of operating as a MASTER PHY and as a SLAVE PHY. If the 49
Auto-Negotiation process is enabled, PMA_CONFIG MASTER-SLAVE configuration is determined during 50
Auto-Negotiation (Clause 98) and the result is provided to the PMA. If the Auto-Negotiation process is not 51
enabled, PMA_CONFIG MASTER-SLAVE configuration is pre-determined to be Master or Slave via man- 52
agement control during initialization or via default hardware set-up. 53
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Draft Amendment to IEEE Std 802.3-2012 IEEE Draft P802.3bp/D1.4
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Draft Amendment to IEEE Std 802.3-2012 IEEE Draft P802.3bp/D1.4
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During reception the PMA_UNITDATA.indication conveys to the PCS via the parameter rx_symb the value 1
of symbols detected on the MDI during each cycle of the recovered clock. 2
3
97.2.2.4.2 When generated 4
5
The PMA generates PMA_UNITDATA.indication (rx_symb) messages synchronously for every symbol 6
received at the MDI. The nominal rate of the PMA_UNITDATA.indication primitive is 750 MHz, as 7
governed by the recovered clock. 8
9
97.2.2.4.3 Effect of receipt 10
11
The effect of receipt of this primitive is unspecified. 12
13
97.2.2.5 PMA_SCRSTATUS.request 14
15
This primitive is generated by PCS Receive to communicate the status of the descrambler for the local PHY. 16
The parameter scr_status conveys to the PMA Receive function the information that the training mode 17
descrambler has achieved synchronization. 18
19
97.2.2.5.1 Semantics of the primitive 20
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PMA_SCRSTATUS.request (scr_status) 22
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The scr_status parameter can take on one of two values of the form: 24
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OK The training mode descrambler has achieved synchronization. 26
NOT_OK The training mode descrambler is not synchronized. 27
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97.2.2.5.2 When generated 29
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PCS Receive generates PMA_SCRSTATUS.request messages to indicate a change in scr_status. 31
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97.2.2.5.3 Effect of receipt 33
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The effect of receipt of this primitive is specified in 97.4.2.4 and 97.4.2.5. 35
36
97.2.2.6 PMA_PCSSTATUS.request 37
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This primitive is generated by PCS Receive to indicate the fully operational state of the PCS for the local 39
PHY. The parameter pcs_status conveys to the PMA Receive function the information that the PCS is 40
operating reliably in data mode. 41
42
97.2.2.6.1 Semantics of the primitive 43
44
PMA_PCSSTATUS.request (pcs_status) 45
46
The pcs_status parameter can take on one of two values of the form: 47
48
OK The PCS is operating reliably in data mode. 49
NOT_OK The PCS is not operating reliably in data mode. 50
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97.2.2.6.2 When generated 52
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PCS Receive generates PMA_PCSSTATUS.request messages to indicate a change in pcs_status. 54
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Draft Amendment to IEEE Std 802.3-2012 IEEE Draft P802.3bp/D1.4
IEEE 802.3bp 1000BASE-T1 PHY Task Force 16 March 2015
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Draft Amendment to IEEE Std 802.3-2012 IEEE Draft P802.3bp/D1.4
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97.2.2.9 PMA_REMRXSTATUS.request 3
4
This primitive is generated by PCS Receive to indicate the status of the receive link at the remote PHY as 5
communicated by the remote PHY via its encoding of its loc_rcvr_status parameter. The parameter 6
rem_rcvr_status conveys to the PMA PHY Control function the information on whether reliable operation of 7
the remote PHY is detected or not. The parameter rem_rcvr_status is set to the value received in the 8
loc_rcvr_status bit in the InfoField from the remote PHY. The rem_rcvr_status is set to NOT_OK if the PCS 9
has not decoded a valid InfoField from the remote PHY. 10
11
97.2.2.9.1 Semantics of the primitive 12
13
PMA_REMRXSTATUS.request (rem_rcvr_status) 14
15
The rem_rcvr_status parameter can take on one of two values of the form: 16
17
OK The receive link for the remote PHY is operating reliably. 18
NOT_OK Reliable operation of the receive link for the remote PHY is not detected. 19
20
97.2.2.9.2 When generated 21
22
The PCS generates PMA_REMRXSTATUS.request messages to indicate a change in rem_rcvr_status based 23
on the PCS decoding the loc_rcvs_status bit in InfoField messages received from the remote PHY during 24
training. 25
26
97.2.2.9.3 Effect of receipt 27
28
The effect of receipt of this primitive is specified in Figure 97–22. 29
30
31
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97.2.2.10 PMA_REMDATAREADY.request 33
34
This primitive is generated by PCS Receive to indicate whether the remote PHY is ready or not ready to 35
receive data. Its value is received from the link partner by the PCS as defined in Table 97-1. 36
37
97.2.2.10.1 Semantics of the primitive 38
39
PMA_REMDATAREADY.request (rem_data_ready) 40
41
The rem_data_ready parameter can take on one of two values of the form: 42
43
OK The remote PHY is ready to receive data. 44
NOT_OK The remote PHY is not ready to receive data. 45
46
97.2.2.10.2 When generated 47
48
The PCS generates PMA_REMDATAREADY.request messages to indicate a change in rem_data_ready 49
based on the PCS decoding the control words in Table 97-1 received from the remote PHY. 50
51
97.2.2.10.3 Effect of receipt 52
53
The effect of receipt of this primitive is specified in Figure 97–22. 54
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IEEE 802.3bp 1000BASE-T1 PHY Task Force 16 March 2015
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97.2.2.11 PMA_RESET.indication 3
4
This primitive is used to pass the PMA Reset function to the PCS (pcs_reset=ON) when reset is enabled. 5
6
The PMA_RESET.indication primitive can take on one of two values: 7
8
TRUE Reset is enabled. 9
FALSE Reset is not enabled. 10
11
97.2.2.11.1 When generated 12
13
The PMA Reset function is executed as described in 97.4.2.1. 14
15
97.2.2.11.2 Effect of receipt 16
17
The effect of receipt of this primitive is specified in 97.4.2.1. 18
19
97.2.2.12 PMA_PCS_RX_LPI_STATUS.request 20
21
When the PHY supports the EEE capability this primitive is generated by the PCS receive function to indi- 22
cate the status of the receive link at the local PHY. The parameter PMA_PCS_RX_LPI_STATUS.request 23
conveys to the PCS transmit and PMA receive functions information regarding whether the receive function 24
is in the LPI receive mode. 25
26
97.2.2.12.1 Semantics of the primitive 27
28
PMA_PCS_RX_LPI_STATUS.request (rx_lpi_active) 29
30
The rx_lpi_active parameter can take on one of two values of the form: 31
32
TRUE The receive function is in the LPI receive mode. 33
FALSE The receive function is not in the LPI receive mode. 34
35
97.2.2.12.2 When generated 36
37
The PCS generates PMA_PCS_RX_LPI_STATUS.request messages to indicate a change in the rx_lpi_ac- 38
tive variable as described in 97.3.2.3 and 97.3.6.2.2. 39
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97.2.2.12.3 Effect of receipt 41
42
The effect of receipt of this primitive is specified in 97.3.6.4. 43
44
97.2.2.13 PMA_PCS_TX_LPI_STATUS.request 45
46
When the PHY supports the EEE capability this primitive is generated by the PCS transmit function to indi- 47
cate the status of the transmit link at the local PHY. The parameter PMA_PCS_TX_LPI_STATUS.request 48
conveys to the PCS transmit and PMA receive functions information regarding whether the transmit func- 49
tion is in the LPI transmit mode. 50
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97.2.2.13.1 Semantics of the primitive 52
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PMA_PCS_TX_LPI_STATUS.request (tx_lpi_active) 54
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IEEE 802.3bp 1000BASE-T1 PHY Task Force 16 March 2015
The tx_lpi_active parameter can take on one of two values of the form: 1
2
TRUE The transmit function is in the LPI transmit mode. 3
FALSE The transmit function is not in the LPI transmit mode. 4
5
97.2.2.13.2 When generated 6
7
The PCS generates PMA_PCS_TX_LPI_STATUS.request messages to indicate a change in the tx_lpi_ac- 8
tive variable as described in 97.3.5 and 97.3.6.2.2. 9
10
97.2.2.13.3 Effect of receipt 11
12
The effect of receipt of this primitive is specified in 97.3.6.4. 13
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97.3 Physical Coding Sublayer (PCS) 16
Editor’s Note: Text written in italics are not approved baseline and are included only for placeholder information. The text will be
17
change to match approved baseline when selected. 18
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97.3.1 PCS service interface (GMII) 20
21
The PCS service interface allows the 1000BASE-T1 PCS to transfer information to and from a PCS client. 22
The PCS Interface is precisely defined as the Gigabit Media Independent Interface (GMII) in Clause 35. 23
24
97.3.2 PCS functions 25
26
The PCS comprises one PCS Reset function and two simultaneous and asynchronous operating functions. 27
The PCS operating functions are: PCS Transmit and PCS Receive. All operating functions start immediately 28
after the successful completion of the PCS Reset function. 29
30
The PCS reference diagram, Figure 97–4, shows how the two operating functions relate to the messages of 31
the PCS-PMA interface. Connections from the management interface (signals MDC and MDIO) to other 32
layers are pervasive and are not shown in Figure 97–4. 33
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Draft Amendment to IEEE Std 802.3-2012 IEEE Draft P802.3bp/D1.4
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Figure 97–4—PCS reference diagram 24
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97.3.2.1 PCS Reset function 27
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PCS Reset initializes all PCS functions. The PCS Reset function shall be executed whenever one of the fol- 29
lowing conditions occur: 30
31
a) Power on. 32
b) The receipt of a request for reset from the management entity. 33
34
PCS Reset sets pcs_reset=ON while any of the above reset conditions hold true (see 97.3.6.2.2). All state 35
diagrams take the open-ended pcs_reset branch upon execution of PCS Reset. The reference diagrams do 36
not explicitly show the PCS Reset function. 37
38
97.3.2.2 PCS Transmit function 39
40
The PCS Transmit function shall conform to the PCS 80B/81B Transmit state diagram in Figure 97–14 and 41
the PCS Transmit bit ordering in Figure 97–5 and Figure 97–7. 42
43
When communicating with the GMII, the PCS uses an octet-wide, synchronous data path, with packet 44
delimiting being provided by transmit control signals and receive control signals. Alignment to 80B/81B 45
blocks is performed in the PCS. The PMA sublayer operates independently of block and packet boundaries. 46
The PCS provides the functions necessary to map packets between the GMII format and the PMA service 47
interface format. 48
49
When the transmit channel is in data mode, the PCS Transmit process continuously generates 81B blocks 50
based upon the TXD <7:0>, TX_EN and TX_ER signals on the GMII. The subsequent functions of the PCS 51
Transmit process then pack the resulting blocks plus one OAM symbol, both of which are then processed by 52
a Reed-Solomon (RS) encoder and subsequently 3B2T mapped into a transmit RS frame of PAM3 symbols. 53
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Transmit data-units are sent to the PMA service interface via the PMA_UNITDATA.request primitive. A 1
symbol period, T, is 4/3 ns. 2
3
If a PMA_TXMODE.indication message has the value SEND_T, PCS Transmit generates sequences of 4
codes defined in 97.3.4.2 to the PMA via the PMA_UNITDATA.request primitive. These codes are used for 5
training mode and only transmit the values {–1, +1}. 6
7
During training mode an InfoField is transmitted at regular intervals containing messages for startup 8
operation. By this mechanism, a PHY indicates the status of its own receiver to the link partner. (See 9
97.4.2.5.) 10
11
In the data mode of operation, the PMA_TXMODE.indication message has the value SEND_N, and the 12
PCS Transmit function uses an 81B-RS coding technique to generate at each symbol period code-groups 13
that represent data or control. During transmission, 45 81B blocks shall be aggregated, encoded by a RS 14
frame encoder, and then scrambled by a PCS scrambler. During data encoding PCS Transmit frames shall be 15
encoded into a sequence of PAM3 symbols and transferred to the PMA. 16
17
Dashed rectangles in Figure 97–14 indicate states and state transitions in the transmit process state diagram 18
that shall be supported by PHYs with the EEE capability. PHYs without the EEE capability do not support 19
these transitions. 20
21
After reaching the data mode of operation, EEE-capable PHYs may enter the LPI transmit mode under the 22
control of the MAC via the GMII. The EEE Transmit state diagram is contained within the PCS Transmit 23
function. The EEE capability is described in 97.3.2.2.16. 24
25
97.3.2.2.1 Use of blocks 26
27
The PCS maps GMII signals into 81-bit blocks inserted into an RS frame, and vice versa, using an 81B-RS 28
coding scheme. The PAM2 PMA training frame synchronization allows establishment of RS frame and 81B 29
boundaries by the PCS Synchronization process. Blocks and frames are unobservable and have no meaning 30
outside the PCS. The PCS functions ENCODE and DECODE generate, manipulate, and interpret blocks and 31
frames as provided by the rules in 97.3.2.2.2. 32
33
97.3.2.2.2 81B-RS transmission code 34
35
The PCS uses a transmission code to improve the transmission characteristics of information to be 36
transferred across the link and to support transmission of control and data characters. The encoding defined 37
by the transmission code ensures that sufficient information is present in the PHY bit stream to make clock 38
recovery possible at the receiver. The encoding also preserves the likelihood of detecting any RS frame 39
errors that may occur during transmission and reception of information. In addition, the code enables the 40
receiver to achieve PCS synchronization alignment on the incoming PHY bit stream. 41
42
The relationship of block bit positions to GMII, PMA, and other PCS constructs is illustrated in Figure 97–5 43
for transmit and Figure 97–6 for receive. These figures illustrate the processing of a multiplicity of blocks 44
containing 10 data octets. See 97.3.2.2.5 for information on how blocks containing control characters are 45
mapped. 46
47
97.3.2.2.3 Notation conventions 48
49
For values shown as binary, the leftmost bit is the first transmitted bit. 50
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80B/81B encodes 10 data octets or control characters into an 81B block. 52
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Figure 97–5—PCS Transmit bit ordering 31
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97.3.2.2.4 Transmission order 34
35
The PCS Transmit bit ordering shall conform to Figure 97–5 and Figure 97–7. Note that these figures show 36
the mapping from GMII to 80B/81B block for a block containing ten data characters. The LSB of the OAM 37
symbol is transmitted first. 38
39
97.3.2.2.5 Block structure 40
41
Blocks consist of 81 bits. The first bit of a block is the data/ctrl header. Blocks are either data blocks or con- 42
trol blocks. The data/ctrl header is 0 for data blocks and 1 for control blocks. The remainder of the block 43
contains the payload. 44
45
Data blocks contain ten data octets. Control blocks begin with a 5-bit pointer field that indicates the location 46
of the first control code within the block. Bit 0 to 3 of pointer points to next octet that is a control symbol. 47
Bit 4 of pointer indicates whether the next control symbol is the final control symbol of the block: 0 = final, 48
1 = more control symbols. If the first octet in the block is a control character, the pointer field is followed by 49
a 3-bit control code. Otherwise the pointer field is followed by one or more data octets until the position of 50
the first control code. Then the 3-bit control code indicates type of control character. The control code is fol- 51
lowed by a 5-bit pointer field to the next control character if the prior pointer field value was greater than 15 52
( i.e. bit 4 = 1). The pointer field may be followed by a data octet or control code depending on the value of 53
54
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2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
Figure 97–6—PCS Receive bit ordering 36
37
the pointer field. In this way any combination of ten data octets and control characters may be encapsulated 38
within an 81B block. 39
40
41
42
43
44
45
46
47
48
49
50
51
52
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2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
Figure 97–7—PCS detailed transmit bit ordering 25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
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48
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The 81B block encoding is defined by the following equations where N = 10. 1
2
N = number of GMII octets encoded into block 3
octets numbered n = 0, 1, 2, …, N-1. octet 0 is the first one presented on GMII. 4
TC[n] = 0 if octet n is data octet on GMII, 1 if octet n is control octet on GMII 5
TC[-1] = 1 by definition 6
TD[n][0:7] = GMII octet n TXD[0:7] if TC[n] = 0 7
TD[n][5:7] = 000 or 010 – IPG, 101 – LPI, 001 – TX Error if TC[n] = 1. TD[n][0:4] is undefined. 8
B[0:8N] is the 8N+1 block. Bit 0 transmitted first. 9
OR(n) = Bitwise OR of TC[n:N-1] 10
NEXT(n)[0:3] = bit position of lowest bit in TC[n:N-1] that is a 1. Bit 3 is MSB. 11
NEXT(n)[4] = 0 if Bitwise SUM of TC[n:N-1] = 1, else 1 12
13
B[0] = OR(0) 14
15
B[8n+1:8n+4] = TD[n][0:3] – if OR(n) = 0 16
NEXT(n)[0:3] – if OR(n) = 1 AND TC[n-1] = 1 17
TD[n-1][3:6] – if OR(n) = 1 AND TC[n-1] = 0 18
19
B[8n+5] = TD[n][4] – if OR(n) = 0 20
NEXT(n)[4] – if OR(n) = 1 AND TC[n-1] = 1 21
TD[n-1][7] – if OR(n) = 1 AND TC[n-1] = 0 22
23
B[8n+6:8n+8] = TD[n][5:7] – if OR(n) = 0 24
TD[n][5:7] – if OR(n) = 1 AND TC[n] = 1 25
TD[n][0:2] – if OR(n) = 1 AND TC[n] = 0 26
27
97.3.2.2.6 Control codes 28
29
A subset of control characters defined at the GMII are supported by the 1000BASE-T1 PCS. When TX_ER 30
and TX_EN are both asserted, the 1000BASE-T1 PCS conveys an Error symbol in the 80B81B block code. 31
When TX_EN is not asserted and no other supported control code is present at the GMII, the 1000BASE-T1 32
PCS will convey and Idle symbol in the 80B81B block code. 33
34
The control characters and their mappings to 1000BASE-T1 control code and GMII control code are speci- 35
fied in Table 97–1. All GMII and 1000BASE-T1 control code values that do not appear in the table shall not 36
be transmitted and shall be treated as an error if received. 37
38
39
Table 97–1—GMII Control Code Mapping 40
41
Control Code[0:2] GMII Transmit GMII Receive 42
000 Normal Inter-Frame with Normal Inter-Frame with 43
loc_data_ready=NOT_OK rem_- 44
data_ready=NOT_OK 45
001 Transmit Error Data Reception Error 46
Propagation 47
010 Normal Inter-Frame with Normal Inter-Frame with 48
loc_data_ready=OK rem_data_ready=OK 49
101 Assert Low Power Idle Assert Low Power Idle 50
51
other Reserved Reserved
52
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The Carrier Extend and Carrier Extend Error, and Reserved transactions, if any occurred, are assigned to the 1
Control Code<0:2> of 010, Normal inter-frame, in the PCS 80B/81B Encoder. 2
3
97.3.2.2.7 Valid and invalid blocks 4
5
A block is invalid if any of the following conditions exists: 6
7
a) The block contains an invalid pointer. 8
b) Any control character contains a value not in Table 97–1. 9
c) The RS frame containing this 80B/81B block is uncorrectable. 10
11
97.3.2.2.8 Idle 12
13
Idle (Normal Inter-frame) control characters are transmitted when TX_EN is not asserted and no other sup- 14
ported control code is present at the GMII. Idle characters may be added or deleted by the PCS to adapt 15
between clock rates. 16
17
97.3.2.2.9 LP_IDLE 18
19
The low power idle control characters (LP_IDLEs) are transmitted when TX_EN is not asserted, TX_ER is 20
asserted, and TXD<7:0> = 0x1. A continuous stream of LPI control characters is used to maintain a link in 21
the LPI transmit mode. Idle control characters are used to transition from the LPI transmit mode to the nor- 22
mal mode. EEE compliant PHYs respond to the Assert Low Power Idle condition on the GMII using the 23
procedure outlined in 97.1.2.4. 24
25
If EEE is not supported, then LP_IDLE shall be converted to IDLE. 26
27
97.3.2.2.10 Error 28
29
The Error control code is sent when TX_ER and TX_EN are both asserted. It is also sent when invalid 30
blocks are received. Error allows physical sublayers such as the PCS to propagate received errors. 31
32
97.3.2.2.11 Transmit process 33
34
The transmit process generates blocks based upon the TXD<7:0>, TX_EN and TX_ER signals received 35
from the GMII. Ten GMII data transfers are encoded into each block. It takes 2700 PMA_UNITDATA 36
transfers to send an RS frame of data. Where the GMII and PMA sublayer data rates are not synchronized to 37
that ratio, the transmit process needs to insert idles, or delete idles to adapt between the rates. 38
39
The transmit process generates blocks as specified in the transmit process state diagram. The contents of 40
each block are contained in a vector tx_coded<80:0>, which is aggregated with 45 81B blocks and OAM, 41
then passed to the Reed Solomon FEC Encoder and then finally passed to the scrambler. tx_coded<0> 42
contains the data/ctrl header and the remainder of the bits contain the block payload. 43
44
97.3.2.2.12 RS encoder 45
46
The 1000BASE-T1 PCS shall encode the transmitted data stream using Reed-Solomon code (450,406). The 47
RS encoder shall follow the notation described in 97.3.2.2.3 where the LSB is the first bit into the RS 48
encoder and the first transmitted bit. 49
50
The FEC code used for 1000BASE-T1 links is a shortened Reed-Solomon (450,406) code over the Galois 51
Field of GF(29)—a code operating on 9 bit symbols, as shown in Figure 97–8. The code encodes 406 infor- 52
mation symbols and adds 44 parity symbols. The code is systematic, meaning that the information symbols 53
are not disturbed in any way in the encoder and the parity symbols are added separately to each block. 54
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2
3
4
5
6
Figure 97–9—PCS to FEC bit mapping 7
8
9
97.3.2.2.13 PCS scrambler 10
11
The PCS Transmit function employs side-stream scrambling. The scrambler for the MASTER shall produce 12
the same result as the implementation shown in Figure 97–10. This implements the scrambler polynomial:1 13
14
4 15 15
G x = 1 + x + x (97–3) 16
17
The scrambler for the SLAVE shall produce the same result as the implementation shown in Figure 97–10. 18
This implements the scrambler polynomial: 19
20
G x = 1 + x + x
11 15
(97–4) 21
22
The initial seed values for the MASTER and SLAVE scramblers are left to the implementor. The seed values 23
shall be non-zero and shall be transmitted during the InfoField exchange. (See 97.4.2.5.5). The scrambler is 24
run continuously on all RS frame output bits. 25
26
27
28
PCS scrambler employed by the MASTER 29
30
31
32
33
34
PCS scrambler employed by the SLAVE 35
36
37
38
39
40
Figure 97–10—MASTER and SLAVE PCS scramblers 41
42
43
97.3.2.2.14 3B2T to PAM3 44
45
The 3B2T mapper generates 2700 PAM3 symbols per RS frame that are sent to the PMA via PMA_UNIT- 46
DATA.request. Every 9-bit symbol is divided into three 3-bit groups with the LSB bits as the first group. 47
Each 3-bit group is then mapped by the 3B2T into 2 PAM3 symbols. The mapping of 3B2T to PAM3 is 48
illustrated in Table 97–2. B[0] is the LSB and T[0] is the first PAM3 symbol transmitted. 49
50
51
1The convention here, which considers the most recent bit into the scrambler to be the lowest order term, is consistent with most refer-
52
ences and with other scramblers shown in this standard. Some references consider the most recent bit into the scrambler to be the high-
est order term and would therefore identify this as the inverse of the polynomial in Equation (97–3). In case of doubt, note that the 53
conformance requirement is based on the representation of the scrambler in the figure rather than the polynomial equation. 54
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Due to the wake signal constrained to occur at the beginning of every second RS frame boundary the PHY 1
wake time may range from 3.6 s to 10.8 s (lpi_wake_timer=Tw_phy as defined by Clause 78). 2
3
97.3.2.3 PCS Receive function 4
5
The PCS Receive function shall conform to the PCS 80B/81B receive state diagram in Figure 97–15 and the 6
PCS Receive bit ordering in Figure 97–6 including compliance with the associated state variables as speci- 7
fied in 97.3.6. 8
9
The PCS Receive function accepts received code-groups provided by the PMA Receive function via the 10
parameter rx_symb. The PCS receiver uses knowledge of the PMA training alignment to correctly align the 11
81B-RS frames. The received 81B-RS frames are decoded with error correction; the framing is checked; and 12
the 80B/81B ordered sets are converted to 10 data octets to obtain the signals RXD<7:0>, RX_DV and 13
RX_ER for transmission to the GMII. 14
15
During PMA training mode, PCS Receive checks the received PAM2 framing and signals the reliable acqui- 16
sition of the descrambler state by setting the parameter scr_status to OK. 17
18
When the PCS Synchronization process has obtained synchronization, the RS frame error rate (RFER) mon- 19
itor process monitors the signal quality asserting hi_rfer if excessive RS frame errors are detected (RS parity 20
error). If 40 consecutive RS frame errors are detected, the block_lock flag is de-asserted. When block_lock 21
is asserted and hi_rfer is de-asserted, the PCS Receive process continuously accepts blocks. The PCS 22
Receive process monitors these blocks and generates RXD<7:0>, RX_DV and RX_ER for transmission to 23
the GMII. 24
25
When the receive channel is in training mode, the PCS Synchronization process continuously monitors 26
PMA_RXSTATUS.indication (loc_rcvr_status). When loc_rcvr_status indicates OK, then the PCS Synchro- 27
nization process accepts data-units via the PMA_UNITDATA.request primitive. It attains frame and block 28
synchronization based on the PMA training frames and conveys received blocks to the PCS Receive pro- 29
cess. The PCS Synchronization process sets the block_lock flag to indicate whether the PCS has obtained 30
synchronization. The PMA training sequence includes 1 bit pattern every 180 PAM2 symbols, which is 31
aligned with the PCS Partial RS frame boundary, as well as an InfoField which is inserted in the 15th PCS 32
Partial RS frame. When the PCS Synchronization process is synchronized to the RS frame boundary using 33
this pattern, block_lock is asserted. 34
35
PHYs with the EEE capability support transition to the LPI mode when the PHY has successfully completed 36
training. Transitions to and from the LPI mode are allowed to occur independently in the transmit and 37
receive functions. The PCS receive function is responsible for detecting transitions to and from the LPI 38
receive mode and indicating these transitions using signals defined in 97.3.6. 39
40
The link partner signals a transition to the LPI mode of operation by transmitting one frame composed 41
entirely of 80B/81B blocks of LP_IDLES. When blocks of LP_IDLES are detected at the output of the 42
80B/81B decoder, rx_lpi_active is asserted by the PCS receive function and the LPI character is 43
continuously asserted at the receive GMII. After the sleep frame the link partner begins transmitting zeros, 44
and it is recommended that the receiver power down receive circuits to reduce power consumption. The 45
receive function uses RS frame counters to maintain synchronization with the remote PHY and receives 46
periodic refresh signals that are used to update coefficients, so that the integrity of adaptive filters and timing 47
loops in the PMA is maintained. LPI signaling is defined in 97.3.5. The quiet-refresh cycle continues until 48
the PHY detects the wake frame. The PHY receive function sends Idles to the GMII for the remainder of the 49
wake frame and then resumes normal power mode operation. 50
51
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53
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vector representing the side-stream scrambler state are arbitrarily set. The initialization of the scrambler state 1
is left to the implementer. In no case shall the scrambler state be initialized to all zeros. 2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
Figure 97–11—A realization of side-stream scramblers by 20
linear feedback shift registers 21
22
97.3.4.1 Generation of Sn 23
24
During PMA training, the training pattern is embedded with indicators to establish alignment to the RS FEC 25
block and the 15 partial frames that comprise the block. The last partial frame is embedded with an informa- 26
tion field used to exchange messages between link partners. PMA training signal encoding is based on the 27
generation, at time n, of the bit Sn. The first bit is inverted in the first 14 partial frames of each RS FEC 28
block. The first 96 bits of the 15th partial frame is XOR’d with the contents of the Infofield. 29
30
31
Scr n 0 1Infofield nmod 180 2519 nmod 2700 2616 32
33
Sn = Scr n 0 1 nmod 180 = 0 (97–7)
34
Scr n 0 otherwise 35
36
97.3.4.2 Generation of symbol Tn 37
38
The bit Sn is mapped to the transmit symbol Tn as follows: if Sn = 0 then Tn = +1, if Sn = 1 then Tn = -1. 39
40
97.3.4.3 PMA training mode descrambler polynomials 41
42
The PHY shall acquire descrambler state synchronization to the PAM2 training sequence and report success 43
through scr_status. For side-stream descrambling, the MASTER PHY shall employ the receiver descrambler 44
generator polynomial same as Equation (97–6) and the SLAVE PHY shall employ the receiver descrambler 45
generator polynomial same as Equation (97–5). 46
47
97.3.5 LPI signaling 48
49
PHYs with EEE capability have transmit and receive functions that can enter and leave the LPI mode 50
independently. The PHY can transition to the LPI mode when the PHY has successfully completed training. 51
The transmit function of the PHY initiates a transition to the LPI transmit mode when it generates a sleep 52
signal composed of 80B/81B blocks containing only LPI control characters, as described in 97.3.2.2.16. 53
54
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When the transmitter begins to send the sleep signal, it asserts tx_lpi_active and the transmit function enters 1
the LPI transmit mode. 2
3
Within the LPI mode PHYs use a repeating quiet-refresh cycle (see Figure 97–12). The first part of this 4
cycle is known as the quiet period and lasts for a time lpi_quiet_time equal to 354 partial RS frame periods. 5
The quiet period is defined in 97.3.5.2. The second part of this cycle is known as the refresh period and lasts 6
for a time lpi_refresh_time equal to 6 partial RS frame periods. The refresh period is defined in 97.3.5.3. A 7
cycle composed of one quiet period and one refresh period is known as an LPI cycle and lasts for an 8
lpi_qr_time equal to 24*15 = 360 partial RS frame periods. 9
10
lpi_offset, lpi_quiet_time, lpi_refresh_time, and lpi_qr_time are timing parameters that are integer multiples 11
of the partial RS frame period. lpi_offset is a fixed value equal to lpi_qr_time/2 + 15. It is used to ensure 12
refresh signals and wake start times are appropriately offset by the link partners. 13
14
15
16
17
18
19
20
21
22
23
24
25
26
Figure 97–12—LPI signal timing 27
28
29
PHYs begin the transition from the LPI receive mode when they detect the wake frame. 30
31
97.3.5.1 LPI Synchronization 32
33
To maximize power savings, maintain link integrity, and ensure interoperability, EEE-capable PHYs must 34
synchronize refresh intervals during the LPI mode. The quiet-refresh cycle is established from the Master 35
Partial Frame Count (PFC24) during PMA Training. At the master, partial frame zero and all multiples of 36
360 partial frames thereafter denote the start of the cycle. 37
38
An EEE-capable PHY in slave mode is responsible for synchronizing its partial frame count to the master’s 39
partial frame count during link up. The slave shall ensure that its partial frame count is synchronized to the 40
master’s partial frames within 1 partial frame. The start of the slave quiet-refresh cycle is delayed from the 41
master by 13 frames (195 partial frames). This offset ensures that the master and slave wake/sense windows 42
are offset from each other and that the refresh periods are nearly a half cycle offset. 43
44
Following the transition to PAM3, the PCS continues to count transmitted partial RS frames (tx_pfc), and 45
uses the counter to generate refresh and wake control signals for the transmit functions. 46
47
Wake frames may be sent at the beginning of every second RS frame boundary starting at the beginning of 48
the refresh RS frame. This sets wake_period to 30 partial RS frames. The master and slave allowable wake 49
positions do not overlap. The wake frame may start in the same RS frame as a planned refresh and obviate 50
this refresh. 51
52
The master and slave shall derive the refresh_active and wake_start signals from the transmitted partial RS 53
frames (tx_pfc) as shown in Table 97-3 and Table 97-4. 54
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Table 97–3—Synchronization logic derived from slave signal partial RS frame count 1
2
3
Slave-side Variable u = tx_pfc
4
tx_refresh_active=true lpi_offset – lpi_refresh_time mod(u, lpi_qr_time) < lpi_offset 5
6
tx_wake_start=true mod(u, wake_period) = 0 7
8
9
Table 97–4—Synchronization logic derived from master signal partial RS frame count 10
11
12
Master-side variable v = tx_pfc 13
14
tx_refresh_active=true mod(v, lpi_qr_time) lpi_quiet_time
15
16
tx_wake_start=true mod(v, wake_period) = wake_period/2
17
18
19
97.3.5.2 Quiet period signaling 20
21
During the quiet period the transmitter shall put zeros on to the MDI. During the quiet period the transmitter 22
and may be turned off to save power. 23
24
97.3.5.3 Refresh period signaling 25
26
During the LPI mode 1000BASE-T1 PHYs use staggered, out-of-phase refresh signaling to maximize 27
power savings. PAM3 refresh symbols are generated from the output of the data mode PCS side-stream 28
scrambler polynomials described in 97.3.2.2.13 with PCS transmit data masked to zero. The scramblers run 29
continuously regardless of the transmit mode. The refresh occupies the last 6 partial RS frames of where the 30
RS frame would occur if it were transmitted. 31
32
The OAM symbol and its associated parity symbols are XOR’ed with the scrambler stream at the same 33
relative position to the RS boundaries as they occupy during normal power mode. The parity is generated 34
using Equation (97–2) with D405 ... D1 = 0 and D0 = OAM. 35
36
97.3.6 Detailed functions and state diagrams 37
38
97.3.6.1 State diagram conventions 39
40
The body of this subclause is comprised of state diagrams, including the associated definitions of variables, 41
constants, and functions. Should there be a discrepancy between a state diagram and descriptive text, the 42
state diagram prevails. 43
44
The notation used in the state diagrams follows the conventions of 21.5. State diagram timers follow the 45
conventions of 14.2.3.2. The notation ++ after a counter or integer variable indicates that its value is to be 46
incremented. 47
48
49
50
51
52
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rx_coded<80:0> is shown in Figure 97–6. The leftmost bit in the figure is rx_coded<0> and the 1
rightmost bit is rx_coded<80>. rx_coded<81> (not shown in the figure) is set to 1 if all parity 2
checks of the Reed Solomon frame are satisfied, otherwise it is set to 0. 3
4
rf_valid 5
Boolean indication that is set true if received Reed Solomon frame is valid. The frame is valid if all 6
parity checks of the coded bits are satisfied. 7
8
rx_lpi_active 9
This variable is set TRUE upon detection of LP_IDLE. Set FALSE upon wake_detection. 10
11
rx_raw<99:0> 12
Vector containing 10 successive GMII output transfers. Each transfer is numbered from 0 to 9 with 13
the first transfer numbered as the 0th transfer. The nth GMII transfer is labeled as RX_DV[n], 14
RX_ER[n], RXD[n][7:0]. 15
For n = 0 to 9, rx_raw<8n> = RX_DV[n], rx_raw<8n+1> = RX_ER[n], rx_raw<8n+9:8n+2> = 16
RXD[n][7:0] 17
18
rx_wake_frame_complete 19
This variable is set TRUE at end of WAKE RS frame, otherwise FALSE. 20
21
tx_coded<80:0> 22
Vector containing the output from the 80B/81B encoder. The format for this vector is shown in 23
Figure 97–14. The leftmost bit in the figure is tx_coded<0> and the rightmost bit is tx_coded<80>. 24
25
tx_data_mode 26
Set true when tx_mode = SEND_N, otherwise false. 27
28
tx_lpi_active 29
This variable is set FALSE at next wake frame if non- LP_IDLE is detected on GMII in any block. 30
This variable is set TRUE on next RS frame if LP_IDLE detected on GMII in the last 80/81 block. 31
32
tx_raw<99:0> 33
Vector containing 10 successive GMII transfers. Each transfer is numbered from 0 to 9 with the 34
first transfer numbered as the 0th transfer. The nth GMII transfer is labeled as TX_EN[n], 35
TX_ER[n], TXD[n][7:0]. 36
For n = 0 to 9, tx_raw<8n> = TX_EN[n], tx_raw<8n+1> = TX_ER[n], tx_raw<8n+9:8n+2> = 37
TXD[n][7:0] 38
39
tx_wake_frame_complete 40
This variable is set TRUE at the end of the RS WAKE frame, otherwise FALSE. 41
42
lpi_tx_mode 43
A variable indicating the signaling to be used from the PCS to the PMA across the PMA_UNIT- 44
DATA.request (tx_symb) interface. 45
lpi_tx_mode controls tx_symb only when tx_mode is set to SEND_N. 46
The variable is set to NORMAL when !tx_lpi_active, indicating that the PCS is in the normal 47
power mode of operation. 48
The variable is set to REFRESH when (tx_lpi_active * tx_refresh active). 49
The variable is set to QUIET when (tx_lpi_active * !tx_refresh active). 50
51
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97.3.6.2.3 Timers 1
2
State diagram timers follow the conventions described in 14.2.3.2. 3
4
97.3.6.2.4 Functions 5
6
DECODE(rx_coded<81:0>) 7
In the PCS Receive process, this function takes as its argument 82-bit rx_coded<81:0> from the 8
Reed Solomon decoder and descrambler. If rx_coded<81> = 1 then the decoder decodes the 9
81B-Reed Solomon bit vector rx_coded<80:0> returning a vector rx_raw<99:0>, which is sent to 10
the GMII. The DECODE function shall decode the block based on code specified in 97.3.2.2.2. If 11
rx_coded<81> = 0 then the decoder returns EBLOCK_R. 12
13
ENCODE(tx_raw<99:0>) 14
Encodes the 100-bit vector received from the GMII, returning 81-bit vector tx_coded. The 15
ENCODE function shall encode the block as specified in 97.3.2.2.2. The ENCODE function shall 16
only encode LPI_IDLE while in the SEND_LPI state. Otherwise LPI_IDLE is converted to Idle in 17
the ENCODE function. 18
19
97.3.6.2.5 Counters 20
21
rfer_cnt 22
Count up to a maximum of RFER_CNT_LIMIT of the number of invalid Reed Solomon frames 23
within the current RFRX_CNT_LIMIT Reed Solomon frame period. 24
25
rfrx_cnt 26
Count number Reed Solomon frames received during current period. 27
97.3.6.3 Messages 28
29
PMA_UNITDATA.indication (rx_symb) 30
A signal sent by PMA Receive indicating that a PAM3 symbol is available in rx_symb. 31
32
PMA_UNITDATA.request (tx_symb) 33
A signal sent to PMA Transmit indicating that a PAM3 symbol is available in tx_symb. 34
35
PCS_status 36
Indicates whether the PCS is in a fully operational state. (See 97.3.7.1.) 37
38
RX_AGGREGATE 39
A signal sent to PCS Receive indicating that 9 aligned 9-bit Reed Solomon symbols are aggregated 40
in rx_coded<80:0>. 41
42
TX_AGGREGATE 43
A signal sent to PCS Transmit indicating that 10 GMII transfers are aggregated in tx_raw<99:0>. 44
45
RX_FRAME 46
A signal sent to PCS Receive indicating that a full Reed Solomon frame has been decoded and the 47
variable rf_valid is updated. 48
49
TX_FRAME 50
A signal sent to PCS Transmit indicating that a full Reed Solomon frame has been transmitted. 51
52
53
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tion for each receive block processed. The PCS shall perform the functions of RFER Monitor, Transmit, and 1
Receive as specified in these state diagrams. 2
3
97.3.7 PCS management 4
5
The following objects apply to PCS management. If an MDIO Interface is provided (see Clause 45), they are 6
accessed via that interface. If not, it is recommended that an equivalent access be provided. 7
8
97.3.7.1 Status 9
10
PCS_status: 11
Indicates whether the PCS is in a fully operational state. It is only true if block_lock is true and 12
hi_rfer is false. This status is reflected in MDIO register 3.32.12. A latch low view of this status is 13
reflected in MDIO register 3.1.2 and a latch high of the inverse of this status, Receive fault, is 14
reflected in MDIO register 3.8.10. 15
16
block_lock: 17
Indicates the state of the block_lock variable. This status is reflected in MDIO register 3.32.0. A 18
latch low view of this status is reflected in MDIO register 3.33.15. 19
20
hi_rfer: 21
Indicates the state of the hi_rfer variable. This status is reflected in MDIO register 3.32.1. A latch 22
high view of this status is reflected in MDIO register 3.33.14. 23
24
Rx LPI indication: 25
For EEE capability, this variable indicates the current state of the receive LPI function. This flag is 26
set to TRUE (register bit set to one) when the PCS Transmit Receive state diagram (Figure 97–15) 27
is in the RECEIVE_LPI or RECEIVE_WAKE states. This status is reflected in MDIO register 28
3.1.8. A latch high view of this status is reflected in MDIO register 3.1.10 (Rx LPI received). 29
30
Tx LPI indication: 31
For EEE capability, this variable indicates the current state of the transmit LPI function. This flag is 32
set to TRUE (register bit set to one) when the PCS Transmit state diagram (Figure 97–14) is in the 33
SEND_LPI or SEND_WAKE states. This status is reflected in MDIO register 3.1.9. A latch high 34
view of this status is reflected in MDIO register 3.1.11 (Tx LPI received). 35
36
97.3.7.2 Counters 37
38
The following counters are reset to zero upon read and upon reset of the PCS. When they reach all ones, they 39
stop counting. Their purpose is to help monitor the quality of the link. 40
41
RFER_count: 42
6-bit counter that counts each time RFER_BAD_RF state is entered. This counter is reflected in 43
MDIO register bits 3.33.13:8. The counter is reset when register 3.33 is read by management. Note 44
that this counter counts a maximum of RFER_CNT_LIMIT counts per RFRX_CNT_LIMIT 45
period since the RFER_BAD_RF can be entered a maximum of RFER_CNT_LIMIT times per 46
RFRX_CNT_LIMIT window. 47
48
97.3.7.3 Loopback 49
50
The PCS shall be placed in loopback mode when the loopback bit in MDIO register 3.0.14 is set to a one. In 51
this mode, the PCS shall accept data on the transmit path from the GMII and return it on the receive path to 52
the GMII. In addition, the PCS shall transmit a continuous stream of GMII to 81B-RS encoded PAM3 sym- 53
bols to the PMA sublayer, and shall ignore all data presented to it by the PMA sublayer. 54
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1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
Figure 97–14—PCS Transmit state diagram
53
54
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2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
Figure 97–15—PCS Receive state diagram 50
51
52
53
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PMA_UNITDATA.request
scr_status / pcs_status 13
rem_rcvr_status
rx_lpi_active
tx_lpi_active
loc_rcvr_status
14
link_status
(rx_symb)
(tx_symb)
tx_mode
15
config
16
17
18
19
20
21
22
23
24
recovered_clock 25
26
27
(MDI) 39
40
Figure 97–16—PMA reference diagram 41
42
NOTE—The recovered_clock arc is shown to indicate delivery of the recovered clock signal back to PMA TRANSMIT for loop timing.
43
44
97.4.2 PMA functions 45
46
The PMA sublayer comprises one PMA Reset function and five simultaneous and asynchronous operating 47
functions. The PMA operating functions are PHY Control, PMA Transmit, PMA Receive, Link Monitor, 48
and Clock Recovery. All operating functions are started immediately after the successful completion of the 49
PMA Reset function. 50
51
52
53
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The PMA reference diagram, Figure 97–16, shows how the operating functions relate to the messages of the 1
PMA Service interface and the signals of the MDI. Connections from the management interface, comprising 2
the signals MDC and MDIO, to other layers are pervasive and are not shown in Figure 97–16. 3
4
97.4.2.1 PMA Reset function 5
6
The PMA Reset function shall be executed whenever one of the two following conditions occur: 7
8
a) Power on (see 98.5.1) 9
b) The receipt of a request for reset from the management entity 10
11
All state diagrams take the open-ended pma_reset branch upon execution of PMA Reset. The reference 12
diagrams do not explicitly show the PMA Reset function. 13
14
97.4.2.2 PMA Transmit function 15
16
The PMA Transmit function comprises a transmitter to generate a 3 level modulated signals on the single 17
twisted pair. PMA Transmit shall continuously transmit onto the MDI pulses modulated by the symbols 18
given by tx_symb after processing with optional transmit filtering, digital to analog conversion (DAC) and 19
subsequent analog filtering. The signals generated by PMA Transmit shall comply with the electrical 20
specifications given in 97.5. 21
22
When the PMA_CONFIG.indication parameter config is MASTER, the PMA Transmit function shall 23
source TX_TCLK from a local clock source while meeting the transmit jitter requirements of 97.5.3.3. The 24
MASTER-SLAVE relationship shall include loop timing. If the PMA_CONFIG.indication parameter config 25
is SLAVE, the PMA Transmit function shall source TX_TCLK from the recovered clock of 97.4.2.8 while 26
meeting the jitter requirements of 97.5.3.3. 27
28
The PMA Transmit fault function is optional. The faults detected by this function are implementation 29
specific. If the MDIO interface is implemented, then this function shall be mapped to the transmit fault bit as 30
specified in 45.2.1.7.4. 31
32
97.4.2.3 PMA transmit disable function 33
34
97.4.2.3.1 Global PMA transmit disable function 35
36
When the Global_PMA_transmit_disable variable is set to TRUE, this function shall turn off the transmitter 37
so that the transmitter Average Launch Power of the Transmitter is less than –53 dBm. 38
39
97.4.2.3.2 PMA MDIO function mapping 40
41
The MDIO capability described in Clause 45 defines several variables that provide control and status 42
information for and about the PMA. Mapping of MDIO control variables to PMA control variables is shown 43
in Table 97–5. Mapping of MDIO status variables to PMA status variables is shown in Table 97–6. 44
45
46
47
48
49
50
51
52
53
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Table 97–5—MDIO/PMA control variable mapping 3
4
Register/bit 5
MDIO control variable PMA register name PMA control variable 6
number
7
Reset Control register 1 1.0.15 PMA_reset 8
Global transmit disable Transmit disable register 1.9.0 Global_PMA_transmit_disable 9
10
11
Table 97–6—MDIO/PMA status variable mapping 12
13
14
Register/bit 15
MDIO status variable PMA register name PMA status variable
number
16
Fault Status register 1 1.1.7 PMA_fault 17
18
Transmit fault Status register 2 1.8.11 PMA_transmit_fault 19
Receive fault Status register 2 1.8.10 PMA_receive_fault 20
21
22
23
97.4.2.4 PMA Receive function
24
25
The PMA Receive function comprises a receiver for PAM3 signals on the twisted pair. PMA Receive con-
26
tains the circuits necessary to both detect symbol sequences from the signals received at the MDI over
27
receive pair and to present these sequences to the PCS Receive function. The PMA translates the signals
28
received on the twisted pair into the PMA_UNITDATA.indication parameter rx_symb. The quality of these
29
symbols shall allow RFER of less than 3.6 10–7 after RS decoding, over a channel meeting the require-
30
ments of 97.5.6.
31
32
To achieve the indicated performance, it is highly recommended that PMA Receive include the functions of
33
signal equalization and echo cancellation. The sequence of symbols assigned to tx_symb is needed to per-
34
form echo cancellation.
35
36
The PMA Receive function uses the scr_status parameter and the state of the equalization, cancellation, and
37
estimation functions to determine the quality of the receiver performance, and generates the loc_rcvr_status
38
variable accordingly. The loc_rcvr_status variable is expected to become NOT_OK when the link partner’s
39
tx_mode changes to SEND_Z from any other values (see PHY Control state diagram in Figure 97-22). The
40
precise algorithm for generation of loc_rcvr_status is implementation dependent.
41
42
The receiver uses the sequence of symbols during the training sequence to detect and correct for pair polarity
43
swaps.
44
45
The PMA Receive fault function is optional. The PMA Receive fault function is the logical OR of the
46
link_status = FAIL and any implementation specific fault. If the MDIO interface is implemented, then this
47
function shall contribute to the receive fault bit specified in 45.2.1.7.5.
48
49
97.4.2.5 PHY Control function
50
51
PHY Control generates the control actions that are needed to bring the PHY into a mode of operation during
52
which frames can be exchanged with the link partner. PHY Control shall comply with the state diagram
53
description given in Figure 97–22.
54
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During PMA training (TRAINING and COUNTDOWN states in Figure 97–22), PHY Control information 1
is exchanged between link partners with a 12 octet InfoField, which is XOR’ed with the first 96 bits of the 2
15th partial RS FEC frame (bits 2520 to 2615) of the RS FEC frame. The InfoField is also denoted IF. The 3
link partner is not required to decode every IF transmitted but is required to decode IFs at a rate that enables 4
the correct actions prior to the PAM2 to PAM3 transition. 5
6
The 12 octet InfoField shall include the fields in 97.4.2.5.2 through 97.4.2.5.8, also shown in the overview 7
Figure 97–17, and the more detailed Figure 97–18 and Figure 97–20. Each message shall be transmitted at 8
least 256 times to ensure detection at link partner. 9
10
11
12
13
14
15
Figure 97–17—InfoField format 16
17
18
19
20
21
22
23
24
Figure 97–18—InfoField TRAINING format
25
26
27
28
29
30
31
32
Figure 97–19—InfoField COUNTDOWN format 33
34
35
36
37
38
Figure 97–20—InfoField message exchange format 39
40
41
97.4.2.5.1 Infofield notation
42
43
For all the InfoField notation below, Reserved<bit location> represents any unused values and shall be set to
44
zero and ignored by the link partner. The InfoField is transmitted following the notation described in
45
97.3.2.2.3 where the LSB of each octet is sent first and the octets are sent in increasing number order (that is,
46
the LSB of Oct1 is sent first).
47
48
97.4.2.5.2 Start of Frame Delimiter
49
50
The start of Frame Delimiter consists of 3 octets [Oct1<7:0>, Oct2<7:0>, Oct3<7:0>] and shall use the
51
hexadecimal value 0xBBA700. 0xBB corresponds to Oct1<7:0> and so forth.
52
53
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97.4.2.5.5 PHY Capability Bits, User Configurable Register, and Data Mode Scrambler Seed 1
2
When PMA_state<7:6>=00, [0ct8<7:0>, 0ct9<7:0>, 0ct10<7:0>] contains the two PHY capability bits 3
(Cap), the user configurable register bits, and the 15-bit data mode scrambler seed (Seed). Each octet is sent 4
LSB first. 5
6
The format of PHY capability bits is Oct9<7>=EEEen and Oct10<0>=OAMen, indicating EEE and OAM 7
capability enable respectively. The PHY shall indicate the support of optional capabilities by setting the cor- 8
responding capability bits to 1. Otherwise it shall set the capability bit to 0 to indicate no support for the 9
optional capability. 10
11
The data mode scrambler seed contains bits S14 (sent first) to S0 (sent last) to indicate the initial state of data 12
mode transmit scrambler of the local device upon reaching the data switch partial frame count. The state of 13
the scrambler in Figure 97–10 shall be S14:S0 at the first bit of the first RS FEC frame when the partial 14
frame counter equals to the DataSwPFC24 value, see 97.4.2.5.6. The format of Seed is Oct8<7:0> = 15
S<7:14> and Oct9<6:0> = S<0:6>. Seed S<14:0> shall not be all zeros. 16
17
The remaining 7-bit Oct10<7:1> shall be user configurable register. See 97.4.2.5.10 for details. 18
19
97.4.2.5.6 Data Switch Partial Frame Count 20
21
When PMA_state<7:6>=01, [Oct8<7:0>, Oct9<7:0>, Oct10<7:0>] contains the data switch partial frame 22
count (DataSwPFC24) sent LSB first. DataSwPFC24 indicates the partial frame count when the transmitter 23
switches from PAM2 to PAM3 which occurs at the start of a RS FEC block. The last value of PFC24 prior to 24
the transition is DataSwPFC24 - 1. 25
26
97.4.2.5.7 Reserved Fields 27
28
When PMA_state<7:6> is greater than 01, [Oct8<1:0>, Oct9<1:0>, Oct10<7:0>] contains a reserved field. 29
All InfoField fields denoted Reserved are reserved for future use. 30
31
97.4.2.5.8 CRC16 32
33
CRC16 (2 octets) shall implement the CRC16 polynomial (x+1)(x15+x+1) of the previous 7 octets, 34
Oct4<7:0>, Oct5<7:0>, Oct6<7:0>, Oct7<7:0>, Oct8<7:0>, Oct9<7:0>, and Oct10<7:0>. The CRC16 shall 35
produce the same result as the implementation shown in Figure 97–21. In Figure 97–21 the 16 delay ele- 36
ments S0,..., S15, shall be initialized to zero. Afterwards Oct4 through Oct10 are used to compute the 37
CRC16 with the switch connected, which is setting CRCgen in Figure 97–21. After all the 7 octets have 38
been processed, the switch is disconnected (setting CRCout) and the 16 values stored in the delay elements 39
are transmitted in the order illustrated, first S15, followed by S14, and so on, until the final value S0. 40
41
42
43
44
45
46
47
48
49
50
51
52
Figure 97–21—CRC16
53
54
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Once the link partner has transitioned from PAM2 to PAM3, PHY Control transitions to the SEND_IDLE2 1
state and starts the minwait_timer. 2
3
Upon expiration of the minwait_timer and when the condition loc_rcvr_statusloc_data_ready=OK and 4
PCS_statusrem_data_ready=OK is satisfied, PHY control transitions to the SEND_DATA state. 5
6
Upon entering the SEND_DATA state, PHY Control stops the maxwait_timer, starts the minwait_timer and 7
enables frame transmission to the link partner by asserting tx_mode=SEND_N. 8
9
The operation of the maxwait_timer requires that the PHY complete the startup sequence from state INIT_- 10
MAXWAIT_TIMER to SEND_DATA in the PHY Control state diagram state diagram (Figure 97–23) in 11
less than 97.5 ms to avoid link_status being changed to FAIL by the Link Monitor state diagram (Figure 97– 12
23). 13
14
97.4.2.5.10 PHY Control Registers 15
16
The PHY control registers are shown in Table 97–9. 17
18
19
Table 97–9—PHY Control Registers 20
21
Variable Name Register mapping 22
force_config (see 97.6.1.1) Master/Slave 1.2304.4 23
24
force_PHY_type (see 97.6.1.1) PHY Type 1.2304.3:0
25
OAM Ability 1.2305.11 26
EEE Ability 1.2305.10 27
PMA_state<7:6> = 00, Oct10<7:1> User Field 1.2306.10:4 28
29
PMA_state<7:6> = 00, Oct10<0> OAM Advertisement 1.2306.1
30
PMA_state<7:6> = 00, Oct9<7> EEE Advertisement 1.2306.0 31
LP PMA_state<7:6> = 00, Oct10<7:1> Link Partner User Field 1.2307.10:4 32
LP PMA_state<7:6> = 00, Oct10<0> Link Partner OAM Advertisement 1.2307.1 33
34
LP PMA_state<7:6> = 00, Oct9<7> Link Partner EEE Advertisement 1.2307.0
35
36
37
97.4.2.6 Link Monitor function 38
39
Link Monitor determines the status of the underlying receive channel and communicates it via the variable 40
link_status. Failure of the underlying receive channel causes the PMA to set link_status to FAIL, which in 41
turn causes the PMA’s clients to stop exchanging frames and restart the auto-negotiation (if enabled) or syn- 42
chronization (if auto-negotiation is not enabled) process. 43
44
The Link Monitor function shall comply with the state diagram of Figure 97–23. 45
46
Upon power on, reset, or release from power down, the Auto-Negotiation or PHY Link Synchronization 47
algorithms set link_control=DISABLE. If the presence of a remote station is sensed through reception of 48
DME data, the Auto-Negotiation process exchanges Auto-Negotiation information with the remote station. 49
During this period, link_status=FAIL is asserted. When the Auto-Negotiation function establishes the pres- 50
ence of a remote 1000BASE-T1 PHY or when the PHY Link Synchronization finishes the synchronization 51
function, link_control is set to ENABLE, and the Link Monitor state machines begins monitoring the PCS 52
and receiver lock status. As soon as reliable transmission is achieved, the variable link_status=OK is 53
asserted, upon which further PHY operations can take place. 54
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Values: 1
MASTER 2
SLAVE 3
4
en_slave_tx 5
The en_slave_tx variable in the InfoField received by the slave. 6
Values: 7
0: Master is not ready for the slave to transmit. 8
1: Master is ready for the slave to transmit. 9
10
link_control 11
When the Auto-Negotiation function is used, this variable is set as defined in Clause 98. 12
When the Auto-Negotiation function is not used, this variable is set as defined in 97.6. 13
14
link_status 15
The link_status parameter set by PMA Link Monitor and passed to the PCS via the 16
PMA_LINK.indication primitive. 17
Values: 18
OK 19
FAIL 20
21
loc_data_ready 22
This variable is set by the PMA Receive function to indicate the local PHY is ready or not ready to 23
receive data. The value of loc_data_ready is equal to OK only if loc_rcvr_status = OK and pcs_sta- 24
tus = OK. Otherwise its value is NOT_OK. This variable is conveyed to the link partner by the PCS 25
as defined in Table 97-1. 26
Values: 27
OK: The local PHY is ready to receive data. 28
NOT_OK: The local PHY is not ready to receive data. 29
30
loc_rcvr_status 31
Variable set by the PMA Receive function to indicate correct or incorrect operation of the receive 32
link for the local PHY. This variable is transmitted in the loc_rcvr_status bit of the InfoField by the 33
local PHY. 34
Values: 35
OK: The receive link for the local PHY is operating reliably. 36
NOT_OK: Operation of the receive link for the local PHY is unreliable. 37
38
loc_SNR_margin 39
This variable reports whether the local device has sufficient SNR margin to continue to the next 40
state. The criterion for setting the parameter loc_SNR_margin is left to the implementer. 41
Values: 42
OK: The local device has sufficient SNR margin. 43
NOT_OK: The local device does not have sufficient SNR margin. 44
45
PMA_refresh_status 46
This variable indicates the status of the Refresh Monitor as described in 97.4.2.7. 47
Values: 48
OK: Refresh is detected reliably. 49
FAIL: Refresh is not detected reliably. 50
51
pma_reset 52
Allows reset of all PMA functions. It is set by PMA Reset. 53
Values: 54
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ON 1
OFF 2
3
PMA_state 4
Variable for the value transmitted in the PMA_state<7:6> of the InfoField by the local PHY. 5
Values: 6
00: TRAINING state. 7
01: COUNTDOWN state. 8
9
PMA_watchdog_status 10
Variable indicating the status of the PAM3 monitor. 11
Values: 12
OK: The local device has received sufficient PAM3 transitions. 13
NOT_OK: The local device has not received sufficient PAM3 transitions. 14
15
rem_data_ready 16
This variable is set by the PCS Receive function to indicate whether the remote PHY is ready or not 17
ready to receive data. This variable is received from the link partner by the PCS as defined in Table 18
97-1. 19
Values: 20
OK: The remote PHY is ready to receive data. 21
NOT_OK: The remote PHY is not ready to receive data. 22
23
rem_rcvr_status 24
Variable set by the PCS Receive function to indicate whether correct operation of the receive link 25
for the remote PHY is detected or not. This variable is received in the loc_rcvr_status bit in the 26
InfoField from the remote PHY. This variable is set to NOT_OK if the PCS has not decoded a valid 27
InfoField from the remote PHY. 28
Values: 29
OK: The receive link for the remote PHY is operating reliably. 30
NOT_OK: Reliable operation of the receive link for the remote PHY is not detected. 31
32
tx_mode 33
PCS Transmit sends code-groups according to the value assumed by this variable. 34
Values: 35
SEND_N: This value is continuously asserted when transmission of sequences of code-groups 36
representing a GMII data stream take place. 37
SEND_I: This value is continuously asserted when transmission of sequences of code-groups 38
representing a idle stream take place. 39
SEND_T: This value is continuously asserted when transmission of sequences of code-groups 40
representing the training sequences of code-groups is to take place. 41
SEND_Z: This value is asserted when transmission of zero code-groups is to take place. 42
43
97.4.4.2 Timers 44
45
All timers operate in the manner described in 14.2.3.2. 46
47
maxwait_timer 48
A timer used to limit the amount of time during which a receiver dwells in the SILENT and 49
TRAINING states. The timer shall expire 97.5 ms 0.5 ms after being started. 50
This timer is used jointly in the PHY Control and Link Monitor state diagrams. The maxwait_timer 51
is tested by the Link Monitor to force link_status to be set to FAIL if the timer expires and 52
loc_rcvr_status, PCS_state or PMA_watchdog_status is NOT_OK. 53
See Figure 97–22 and Figure 97–23. 54
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1
minwait_timer 2
A timer used to determine the minimum amount of time the PHY Control stays in the SILENT, 3
TRAINING, SEND IDLE1 and SEND IDLE2 states. The timer shall expire 975 us 50 us after 4
being started. 5
6
7
8
9
10
11
12
13
14
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98
Draft Amendment to IEEE Std 802.3-2012 IEEE Draft P802.3bp/D1.4
IEEE 802.3bp 1000BASE-T1 PHY Task Force 16 March 2015
99
Draft Amendment to IEEE Std 802.3-2012 IEEE Draft P802.3bp/D1.4
IEEE 802.3bp 1000BASE-T1 PHY Task Force 16 March 2015
100