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Linear Waveshaping: V V C J R R
Linear Waveshaping: V V C J R R
net
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LINEAR WAVESHAPING
Introduction:
If a circuit is designed with components like R ,L and C then it is called linear circuit.
When sinusoidal signal is applied ,the shape of the signal is preserved at the output with
or without change in the amplitude and shape. But a non-sinusoidal signal alters the
output when it is transmitted through a linear circuit.
The process whereby the form of non-sinusoidal signals such as step, pulse,
square wave, ramp and exponential is altered by transmission through a linear network
is called linear wave shaping.
HIGHPASS RC CIRCUIT
Consider high pass RC circuit as shown in fig.1 below.
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Fig.1 Highpass RC circuit
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The capacitor offers high reactance at low frequency and low reactance at high
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frequency. Hence low frequency components are not transmitted ,but high frequencies are with
less attenuation. Therefore the output is large and the circuit is called a high pass circuit.
or
Let us see now is, what will be the response if different types of inputs, such as,
sinusoidal ,step, pulse, square wave, exponential and ramp are applied to a highpass circuit., like?
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R
Vo = Vi
R + 1 / jωC
Vo R R 1
= = =
Vi 1
2
1
2
1
2
2
R + R 1+ 1+
ωC ωCR ωCR
1
Let ω1 =
CR
Vo 1
= 2
Vi ω
1+ 1
ω
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At ω = ω1
Vo 1
= = 0.707
Vi 2
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fig.2 frequency response curve for sinusoidal input.
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At t = 0, Vi = Vo = B1 +B2
Therefore, B2 = Vi – B1
= Vi – V f
Hence the general solution is
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Vo = V f + ( Vi - V f ) e -t/τ
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Fall time tf: When a step is applied, the time taken for the output voltage to fall from 90%of its
initial value to 10% of its initial value is the fall time. It indicates how fast the output reaches its
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− t1
0.9 = e τ
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t1
e τ
= 1/0.9 = 1.11
t1 / τ = ln(1.11)
t1 = τ ln (1.11) = 0.1 τ
At t = t2, Vo (t) = 10% of V = 0.1V
−t2
0.1 = e τ
t2
e τ
= 1/ 0.1 =10
t2 = τ ln (10) = 2.3 τ
∴fall time, tf = t2- t1 = 2.3τ - 0.1τ = 2.2 τ
The lower half power frequency of the highpass circuit is
1
f 1=
2πRC
1
τ = RC =
2πf 1
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2 .2 0.35
Fall time = tf = 2.2 τ = =
2πf 1 f1
Hence, the fall time is inversely proportional to f1, the lower cut-off frequency.
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(iii) Pulse input: A pulse can be expressed as combination of a positive(negative) step followed
by negative(positive) step w.r.t. times i.e.
Vi = Vu (t) - Vu (t – tp) where tp is the duration of the pulse as shown below in fig.5
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At t = tp, the input abruptly falls by V . Vo also falls by the same amount.
At t = tp, Vo = V1 - V
Since V1 is less than V , Vo is negative and its value is V2 and this decays to zero exponentially.
−(t −t p )
)e
τ
For t > tp, Vo = ( V1 - V
−t p
But V1 = Ve τ
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−t p −(t −t p )
∴ Vo = V(e τ
−1) e τ
The response of a highpass circuit with pulse input for different values of τ is plotted in
fig.1.6.
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τ << t p A1=A2
It is very clear that output has distortion when a pulse is passing through a high pass RC
circuit. The shape of the pulse at the output is almost preserved when the time constant τ is very
large (fig.6b) whereas in fig.6c there is a tilt at the top of the pulse and an undershoot at the end
of the pulse.
If τ << tp (fig.1.6d), the output consists of a positive spike at the beginning of the pulse
and a negative spike at the end of the pulse, that means a highpass circuit converts a pulse into
spikes called ‘peaking’. To have a less distortion,τ must be very much larger than the time period
of the input pulse. In general, there is an undershoot at the end of the pulse. The area above the
axis(A1) is always equal to the area below (A2).
Area A1: 0< t< tp
−t
Vo = Ve τ
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tp tp
−t
−Vτ e−tτ
A 1= ∫Ve
0
τ
dt = 0
−Vτ e +Vτ = Vτ (1 − e
τ
A1 =
τ
)
Similarly
∞
−t p −(t −t p )
A2 = ∫V(e τ
−1)e τ
dt
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tp
∞
−tτ −(t −t p )
= ∫ Ve −Ve dt
τ
tp
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∞ ∞
Ve−tτ 1 −(t −t p )
− V
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= e τ
−1 −1
τ t p τ t p
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−tpτ
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−t p
A2 = Vτ e −Vτ = − Vτ (1 − e
τ
)
ar
A1 = A2
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Fig.8 output of a highpass for symmetric square wave input
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Whatever is the dc component associated with the periodic input, waveform the dc level of the
steady state output signal for the highpass circuit is always zero.
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This can be verified by using KVL equation
q
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= +
dt C dt dt
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dq
But i =
dt
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∫ dV
T
i = [Vi ]0 = Vi (T ) − Vi (0)
0
T T
Vo 1
∫τ
0
dt =
τ ∫ V dt
0
o
∫ dV
T
o = [Vo ]0 = Vo (T ) − Vo (0)
0
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Under steady-state conditions, the output and the input waveform are repetitive with a time period
T. Therefore, Vi (T ) = Vo (T ) and Vi (0) = Vo (0)
∫ V dt = 0
0
o
Since this integral represents the area under the output waveform over one cycle,it is
evident that the dc in the steady state is always zero.
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Now consider the response of the highpass RC circuit for a square wave input for
different values of the time constant, τ , fig.9.
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(d) Response when τ is very small
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Fig.9 Response of a highpass circuit for square input
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Consider the typical response of the highpass circuit for square wave input, fig.10
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−T1
We know that V1' = V1e τ
and V1' −V2 = V
−T2
And V2' = V2e τ
and V1 −V2' = V
T
For a symmetric squarewave T1 = T2 =
2
And because of symmetry V1 = −V2 and V1' = −V2'
From equation V1' −V2 = V
−T1
But V1' = V1e τ
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−T1
ThereforeV1e τ
−V2 = V
From V1 = −V2
Substituting ,we have
−T1
V1e τ
+V1 = V
−T1
V1 (1+ e τ
) =V
V
Thus, V1 = −T1
1+ e τ
T
For a symmetric squarewave as T1 = T2 = ,
2
V
therefore V1 =
1+e−T / 2τ
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But V1' = V1 e −T / 2τ
e−T / 2τ
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'
V =V 1 −T
or
2τ
(1+ e )
There is a tilt in the output waveform. The percentage tilt is defined as
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V1 − V1'
% Tilt = P = × 100 %
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V
2
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V Ve−T / 2τ
−
1 + e−T / 2τ 1 + e−T / 2τ ×100%
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P=
V
2
T
If << 1
2τ
T T
P ≅ × 100% since << 1
2τ 2t
T
P = × 100 %, for a symmetrical squarewave
2τ
1
The lower cut-off frequency, f1 =
2πτ
1
Therefore = πf1
2τ
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P = πf 1T × 100 %
πf 1 1
Therefore, P = × 100 %, since T =
f f
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(vi) Ramp input: Ramp waveform is one which increases linearly with time for t> 0 and is zero
for t<0.
Let the input to the highpass circuit be Vi = α t where α is the slope fig.13
1
αt =
τ ∫ V dt + V
o o
solving for Vo
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−t
Vo (t) = ατ 1 − e τ
t
If
τ
<< 1
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−t
t t2
e τ = 1− + 2
or
τ 2τ
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t t2
Therefore Vo (t ) = ατ 1 − 1 + − 2
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τ 2τ
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t
Vo (t ) = α t 1 −
Sm
2τ
The output falls away from the input, fig.14
Vi − Vo
et =
Vi
Vi = α t
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T
At t =T, Vi = αT , And Vo = α T 1 −
2τ
2
T αT
αT − αT (1 − )
Therefore et = 2τ = 2τ = T
αT αT 2τ
T 1
Thus, et = = ∏ f1T as = πf 1
2τ 2τ
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If the time constant of the RC highpass circuit is very much smaller than the time period of the
input signal, then the circuit behaves as a differentiator. Then the voltage drop across R is very small
when compared to the drop across C.
1
C∫
Vi = idt + iR
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But iR = Vo is small
1
Therefore Vi = ∫ idt
C
V
i= o .c
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R
1 1
∴Vi = Vi = ∫ Vo dt = ∫ Vo dt
or
τ τ
Differentiating
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dVi Vo
= fig.15 output of a differentiator
dt τ
ar
dV
Vo = τ i
Sm
dt
dV
∴ Vo ∝ i
dt
The output is proportional to the differential of the input signal, fig.15
1
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LOWPASS CIRCUITS,
Introduction:
Low pass circuit is one which allows low frequencies with less attenuation and high
frequencies with maximum attenuation. This is because capacitance offers high reactance
at low frequencies and hence there is an output.
LOWPASS RC CIRCUIT: Following is the lowpass RC circuit.
Lowpass RC Circuit
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At low frequencies the reactance of C is large and as frequency increases its
reactance decreases. Hence the output is larger for smaller frequencies and is
smaller for larger frequencies. Hence this circuit is called a lowpass circuit.
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Cosider the response of this circuit for different types of inputs.
i) SINUSOIDAL INPUT: For the circuit shown above, if sinusoidal signal is
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applied as an input, the output Vo is given by
1
or
jω C
Vo = Vi
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1
R+
jω C
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Vo 1
=
Vi 1 + jωCR
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Vo 1 1 1
= = ,where ω 2 =
Vi 1 + (ωCR )
2
ω
2 CR
1 +
ω2
Vo 1
At ω = ω 2 , = = 0.707
Vi 2
Hence, f2 is the upper cut-off frequency as shown in the response curve below.
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(ii) STEP INPUT: When a step voltage is applied as input to the lowpass circuit the
output will be appeared as shown in fig. Below.
We have RC = τ
−t
Vo = V f + (Vi − V f )e τ
Here, V f = V and Vi = 0
−t
−t
∴ Vo (t ) = V − Ve τ = V 1 − e τ
As t → ∞, Vo (t ) → V Response of lowpass circuit to step input
On the otherhand, the output can be obtained by solving the differential equation.
1
V = Vi = Ri + ∫ idt
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C
1
C∫
We know that idt = Vo
i dVo
= .c
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C dt
or
dVo
i=C
dt
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dVo
V = RC + Vo
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dt
dV
ar
V = τ o + Vo Solving for
dt
Sm
−t −t
Vo (t ) = Vo = V − Ve = V 1 − e τ
τ
Rise time: The time taken for the output to reach from 10% of its final value
to 90% of its final value is called rise time.
Fom equation
−t
Vo
= 1− e τ
V
From fig. at t = t1 , Vo = 0.1V
− t1
0 .1 = 1 − e τ
− t1
e τ = 0 .9
t1 = 0.1τ
Similarly at t = t2 , Vo = 0.9V
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−t
0.9 = 1 − e τ
e−t2 / τ = 0.1
t 2 = 2.3τ
Rise time t r = t 2 − t1 = 2.3 τ - 0.1 τ = 2.2 τ
1
Also f 2 =
2πRC
1
RC = τ =
2πf 2
2 .2 0.35
t r = 2.2 τ = =
2πf 2 f2
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Vo (t ) = −ατ + αt + ατe −t / τ
[ (
Vo (t ) = α t − τ 1 − e −t / τ )]
At t=T
[ )]
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(
Vo (T ) = α T − τ 1 − e −T / τ
Case 1 : If τ << T, then the deviation of the output from the input is very
small since
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e −T / τ ≈ 0
or
Vo (t ) = α (T − τ )
Case 2: If τ >> T, then e-T/τ can be expanded as series
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T T 2
Vo (t ) = α T − τ − 2
τ 2τ
ar
T 2 αT 2
Sm
= α T − T + = −−−−−− 2.36
2τ 2τ
The response is plotted in fig. below
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When a ramp is applied as input to a lowpass circuit, the output deviates from
the input which is defined as transmission error et. Mathematically it can be written as
Vi − V0
et =
Vi
αT − α (T − τ )
=
αT
τ
et =
T
1
f2 =
2πτ
1
τ=
2πf 2
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1 1
Therefore et = .
2πf 2 T
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Lowpass circuit as an integrator
or
For the lowpass circuit to behave as an integrator τ >>T , then the voltage
variation in C is very small
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1
C∫
Vi = iR + idt
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Vi ≅ iR
1
C∫
Since, idt << iR
Vi
i=
R
1 1 1
Therefore Vo =
C ∫ idt =
RC ∫ Vi dt = ∫ Vi dt
τ
The output is proportional to the integral of the input signal
Hence a lowpass circuit with large time constant produces an output that is proportional
to the integral of the input.
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Attenuators:
An attenuator is a circuit that reduces the amplitude of the signal by a finite amount.
A simple resistance attenuator is as shown below.
Resistive Attenuator
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The output is reduced depending on the choice of R1 and R2. The output of this
attenuator can be connected as input to an amplifier having a stray capacitance C2
and input resistance Ri.If Ri>>R2, then the effective value of resistance will be
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smaller than R2. The attenuator circuit will be now as
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or
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Reducing the two loop network into a single loop network by Thevenizing
R2 R2
VTh = Vi × = αVi where α =
R1 + R2 R1 + R2
and
Rth = R1 // R2
Hence the above circuit reduces to
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When the input αVi is applied to this lowpass RC circuit, the output will not
reach the steady-state value instantaneously. For e.g. in the above circuit,
R1=R2=1M and C2 = 20nF.Then the rise time tr = 2.2RthC2=2.2 × 0.5 × 106 × 20
× 10-9, tr = 22msec. which says that approximately after a time interval of 22 msec
after the application of the input αVi to the circuit, the output reaches the steady-
state value. Obviously this is an abnormally long time delay. An attenuator of this
type is called an uncompensated attenuator and the response is depending on
frequency. To make the response of the attenuator independent of frequency,
capacitor C1 is shunted across R1. This attenuator now is called a compensated
attenuator as shown in.fig.a ,and the same is redrawn as in fig.b
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fig.a Compensated Attenuator
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R1,R2,C1,C2 form four arms of the bridge. The bridge is said to be balanced when
R1C1=R2C2.Then no current flows in the branch xy. Hence for the purpose of
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When a step voltage Vi=V is applied as input, the output is calculated as follows:
At t=0+, as the capacitors will not allow any sudden changes in voltage, as the
input changes the output also should change abruptly, depending on the values of
C1 and C2.
C1
V (0 + ) = V
C1 + C 2
Thus, the initial output voltage is determined by C1 and C2.
As t→∞, the capacitors are fully charged and they behave as open circuits for dc.
Hence the resultant output is
R2
V0 (∞) = V
R1 + R2
Perfect compensation is obtained if, Vo(0+)=Vo(∞)
C1 R2
i.e. V =V
C1 + C 2 R1 + R2
From this we get
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C1R1=C2R2,or C1=(R2/R1)C2=Cp
and the output is αVi
Hence following conditions(cases) arise.
(i) .c
When C1=Cp, the attenuator is a perfectly compensated attenuator.
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(ii) When C1>Cp , it is an over-compensated attenuator and
(iii) When C1<Cp , it is an under-compensated attenuator.
or
The responses of the attenuator for step input is shown in the following fig.
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Case(i)
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Case(ii)
Case(iii)
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If a square wave is applied as input to a clamping circuit, the output reaches the steady-
state value after a few cycles. Hence for the input in Fig.(a) the output of the clamping
circuit is given in (b).
(a) input
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The output at steady-state is as in figure above with voltage levels V1, V11, V2 and V21.
This output can be plotted to scale if the voltages V1, V11, V2 and V21 are calculated. To
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calculate these four unknowns, we need four equations and these four equations are
obtained as follows.fig.
(a) consider the situation at t = 0-
At t = 0- , Vs =V11 and V0 = V21
The diode is reverse biased and the corresponding equivalent circuit is
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R
Vs = V11 and V21 = Vi
Rs + R
( Rs + R )
∴ Vi = V21
R
Substituting the values of Vs and Vi in equation 2
( Rs + R )
∴ VA(0-) = V11 – V21 -------- 3
R
(b) Consider the situation at the instant t = 0+
At t= 0+, Vs = V1 and V0 = V1. the diode is ON and the corresponding equivalent
circuit is
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The voltage across the capacitor terminals at t = 0+ is
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VA(0+) = Vs – Vi
= V1 - V i
or
Rf
V1 =Vi ,
Rs + Rf
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( Rs + Rf )
∴ Vi = V1
tz
Rf
ar
( Rs + Rf )
∴ VA(0+) = V1 - V1 -------- 4
Rf
Sm
VA(T1-) = Vs-Vi
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Rf + Rs 1
= V1 - V1 ------- 7
Rf
Similarly, at t = T1+ from the equivalent circuit, since D is OFF
∴ VA(T1+) = Vs – Vi
R + RS
= V11 - V2 ------- 8
R
Again as VA(T1-) = VA(T1 +), from equations 7 and 8
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Rf + Rs 1 R + RS
V1 - V1 = V11 - V2
Rf R
V = V1 – V11 =
Rf + Rs 1 R + RS
Rf
V1 -
R
V2
.c
------- 9
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Further at t = 0+, V0 = V1 and in the interval 0 to T1, V0 decays with a time constant
(Rf+Rs)C
or
−T1
w
1 (Rf +Rs )C
Hence, V1 = V1 e --------- 10
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Similarly in the interval T1 to T2, the diode is reverse biased and the circuit time constant
is (Rs+R)C
ar
(Rs +R )C
V2 1 = V2 e --------- 11
Equations 6, 9, 10 and 11 will enable us to determine the voltage V1, V11, V2 and V21. If
in the above circuit Rs = 0.
Equations 6 and 9 reduce to
V = V1-V21 = V11 – V2 -------- 12
It is evident from the above discussion that the output is independent of the levels V1 and
V11 associated with the input and is only determined by the amplitude V.
Subtracting equation 9 from equation 6
Rf + Rs R + RS
(V1 – V11) - (V21-V2) = 0 ------- 13
Rf R
If V1-V11 = ∆ f and V21 – V2 = ∆ r
From Equation 13
Rf + Rs R + RS
∆f = ∆r
Rf R
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Rf R + RS
∆f= . ∆r
Rs + Rf R
If Rs << R
Rf
∆f = ∆r ,
Rs + Rf
where ∆ f is the tilt in the forward direction and ∆ r is the tilt in the reverse direction .
Let Rs << Rf
Then ∆ f ≈ ∆ r
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To obtain the steady-state response of the circuit, first assume that VR is zero. Then this
circuit is clamping circuit that clamps the positive peak of the input signal to Vγ .Now the
steady-state response for the input of an unsymmetrical square wave, will be as follows.
om
.c
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or
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Solving four equations (we have discussed earlier) the values of V1, V11, V2 and V21 can
ar
be evaluated. To each of these values calculated add VR. With the result, the positive peak
Sm
If on the other hand, if the polarity of VR is reversed, add (-VR) to each of the values
computed. The result is that the positive peak in the output is clamped to (-VR).
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Diode as a switch:
A PN junction diode can be used as a switch. When diode is forward biased, the switch is
said to be in the ON state and in reverse-bias, the switch is in the OFF state. The V-I
characteristic of a PN junction diode is shown here.
om
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or
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.c
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Fig a) Minority carrier density distribution as a function of x, the distance from
or
the junction when the diode is ON
pn 0 = density of holes on the n-side at equilibrium
w
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When the diode is ON the number of minority carriers is large fig(a). When the polarity
of the external voltage is suddenly reversed, the diode forward current when ON being
large, is to be reduced to reverse current which is very small. But this is not happened as
it takes a finite time delay for the minority carrier density distribution to take the form
shown in fig.(b). During this period the injected minority carrier density will drop to zero
and the minority carrier density reaches the equilibrium value.
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Sm
As long as the voltage Vi = VF till t1, the diode is ON. The forward resistance of the
V
diode being negligible when compared to RL, therefore I F = F . At t = t1, the polarity
RL
− VR
of Vi is abruptly reversed, i.e.Vi = -VR and − I R = until t = t2 at which time
RL
minority carrier density pn at x = 0 has reached the equilibrium value pn0.
At t = t2 the charge carriers have been swept, the polarity of the diode voltage reverses,
the diode current starts to decrease.
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The time duration, t1 to t2, during which period the stored minority charge becomes zero
is called the storage time ts.
The time interval from t2 to the instant that the diode has recovered (V = -VR) is called
the transition time,tt.
The sum total of the storage time,ts and the transition time,tt is called the reverse recovery
time of the diode, trr.
∴ t rr = t s + t t
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Transistor switching times
or
Delay Time, td : It is the time taken for the collector current to reach from its initial value
w
If the rise of the collector current is linear, the time required to rise to 10%IC(sat) is 1/8
the time required for the current to rise from 10% to 90% IC(sat).
ar
It is given as
1
Sm
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Breakdown Voltages:
In a transistor switch, the voltage change which occurs at the collector with switching is
nominally equal to the collector supply voltage. Since this voltage change will be used to
operate other circuits and devices VCC should be made as large as possible. However, by
increasing the value of VCC, the reverse- bias voltage on the collector base diode may
become so large that avalanche breakdown may occur in the collector diode. The leakage
current IC0 will now become MIC0 where M is the avalanche multiplication factor. M
depends on VCB.
Following empirical relation for M, is considered for many transistor types.
1
M = n
VCB
1 −
BVCBO
where BVCBO is maximum reverse bias voltage that can be applied between the collector
and base terminals of the transistor when the emitter lead is open circuited .
om
When n is large, M remains almost approximately at unity till such time VCB reaches
BVCBO at which time it becomes infinity abruptly.
On the otherhand, if n is small, the onset of breakdown occurs more gradually.
.c
Let us consider the CB characteristics when extended into the breakdown region.
ld
or
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tz
ar
Sm
It is seen from the characteristics, that in the active region, IC varies slowly and IC rises
sharply as VCB reaches BVCBO.
The current gain in the CB configuration being hFB, the collector current IC = hFBIE.
Taking the avalanche multiplication into consideration, then
IC = MhFBIE
This means that if avalanche multiplication takes place, hFB is seen to have increased by a
factor M so that hFB* in the presence of avalanche multiplication is
hFB* = MhFB
CE configuration:
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om
1 − CB
BVCBO
n
VCB
= 1 - hFB
BVCBO .c
ld
and VCB = BVCBO n 1 − hFB
or
∴ VCE ≈ VCB
tz
hFB
As = hFE
ar
1 − hFB
and as hFB ≈ 1
Sm
h 1
1 − hFB = FB ≈
hFE hFE
From above equations
1
BVCEO = BVCBO n
hFE
If for a transistor, n = 6, hFE = 50
BVCEO = 0.52 × BVCBO
If BVCBO = 40V
BVCEO = 0.52 × 40 = 20.8V
BVCEO is approximately half of BVCBO
The CE characteristics extended upto BVCEO are plotted here.
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MULTIVIBRATORS
multivibrator remains in one of the stable states until we are asked to change. Hence this
om
circuit is essentially used as a memory element in digital circuits..
.c
A monostable multi has only one stable state and one quasi-stable state. Initially the multi
ld
is in stable state. After the application of a trigger, the multi goes into the quasistable
or
state and stays there for a finite time and will return back to the initial stable state. Such a
w
Other type of multivibrator is an Astable multi which has two quasistable states. This
Sm
means that change of state occurs in the multi simultaneously. So, the output of this multi
digital circuits.
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BISTABLE MULTIVIBRATORS
Introduction:
. This circuit has two devices Q1 and Q2. Let initially be Q1 , OFF and Q 2 , ON .
On the application of a trigger Q1 goes to ON and Q2 goes to OFF . When next trigger is
applied Q1 goes OFF and Q2 goes ON. If the ON device is driven in to saturation, the
Binary is called saturating Binary. If on the otherhand, the ON device is held in the active
region, the binary is called a non-saturating binary.
Consider two types of Bistable multivibrator circuits.
1. Fixed bias binary
2. Self bias binary
Fixed bias binary:
The circuit shown in fig.below is a fixed-bias binary
om
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ld
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Sm
Let initially Q1 be OFF and Q2 be in ON. Then the voltage at the first collector is VCC
and the voltage at the second collector is VCE(sat) . If a negative trigger is applied at the
base of the ON device (Q2), Q2 goes into the OFF i.e. its collector voltage rises to VCC .
Consequently Q1 goes into the ON state and its collector voltage falls to VCE(sat).
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To verify whether Q1 is really OFF and Q2 is really ON and in saturation, consider the
following circuit.This circuit uses npn silicon transistors having hFEmin = 50,
VCE(sat)=0.3V, VBE(sat)= 0.7V, VCC=12V, VBB=12V, RC=1K, R1=10K, R2=20K
om
.c
ld
or
To verify this, base current IB2 and its collector current IC2 should be calculated.
tz
If the base current calculated is much in excess of the minimum base current then Q2 is
really in saturation.
ar
To verify Q1 is in OFF :
The transistor Q1 is OFF if its base–emitter junction is reverse biased. For this ,
Sm
the voltage at the base of Q1 is to be calculated. If it reverse biases the emitter junction,
then the transistor Q1 is indeed in the OFF state.
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Vσ − (−VBB ) 12.7
I2 = = = 0.635mA
R2 20 K
IB2 = I1-I2 = 1mA-0.635mA = 0.365mA
om
To calculate IC2:
.c
ld
or
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12 − 0.3
I3 = = = 11.7 mA
RC 1K
Sm
I C 2 = I 3 − I 4 = 11.7 − 0.41
= 11.29mA
To verify Q2 is in saturation:
IC2 11.29mA
I B 2 min = = = 0.226mA
hFE min 50
For Q2 to be in saturation
I B 2 ≅ 1.5I B 2 min
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.c
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The voltage VB1 at the base of Q1 is due to two sources, -VBB source and VCE(sat) source.
or
Using the superposition theorem
w
R2 R1
VB1 = VCE ( sat ) + (−VBB )
tz
R1 + R2 R1 + R2
20 10
ar
= 0.3 × − 12 ×
30 30
Sm
= 0.2-4
= - 3.8V.
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Vσ − (−V BB )
R2 =
I2
1
om
Choose I 2 ≈ IC2
10
= 0.5mA
∴ R2 =
0.7 + 12 12.7V
0 .5
=
0.5mA
= 25.4 KΩ
.c
ld
≈ 22 KΩ
or
I 5mA
I B 2 min = C 2 = = 0.1mA
hFE min 50
w
tz
If Q2 is in saturation
I B 2 = 1 . 5 I B 2 min
ar
= 0 . 15 mA
Sm
I 1 = I 2+ I B 2
= 0 . 5 mA + 0 . 15 mA = 0 . 65 mA
V CC − V σ 12 − 0 . 7 11 . 3V
R C + R1 = = = = 17 . 38 K Ω
I1 0 . 65 mA 0 . 65 mA
R1 = ( R C + R1 ) − R C
=17 . 38 − 2 . 36 = 15 . 02 K Ω
Choose R1 = 15 K Ω
The circuit, so designed, with component values indicated is shown below:
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After the design is complete, verify whether Q2 is in saturation and Q1 is OFF or not.
VCC − VCE ( sat )
IC 2 ≈
2.2 K
12 − 0.2V 11.8V
= = = 5.36mA
2.2 K 2.2 K
5.36mA
I B 2 min = = 0.107mA
50
V + VBB 12.7
I2 = σ = = 0.58mA
R2 22 K
VCC − Vσ
I1 =
RC + R1
12 − 0.7
om
=
2 + 10
11.3
=
12
.c
ld
= 0.94mA
I B 2 = I1 − I 2
or
= 0.94mA − 0.58mA
w
= 0.36mA
tz
I B 2 ≥ I B 2 min
ar
Hence Q2 is in saturation
R2 R1
Sm
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Sm
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om
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Unsymmetrical triggering of a binary
or
Let the trigger be applied to the collector C1 of the circuit at t=0. If Q1 is OFF, D1 is ON
and this negative pulse appears at the base of Q2 as the first collector and second base are
w
connected. Q2 goes into the OFF state and Q1 into the ON state.The next through C1
tz
trigger pulse, i.e. the Reset pulse, is applied through D2 at the second collector C2 which
is coupled to the first base through C1. Q1 now goes into the OFF state and Q2 into the
ar
ON state. Unsymmetrical triggering is used to generate a gated output, the width of this
gate must be at least equal to the spacing between two successive triggers.
Sm
To prevent the loading down problem from the trigger source , R should be large.
But when a trigger is applied, a charge is built up on the condenser Ci. If the charge is to
be quickly removed before the application of the next trigger signal at this terminal, R
should be small. So while choosing the value of resistance R a compromise is necessary.
A single resistance cannot simultaneously satisfy these two requirements. Hence in place
of R, diodes D3 and D4 are used. When a pulse appears, the diode is OFF (D3 or D4), a
large reverse resistance of the diode appears in place of R. Otherwise the diode is ON
offering negligible resistance so that the charge on the capacitance can be quickly
removed.
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Symmetrical triggering:
In symmetrical triggering, one triggering pulse generator is taken to change from
one stable state to the other in one direction. The same is used to change the state in
reverse direction also. This method of triggering is normally used in counters.
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Symmetric triggering of binary
or
The purpose of D is similar to the diodes D3 and D4 used earlier. The first trigger pulse
w
makes D1 conduct and this pulse is coupled to the base of Q2 and drives Q2 into the OFF
tz
state and Q1 into the ON state. The next trigger pulse applied at t = tp is coupled to the
base of Q1 as D2 is now ON. Hence Q1 again goes into the OFF state and Q2 into the ON
ar
state. D1 and D2 are called steering diodes as these diodes steer the trigger pulse train.
Sm
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Self-bias binary :
In a fixed bias binary there are two separate sources, VCC and VBB. Instead two
we can design a binary with one power supply using self-bias method.
om
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Self-bias Binary
or
Let Q2 be ON and in saturation, in the initial stable state. As a result IB2 and IC2 flow
through RE developing a voltage VEN. The voltage between the base emitter terminals of
w
If this voltage reverse biases the emitter diode of Q1, then Q1 is indeed in the OFF state.
To calculate the stable state currents and voltages consider a practical circuit.
ar
In npn silicon transistors are used. VBE(sat) = 0.7V, VCE(sat) = 0.4V and hFEmin = 50,
VCC = 20V, RC = 6.7K, R1 = 30K and R2 = 15K, RE = 400Ω
Sm
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R2
Vthb = VCC ×
RC + R1 + R2
15
= 20 ×
4.7 + 30 + 15
= 6.03V
and
R2 ( RC + R1 )
Rthb=R2//(RC+R1) =
R2 + RC + R1
(15)(30 + 4.7)
=
4.7 + 30 + 15
=10.47K
( R1 + R2 )
om
Vthc = VCC ×
RC + R1 + R2
20 × (30 + 15)
=
4.7 + 30 + 15 .c
ld
= 18.10V
or
Rthc = ( R1 + R2 ) // RC
w
(30 + 15)(4.7)
=
tz
30 + 15 + 4.7
= 4.25K
ar
Sm
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IB2=0.35mA
IC2=3.79mA
I 3.79mA
I B 2 min = C 2 =
hFE 50
= 0.076mA
I B 2 >> I B 2 min
Hence Q2 is saturation
∴ VEN = VEN 2 = ( I B 2 + I C 2 ) RE
VCN 2 = VEN 2 + VCE ( sat )
= (1.66V + 0.4V ) = 2.06V
VBN 2 = VEN 2 + Vσ
= (1.66V + 0.7V ) = 2.36V
R2
VBN 1 = VCN 2 ×
om
R1 + R2
2.06 × 15
=
15 + 30
= 0.69V .c
ld
VBE1 = VBN 1 − VEN 2
= (0.69V − 1.66) = −0.97V
or
V − VBN 2
I1 = CC
RC + R1
tz
20 − 2.36
ar
=
4.7 + 30
= 0.51mA
Sm
VCN 1 = VCC − I1 RC
= 20 − (0.51)(4.7)
= 17.6V
The stable state voltages are
VCN1=17.6V, VBN1=0.69V
VCN2=2.06V VBN2=2.36V
VEN=1.66V
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.c
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Solution:
1 1
or
Assume VEN= VCC = × 9 = 3V
3 3
w
4mA
IB2min = = 0.08mA
ar
50
Sm
VEN 2 3V
RE = = = 0.728 KΩ
I C 2 + I B 2 4.12mA
Select RE ≈ 500 Ω
V − VCE ( sat ) − VEN 2
RC = CC
IC
9 − 0.3 − 3 5.7V
= = = 1.425KΩ
4mA 4mA
Choose RC=1K
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Let
1 1
I2 = I C 2 = × 4mA = 0.4mA
10 10
V BN 2 = V EN 2 + Vσ = 3 + 0.7 = 3.7V
V BN 2 3.7V
R2 = = = 9.25 K
I2 0.4mA
Choose R2 = 10K
Find I2 for this R2
VBN 2 3.7V
I2 = = = 0.37mA
R2 10 K
VCC − VBN 2
RC + R1 =
I2 + I B2
9 − 3 .7 5.3V
= 10.8 KΩ
om
= =
0.37 + 0.12 0.49mA
( RC + R1 ) = 10.8 KΩ
( RC + R1 ) − RC = 10.8 − 1 = 9.8 KΩ
.c
ld
Choose R1 = 10K
or
w
tz
ar
Sm
Having fixed the component values, once again verify whether Q2 is really in
saturation or not and Q1 is OFF or not.
When calculated
IB2=0.149mA, IC2=5.46mA, IB2min=0.109mA, VEN2=2.8V, VCN2=3.1V, VBN1=1.55V,
VBE1=VBN1-VEN2= -1.25V
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Monostable Multivibrator
Introduction:
This circuit consists of two active devices Q1 and Q2, one is in the OFF state, say (Q1)
and the other, Q2 in the ON state. These devices remain in the same state forever. Only on
the application of a trigger, the multi goes into the quasistable state (Q1 ON and Q2 OFF)
and after a time interval T, will return to the stable state (Q1 OFF and Q2 ON). Thus this
circuit generates a gate pulse of duration T.
The output of this circuit is high for a time duration T called the pulse duration, pulse
width or gate width.
Collector-Coupled monostable multi: The collector coupled monostable multivibrator
is shown below.
om
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or
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Sm
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Charging of C
om
C now tries to charge to VCC through RC of Q1 and small input resistance of Q2,. As
t→ ∞ , this voltage reaches VCC. On the application of a trigger at t=0, (a negative pulse at
.c
B2), Q2 goes into the OFF state and Q1 is driven into the ON state and preferably into
saturation. Hence there is a current I1 in Q1. VC1 is VCE(sat), if I1=IC(sat)
ld
or
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The charge on C now discharges with a time constant τ=RC,. As a result the voltage at
B2 changes as a function of time .When this voltage VB2 at B2 reaches Vγ after a time
interval T, Q2 is switched ON and Q1 is switched OFF due to regeneration, thus ending
the quasistable state.
The voltage variation at B2 of Q2
om
Fig.7.5. Voltage variation at the base of Q2 in the quasistable state.
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Fig. . Monostable as a voltage to time converter
or
The time T for which Q1, in the quasistable state, is ON and Q2 is OFF is calculated.
w
VB 2 (t ) = V f − (V f − Vi )e τ
Vf = V
Vi = Vσ – I1RC
If Q1 is in saturation
I1RC=VCC-VCE(sat)
Vi=Vσ – VCC+VCE(sat)
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−t
(V + VCC )
T = τ ln
V
V
T = τ ln(1 + CC )
V
Thus, to change T, V can be varied.
om
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or
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ASTABLE MULTIVIBRATOR
Introduction:
Two cross-coupled switching circuits are connected in this arrangement. The
devices in this Multivibrator will not remain in one state (either ON or OFF) forever.
Change of state in the devices occurs continuously after a finite time interval depending
on the circuit components used. Hence this circuit has two quasistable states.
Let Q1 and Q2 be two transistors used. If Q1 is ON, then Q2 is OFF. These will
remain in this state only for a fixed time duration after which Q1 switches into the OFF
state and Q2 into the ON state without applying triggering pulse and this process is
repeated. Therefore it is also called Free running multivibrator. The output of the circuit
is a squarewave, having two time periods,T1 and T2. If T1 = T2=T/2 , then the circuit is a
symmetric astable multivibrator. If T1≠ T2, then it is called an unsymmetrical astable
multi-vibrator. The astable multivibrator is essentially a squarewave generator.
om
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or
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Sm
astable multi
Assume that transistor Q1 is OFF and Q2 is ON initially. Then VB2 = Vσ, VC2 = VCE(sat)
and VC1=VCC. With Q1 OFF and Q2 ON, C1 will try to charge to the supply voltage
through the collector resistance RC1 and through the base and emitter terminals of Q2 .
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Charging of capacitor C1
Prior to this condition, Q2 must have been in the OFF state and Q1 must have been
in the ON state. As a result C2 must have been charged through RC2 . Between the base
and emitter terminals of Q1,
om
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or
Charging of capacitor C2
When Q2 suddenly changes from the OFF state to ON state, the voltage between its
w
collector and emitter terminals is VCE( ≈ 0V). Hence the collector of Q2 is at ground
tz
potential i.e. the positive end of the capacitor C2 is at the ground potential and its negative
terminal is connected to base of Q1. As a large negative voltage is now coupled to base of
ar
But Q1 is not going to remain in the OFF state forever. Now, with Q2 ON, the
charge on the capacitor C2 discharges with a time constant τ2 = R2C2.
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discharge of C2 through R2
or
a voltage drop across RC1 and the voltage at the collector of Q1 falls. Earlier this voltage
tz
was VCC and now it is smaller than VCC. Therefore, the negative step at this collector is
coupled to the base of Q2 through C1. As the collector of Q1 and the base of Q2 are
ar
connected through C1 and as a capacitor will not allow any sudden changes in voltage,
whatever is the change that has taken place at the first collector an identical change takes
Sm
place at the base of Q2. As a result the base current of Q2 is reduced, its collector current
is reduced and the voltage at its collector rises. This positive step change is coupled to the
base of Q1. Its base current further increases. The collector current increases, the voltage
at the collector of Q1 further falls and this change is coupled to the base Q2 and this
process is repeated. Thus a regenerative action takes place and Q2 switches into the OFF
state and Q1 goes into the ON state.
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The waveforms at the base and collectors of Q1 and Q2 are shown below.
om
.c
Waveforms of collector–coupled astable multi
ld
When suddenly the transistor changes from the OFF state to the ON state there could be a
or
small overshoot at this base and at the collector of the other transistor.
Further, it is seen that when a transistor changes from the ON state into OFF state,
w
say Q1, its collector voltage is required to abruptly rise to VCC. But when Q1 is OFF and
tz
Q2 is ON, there is a charging current of capacitor C1. As a result the voltage VC1 will not
suddenly rise to VCC. Only when this charging current is zero, the collector voltage
ar
reaches VCC . Hence, there is rounding off of the rising edge of the pulse.
Sm
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om
dt dt
=
dV S
t =0
dt
.c
ld
(b) Displacement error, ed is the maximum difference between the actual sweep voltage
or
and the linear sweep which posses through the beginning and end points of the a sweep.
w
(V s − Vs' ) max
ed =
Vs
tz
ar
Sm
(c)Transmission error, et
If a ramp voltage is transmitted through a highpass RC circuit, the output falls away from
the input.
(Vs' − Vs )
et =
Vs'
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(1) Exponential sweep generator: A simple exponential sweep generator and its output
are shown in Figs. a) and b) respectively
If initially the capacitor is uncharged and t = 0 the switch S is open, the capacitor charges
to the supply voltage V.
Fig.a) A simple exponential sweep generator Fig.b) Output of the sweep generator
om
If the resistance offered by the switch is ideally not zero there is a finite time delay
before the signal reaches its initial value. This time delay is called flyback time,
restoration time or retrace tie.
Normally Tr << Ts , so T ≈ Ts .c
ld
or
w
tz
ar
Sm
vc (t ) = V f − (V f − Vi )e −t / τ
= V − (V − 0)e − t / τ
v c ( t ) = v s = V (1 − e − t / τ )
Assume that after an interval Ts when vs = Vs, the switch closes. The charge on the
capacitor discharges with a negligible time constant and the voltage abruptly falls to zero
at t = TS.
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v s = V (1 − e − t / τ )
dv s 1 V
= −Ve −t / τ ( − ) = e −t / τ
dt τ τ
dv s V
t=0 =
dt τ
−TS
dv s V
t = TS = e τ
dt τ
−TS
V V
− e τ
−TS
∴ es = τ τ
om
= 1 − e τ
V
τ
at t = TS , v s = Vs
.c
ld
−TS
Vs = V 1 − e τ
or
Hence
w
−TS Vs
tz
∴1 − e τ
=
V
ar
Vs
es =
V
From above equation it is evident that es is small when V >> Vs . i.e. the linearity
improves if V is large when compared to Vs . Therefore, a simple exponential sweep
suffers from the disadvantage that a linear sweep is generated only when the sweep
amplitude is very much small when compared to the applied d.c. voltage, V
t
If << 1
τ
−t t t2 t3
e τ
= 1− + − +Λ
τ 2τ 2 6τ 3
vs = V 1 − e τ
−t
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t t2 t3
= V 1 − 1 + − 2 + 3 Λ
τ 2τ 6τ
Vt t t2
= 1
τ 2τ 6τ 2
− +
Since vs = Vs at t = Ts
To first approximation
' VTs
Vs =
τ
As this is a linear sweep
V T
es = s = s
om
V τ
.c
If the actual sweep is non-linear, consider the first two terms
ld
Vt t
1 −
or
vs =
τ 2τ
w
VT T
∴ V s = s 1 − s
τ 2τ
tz
et =
Vs'
VTs VTs Ts
− 1 −
τ τ 2τ
=
VTs
τ
Ts
et =
2τ
Now,
Ts
es =
τ
If we relate es and et
Ts e s
et = =
2τ 2
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Displacement error, ed is
(v S − v S' ) max
ed =
Vs
Vt t
vs = 1 −
τ 2τ
Vt
v1s =
τ
Vt t
(v s − v 1s ) = ×
τ 2τ
om
Ts
The deviation is maximum at t =
2
(v s − v1s ) max =
VTs Ts
×
2τ 4τ .c
ld
Vt
vs =
or
τ
At t = Ts v s = Vs
w
tz
VTs
∴ Vs =
τ
ar
VTs Ts
1 ×
(vs − v ) 2 4τ
Sm
∴e d = s max
= τ
Vs VTs
τ
Ts Ts
= =
8τ 8τ
1
ed = e s
8
The interrelationship between the three types of errors is given below
1 1
ed = es = et
8 4
If we know one type of error, we can calculate the other types of errors
I
If the capacitor is charged with a constant current I then the voltage across C = t.
C
Hence, the rate of change of voltage with time is called sweep speed.
I
Sweep speed =
C
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UJT SWEEP
om
Fig.(b) d.c.circuit
RBB
tz
When V1 ≥ ηVBB D is ON and a large number of charge carriers exist on the N-side,
Sm
reducing the resistance and the device conducts heavily, switch S is closed. The V-I
characteristic of a UJT is shown in fig.c
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om
Fig.c A practical UJT sweep generator and its output
vs = VBB 1 − e τ
−t
At t = Ts , v s = ηVBB .c
ld
ηVBB = VBB 1 − e
−t
τ
or
−TS
w
VBB e = VBB (1 − n)
τ
1
tz
Ts = τ ln
(1 − n)
ar
Alternately
Sm
−t
vs = V f − (V f − Vi )e τ
−t
= VBB − (VBB − Vv )e τ
At t = Ts , vs = Vs = V p
−TS
V p = VBB − (VBB − Vv )e τ
(VBB − VV )
Ts = τ ln
(VBB − VP )
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om
Fig.(a) Output characteristics of CB configuration
It is evident from the above characteristics that if a capacitor is charged using the
.c
constant collector current of the CB configuration, the resultant sweep voltage must be a
linear sweep voltage. Fig.b shows the circuit of a transistor constant current sweep
ld
generator using the CB configuration.
or
w
tz
ar
Sm
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To determine the sweep voltage Vs, consider the small signal model of the transistor in
CB configuration.fig.c
om
dt
dv s
h fb I e + hobVs = −C
dt
I e (R E + hib ) + hrbVs = Vi .c
ld
Vi − hrbV s
∴ Ie =
or
R E + hib
− CdV S V − hrbVS
w
∴ = h fb i + hobVs
dt RE + hib
tz
dV s h fb hrb h fbVi h V
VS + + ob s = 0
ar
−
dt C (R E + hib ) C (RE + hib ) C
dv s 1 h fb hrb
Sm
− h fbVi
+ hob − VS =
dt C (RE + hib ) C ( RE + hib )
1 αhrb 1
Let α = − h fb and = hob +
τ RE + hib C
dV 1 αVi
∴ s + Vs =
dt τ C (RE + hib )
αVi
Let =K
C (RE + hib )
dV s 1
+ Vs = K
dt τ
Solving, we have
Vs (t ) = τK 1 − e τ
−t
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ατVi 1 − e − t τ
Vs (t ) =
C (RE + hib )
−t
Expanding e τ
and taking only the first term
αVi t
Vs =
C (RE + hib )
Vi
But at t = 0, I e =
RE + hib
Therefore we have
αI t
Vs = e
C
At t = Ts, Vs = Vs
αViTs
∴VS =
(RE + hib )C
om
CVs (RE + hib )
∴ Ts =
αVi
where Ts is the sweep duration and Vs is the sweep amplitude.
.c
ld
Ts CV ( R + hib ) 1 αhrb
= s E hib +
or
The slope error es =
τ α Vi C R E + hib
w
= +
αVi Vi
ar
VS
∴ es = hrb +
hob
(RE + hib )
Vi
Sm
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om
Fig. Method to linearize a non-linear sweep
Miller Sweep:
.c
Now let Z be the ground terminal, and redrawing the above circuit
ld
or
w
tz
ar
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Bootstrap Sweep: Let Y be the ground terminal redrawing the above circuit and
replacing the auxiliary generator by an amplifier with X and Y as input terminals the
amplifier should have again of unity as v = vC
om
.c
Fig. Bootstrap sweep generator
ld
This type of sweep generator is called a Bootstrap sweep generator
or
w
tz
ar
Sm
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om
Thevenising the circuit at the input
Ri 1
V ' =V =V
R + Ri
1+
R
Ri .c
ld
R × Ri
R' =
or
R + Ri
w
tz
ar
Sm
Let Ro = 0
At t = 0 the voltage across the capacitor is zero
∴ vi − Avi = 0 , v i (1 − A) = 0 , v i = 0
v i = AVi = Vo = 0
As t → ∞, the capacitor is fully charged no current flows in it and hence can be replaced
by an open circuit for
the purpose of finding out the output
voltage. The resultant circuit is
At t = ∞ , V i= V '
Hence V 0= AV '
Vs
We know that es =
V
where Vs = sweep amplitude
V = total peak to peak excursion of the exponential
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Vs Vs Vs 1
Hence, es = = = ×
Miller
V0 / A / V ' / A / V '
Vs 1 + R / Ri
Substituting , eSMiller = ×
/ A/ V
Vs 1 + R / Ri V
= × ,where s is the slope error of the exponential sweep.
V / A/ V
1 + R / Ri
∴ esMiller = eS × .Even if Ri is small, as A is large, the slope error of a Miller’s
A
sweep is very small. Hence, for all practical purposes this sweep generator produces a
near linear sweep.
om
.c
ld
or
w
tz
ar
Sm
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om
As t ∞, C is fully charged and is open circuited, fig.6.20
V0 (t → ∞) =
V ( ARi − R0 ) .c
ld
R0 + R + Ri (1 − A)
or
Dividing by Ri
w
V ( A − R 0 / Ri )
V0 (t → ∞) =
tz
R R0
(1 − A) + +
Ri Ri
ar
Sm
V
V0 (t → ∞) ≈
(1 − A) + R / Ri
Ro is the output resistance which is small and Ri is its input resistance which is large.
R0
∴ is negligible and A ≈ 1
Ri
Equation reduces to
V
∴ e sBootstrap = s (1 − A + R / Ri )
V
R
≅ eS
Ri
If R=Ri, esBootstrap = e S .That is the Bootstrap circuit will not provide any improvement in
linearity. For this sweep to be linear Ri >>R
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Transistor Miller Sweep: Consider the working of the triggered transistor Miller’s
sweep generator as shown below.
om
Fig. Transistor Miller sweep
.c
The circuit conditions are adjusted such that when the input is zero Q1 is ON and is in
ld
saturation. Therefore the voltage at C1 (collector of Q1) is VCE (sat ) ≈0. Transistor Q2 is
or
OFF since VBE 2 ≈ 0 . The voltage at C 2 (collector of Q2) is VCC .
The voltage across the capacitor C s is VCC . When the input signal goes negative, Q1 is
w
OFF and the voltage at C1 rises and Q2 goes ON. The charge on the capacitor C s
tz
discharges. Hence the output is a negative going ramp. Again at the end of the input
ar
pulse,Q1 goes ON,Q2 goes OFF and the output again reaches VCC . The waveforms are
shown in fig
Sm
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om
Fig. Bootstrap sweep generator
.c
At t = 0, the switch S is open and the capacitor charges. C1 is very large. Therefore, it is
assumed that the voltage across C1 remains unaltered during the sweep period. Let the
ld
voltage gain of the emitter follower remain constant. Then the voltage at P2 (output of the
or
emitter follower) follows P1 (input of the emitter follower). The voltage between P2 and
P1 will remain invariant and the current i R through R is constant .As the capacitor charges
w
1
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The ramp is generated across capacitor C1 which is charged from the current through R1 .
The discharge transistor Q1 when ON keeps the V1 at VCE (sat ) until a negative input
pulse is applied. Q2 is an emitter follower with low output resistance. Emitter resistance
Re is connected to a negative supply VEE instead of referencing to ground to ensure that
Q2 remains conducting even when its base voltage V1 is close to ground. Capacitor C3 ,
called bootstrapping capacitance, has a much higher capacitance than C1 . C3 is meant to
maintain a constant voltage across R1 and thus maintain the charging current constant.
Quiescent conditions:
om
.c
ld
or
w
tz
ar
Sm
As long as the input trigger signal is zero, Q1 has sufficient base current . So Q2 goes into
saturation. Therefore the voltage V1 across the capacitor C1 is VCE(sat).
V1 = VCE(sat)
2
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V0 = V1 – VBE2
= which is very less
For all practical purposes both V1 and Vo are zero. The voltage across R1 is
VR1 = VCC – VD1 – VCE(sat) ≈ VCC
Also, the voltage across C3 is VC3 ≈ VCC.
V
Hence the current I1 in R1 is I 1 = CC
R1
As the base current of Q2 is smaller than the collector current of Q1
V V
iC1 ≈ I 1 = CC and I B1 = CC
R1 RB
For Q1 to be in saturation, iB1(sat) > iB1(active)
V V
∴ CC > CC , or RB < hFER1
RB hFE R1
Sweep generation:
om
At t=0, when voltage at the base of Q1 goes negative, Q1 is OFF. There is no current into
the collector lead of Q1 and instead this current flows through C1 charging it. As the
i
voltage across the capacitor C1 varies as
C .c
t and so does the output.
ld
V t
V0 = CC .
R1 C 1
or
When the sweep starts, D1 is reverse biased and is an open circuit. The changing current
w
(Tg) is small so that in this period V0 does not reach VCC. However , if Tg is large, the
ar
output V0 may reach VCC even before Tg. When V0 = VCC, the voltage VCE2 of Q2 is
practically zero (saturation). Q2 no longer behaves as an emitter follower. V0 and V1
Sm
V
therefore remain at VCC. The current CC now flows through C3, R1 and through the base
R1
emitter diode of Q2.therby changing voltage across C3 by a small amount (∆V).
If Ts < Tg (ie V0 reaches VCC before Tg)
Then at t = Ts, Vs = VCC
V T
Hence VCC = CC s , or Ts = RC
RC
On the otherhand if Vs < VCC, the maximum ramp voltage is
VCC Tg
Vs =
RC
3
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VCC
iC1 = hFE .
RB
The current iR1 through R1 and the discharging current ia of C1 now constitute iC1,
neglecting the small base current of Q2
iC1 = iR1 + ia and
V
iR1 remains approximately at CC and the capacitor discharges with a constant current ia
R1
The voltage across C1 falls, and consequently Vo falls since once again Q2 behaves as an
emitter follower.
om
The discharge current id from above equation is
ia = iC1 – iR1
h V V
ia = FE CC − CC
RB R1 .c
ld
Therefore V1 and V0 fall linearly to the initial value.The voltage variation during the
retrace time Tr is
or
i T CV
VS = d r , therefore ∴ Tr = 1 s
w
C1 id
tz
V
C1 S
C1Vs VCC
ar
Tr = =
h 1 hFE 1
VCC FE − −
Sm
RB R 1 RB R1
.
4
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om
.c
ld
or
w
tz
ar
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om
.c
ld
or
The gating waveform VB operates between two levels. The lower level keeps the
transistor in cut off while the upper level drives the transistor into saturation.
ar
As long as the input is negative Q1 is biased OFF and the inductor current is zero. At
Sm
t=0+ as the input goes positive Q1 is driven into saturation. The current i L increases
linearly with time. During the sweep period the diode D does not conduct since it is
reverse-biased. The sweep terminates at t = TS when the trigger signal drives the
transistor to cut off. The inductor current then continues to flow through the diode D and
the resistance Rd till it decays to zero. This decay is exponential with a time constant
L
τ= where Rd is the sum of the damping resistance and the diode forward resistance.
Rd
The inductor current attains a maximum value of I L in fig b.
Before the transistor is turned ON, and sometime after it has been turned OFF, VCE = VCC .
When the transistor is ON, VCE = VCE ( sat ) , very low. At t=Ts Q1 is turned OFF.A spike
of amplitude I L Rd appears across the inductance L. This peak voltage must be limited to
make sure that it would not exceed the break down voltage of the collector base
junction. I L is normally chosen on deflection requirements, and a spike of magnitude
I L Rd is generated. Thus there is an upper limit to the size of Rd . The spike decays with
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the same time constant as the inductor current. Thus we see that the spike duration
depends on L, whereas the spike amplitude does not.
So far we have neglected the resistance of the inductor RL and the collector saturation
resistance of the transistor, RCS.
Taking RL and RCS into account
− ( RL + RCS ) t
V CC L
iL = (1 − e )
R L + RCS
Expanding it in to series
VCC + ( RL + R CS )t ( RL + RCS ) 2 t 2
iL ≈ 1 − 1 −
RL + RCS L 2 L2
VCC 1 ( RL + RCS )t
iL = t 1−
L 2 L
IL ( R + RCS ) I L
The slope error es is es = = L
om
VCC /( RL + RCS ) V CC
The current sweep is linear if the slope error is small. Therefore, to ensure linearity the
voltage ( RL + RCS ) I L must be small when compared with the supply voltage VCC .
.c
As this simple current sweep may not produce a linear output, we may think of methods
ld
that help in linearising the sweep. One simple method to produce a linear current sweep is
by adjusting the driving waveform.
or
w
tz
ar
Sm
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om
Fig.c Driving waveform for generating a linear current sweep
Let Rs be the internal resistance of the source Vs. The total circuit resistance
.c
( RS + RL ) .we want the inductor current to vary linearly
i.e. i L = Kt , where K is the constant of proportionality.
ld
If i L = Kt ,then the source voltage VS is
or
di
VS = L L + ( R s + R L )i L
dt
w
di
If i L = Kt , L = K
tz
dt
ar
∴VS = LK + ( R s + R L ) Kt
This waveform consists of a step by followed by a ramp ( Rs + RL ) Kt . Such a waveform
Sm
The waveform of this current source is also a step followed by a ramp, as shown in fig d.
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Thus a trapezoidal driving waveform generates a linear current sweep. At the end of the
sweep the current once again will return to zero exponentially with a time constant
L
τ= .
RS + R L
L
Generally, RS >> RL hence τ ≈
RS
If RS is small the current will decay slowly and a long period will have to elapse before
another sweep is possible. But the advantage is that, the peak voltage developed across
the current source (transistor) will be small.
Alternately, if RS is large, the current will decay rapidly, but a large peak voltage will
appear across the source.
Generally, one has to strike a compromise such that the spike amplitude is not
om
appreciably large and at the time the inductor current decays in a smaller time interval.
To achieve this normally a damping resistance Rd is connected across the yoke to limit
the peak voltage.
.c
Let R be the parallel combination of RS and Rd . Then the retrace time constant is
ld
τr = L/R.
or
Now, how to generate this trapezoidal waveform which when applied as a driving source
will result in the linearity of the current sweep.
w
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Dividing by R 2
R
V (1 + 1 ) − Ve −t /( R1 + R2 )C1
R2
vo =
R1 / R 2 +1
VR
≈ 1 + V − Ve −t / R2C1
R2
VR1
= + V (1 − Ve −t / R2C1 )
R2
R Vt t
v0 = V 1 + (1 − )
R 2 R2 C1 2 R2 C1
t
If << 1
2 R 2 C1
om
R Vt
v0 = V 1 +
R 2 R2 C1
Thus v0 is a step followed by ramp.
.c
ld
or
w
tz
ar
Sm
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om
.c
ld
or
w
tz
ar
Sm
Q1 acts as switch-It is ON when the input zero and is OFF when the input goes
negative.R1,R2 and C1 generate the trapezoidal driving waveform .Q2 and Q3 combination
is a Darlington pair and RE stabilizes iL. The emitter follower provides large input
resistance thus eliminating loading on the driving source by its input. The current iL
1
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waveform
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Here the UJT switch is open so that the capacitor tries to charge to VBB. The moment the
voltage across C reaches VP, the switch closes, allowing the charge on the capacitor C to
discharge almost completely. Again, when the voltage across C reaches VV , the switch
opens, again the capacitor charges. This process is repeated, resulting in a waveform as
shown in fig.above. To synchronize this device with an external signal, the external
signal called the sync signal is connected such that this changes the peak voltageVP. Thus
in a UJT, the sync signal (negative pulse) is applied at B2 to lower VP.
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Consider the situation when the synchronizing pulses are applied. Synchronous pulses
lowers the peak or breakdown voltage for the duration of the pulse. A regularly spaced
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pulse train, having a certain amplitude is shown, starting at t = 0.For the first few cycles
of the sweep generator output, no synchronization is seen to be effected and the sweep
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generator runs at a frequency fo(=1/To) . At time t = T, the negative pulse reduces the
peak and the relaxation device goes ON. From now onwards the sweep generator output
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Thus it observed that the unsynchronized generators run in synchronism after a few
cycles. Synchronization takes place only when the sync pulse occurs at a time when it
would terminate the sweep cycle prematurely. This means that for synchronization to
occur, the interval between the pulses, Tp must be less than the sweep duration T0.
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Here, Tp > T0 and sync pulses occur at such instants that they will not be able to
prematurely terminate the sweep cycle. Hence no synchronization is possible between
these two waveform generators. Obviously, synchronization cannot take place as Tp is
greater than T0.
Consider another situation where Tp < T0, but the amplitude of the sync pulses is small as
shown in fig.
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Though, in the present case, Tp < T0, as the amplitude of the sync pulses is small, they will
ar
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(a) Frequency division by 2.
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Consider fig.(b) where pulses 1 and 2 are not sufficiently large enough to terminate the
cycle. Only when amplitude of the pulse1 is as large as V1 and that for pulse 2, V1' , they
will be able to terminate the cycle prematurely to effect synchronization. However, pulses
marked ‘3’ occur at such an instant and have such a magnitude that they will be able to
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effect synchronization. Hence for every three sync pulses the sweep generator completes
one cycle. Therefore frequency division is said to have occurred by a factor 3.
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or
Fig(b) waveforms
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pulses are applied at the base B1 of Q1.to astable multi shown in fig.(b)
In the absence of sync pulses the astable must have had a time period T0 when
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the cycle would have naturally terminated at V B1 = Vγ , But the 6th pulse prematurely
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terminates the natural cycle as this pulse drives the base of Q1 positive and hence Q1
goes ON. The new time period is TS. Here in this arrangement the multivibrator
completes one cycle for every six sync pulses. However, though the complete period is
synchronized, the individual time periods are not synchronized. T2 is the same as without
synchronization.
Consider Positive pulses applied to B1 through a small capacitor from a low impedance
source. During the period when Q1 is ON, as the time constant of the pulse input is very
small, the pulse is quasi-differentiated. The negative spike is amplified and inverted by
Q1 and this appears as a positive spike during the exponential variation at B2. The positive
spike appearing at the trailing edge of the third input pulse will prematurely terminate the
OFF period of Q2. During the exponential variation of the voltage at B1 the positive
pulses are superimposed and at the leading edge of the sixth pulse, the OFF period of Q1
is prematurely terminated. Thus not only the entire cycle of the astable is synchronized
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with a frequency division of 6:1 but the individual time periods are also synchronized
with a division of 3:1.fig.©
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Fig.c. Synchronization of both portions of an astable multi with positive pulses applied at
B1 through a small capacitor and low impedance source.
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In this case two portions of the multi waveform will be synchronized. In this later case
the counting ratio will change with increasing amplitude of pulse input. If the overshoot
is large enough, the exponential will be terminated by the overshoot at a pulse 2 or pulse
1, in which case the counting ratio will become 3 or 2. Finally, with a large enough
overshoot, the timing portion will terminate at the trailing edge of pulse 4 and the circuit
will not operate as a multi at all.
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terminate at Vpo. This means that the intersection of the sweep voltage with the
waveform Vp must occur, as shown in Fig at the time when V p crosses Vpo, at the points
labeled 0 in the figure. The possibility that the sweep will terminate at the points marked
0' will be considered shortly.)
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In the case of sync-signal period was equal to or less than the natural period.
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Actually a pulse could serve reliably only to terminate a timing cycle prematurely and not
or
to lengthen it, In the present case, synchronization is possible both when T < T0 and
when T > T0 . The timing relationship between the sweep voltage and the breakdown
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voltage for both cases is shown in Fig. The sweep voltage, drawn as a solid line, has a
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natural period T0′ >T. The sweep voltage meets the VP curve at a point below V PO and is
consequently prematurely terminated. The dashed sweep voltage has a natural period
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T0′′< T . this sweep meets the curve at a point above V PO and is consequently lengthened.
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synchronization when T ≠ TO
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the VP waveform. figure illustrates a case (dashed sweep) where the sync amplitude is in
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Figure The sweep circuit used as a counter. Illustrating the change in counting ratio with
sync-signal amplitude.
Principle just large enough to cause 1:1 synchronization. The actual sweep waveform
consists of alternate long and short sweeps.
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Figure Illustrating a possible result of excessive amplitude of the sync signal in a sweep
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Sampling gates
Introduction:
an input waveform during a selected time interval and is zero otherwise. The time
interval for transmission is selected by an externally impressed signal which is called the
gating signal or the control signal. These sampling gates basically of two types, one is
called a unidirectional gate which allows signal of only one polarity to the output
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terminals and the other is a bidirectional gate which allows transmission of both positive
Sampling gate is a transmission circuit that faithfully transmits an input signal to the
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output, but only a for a selected time duration decided by an external signal, called a
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The input appears at the output without distortion but is available for a time duration T
(i) Unidirectional gates: These gates transmit signals of only one polarity.
(ii) Bidirectional gates: These gates transmit bidirectional signals (positive and
negative signals).
Linear gates can use (a) a series switch or (b) a shunt switch fig
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In (a) the switch closes for transmitting the signal whereas in (b) the switch is open
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The gating signal is also known as control pulse, selector pulse or an enabling pulse.
It is a negative signal, the magnitude of which changes abruptly between –V2 and
–V1.
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Consider the instant at which the gate signal is –V1 which is a reasonably large
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negative voltage. Even if an input pulse is present at this time instant, the diode
remains OFF as the input pulse amplitude may not be sufficiently large so as to
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Now consider the duration when the gate signal has a value –V2 and when the input is
also present (coincidence occurs).
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(i) for example, -V1 = -25V, -V2 = -15V and the signal amplitude is 15V.
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The output of the gate changes by adjusting –V2 and in the last case it is seen that the
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output is superimposed on a pedestal of 5V. Thus the output is influenced by the
control signal.
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But, for the gate signal RC network behaves as an integrator. Hence the gate signal is
not necessarily a rectangular pulse but rises and falls with a time constant RC. As a
or
result there is a distortion in gate signal. But if the duration of the input signal is
much smaller than the duration of the gate, the output is a sharp pulse as desired.
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Fig. A unidirectional diode AND gate
When any of the control voltages is at –V1, point X is at a large negative voltage,
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even if the input pulse Vs is present., D0 is reverse biased. Hence there is no signal at
the output.
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When all the control voltages, on the other hand, are at –V2 , if an input signal Vs is
present, D0 is forward biased and the output is a pulse of 5V. Hence this circuit is a
or
Till now we have considered gates that pass only unidirectional signals. Bidirectional
sampling gates transmit bidirectional signals. These gates can be derived using
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diodes, transistors, FETS etc. A single transistor bidirectional sampling gate is shown
in fig.
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The control signal and the input are applied to the base of Q. The control signal is a
pulse whose amplitude varies between V1 and V2 and has a duration tp sufficient
enough for signal transmission. As long as VC is at the lower level V1, Q is OFF and
at the output we have only a dc voltage VCC. However, when VC is at its upper level
V2, Q is ON for the duration tp and if the input signal is present, is amplified and
transmitted to the output with phase inversion but referenced to a dc voltage VdC. At
the end of tp, Q is again OFF and the dc voltage at its collector jumps to VCC. Thus the
signal is transmitted when the gating signal is at V2.
Following figure shows another bidirectional transistor gate where two devices Q1
and Q2 are used and the control signal and the input signal are connected to two
separate bases.
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Let the control voltage be at its upper level, V2 then Q1 is ON and there is sufficient
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emitter current IE1 which results in VEN1 across Re. And if this voltage is sufficient
enough to reverse bias the base emitter diode of Q2, then Q2 is OFF. There is no
signal output. When the gating signal is at its lower level V1, Q1 is OFF and Q2
operates in the active region and can operate as an amplifier and if an input signal is
present, there is an amplified output Vo. Presence of Re increases the input resistance
Ri2 and thus signal source is not loaded.
From the waveforms shown in fig.(b) it is seen that the output is VCC when Q2 is
OFF. When the gating signal drives Q1 OFF and Q2 ON, the dc voltage at the
collector of Q2 falls to Vdc (a voltage smaller than VCC) and during the period of the
gating signal, the signal is amplified by Q2 and is available at the output. Again at the
end of the gating signal Q2 goes OFF and Vo jumps to VCC. Hence the signal is
superimposed on a pedestal.
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Fig. Circuit that minimizes the pedestal
The control signal applied to the base of Q2 is of opposite polarity to that applied to
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the base of Q1. When the gating signal connected to Q1 is negative, Q1 is OFF and at
the same time the gating signal connected to Q2 drives Q2 ON and draws current IC.
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As a result there is a dc voltage Vdc at the collector. But when the gate voltage at the
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base of Q1 drives Q1 ON, Q2 goes OFF. But during this gate period if the input signal
is present, it is amplified and is available at the output, with phase inversion. But the
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If the gating signals are not ideal pulses but have a finite risetime, these may give rise
to spikes in the output.fig.
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Spikes in the output when gating signals are not perfect pulses
If the gate pulse is a large negative voltage when compared to the VBE of the devices
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when in active region, then the base of that transistor is far below cutoff. Now when
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the gate voltage is present Q2 goes OFF before Q1 goes ON. Similarly, at the end of
the gating signal Q1 goes OFF before Q2 goes ON. As a result the gating signals
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themselves give rise to spikes in the output. If the rise time of the gating signal is
large, these spikes are of larger duration where as if the rise time of the gating signal
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is small, these output spikes are of smaller duration. If the rise time of the gating
signal is small when compared to the duration of the gate, these spikes will not cause
distortion of the signal and hence are not objectionable.
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Fig.(a) Bidirectional diode gate
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The above circuit is redrawn in fig.(b)
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When the control signals are at V1, D1 and D2 are OFF, no input signal is transmitted to
the output. But when control signals are at V2, diode D1 conducts if the input is positive
pulses and diode D2 conducts if the input is negative pulses. Hence these bidirectional
inputs are transmitted to the output. This arrangement eliminates pedestal, because of the
circuit symmetry.
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Thevinising the circuit ,fig.(b), at A, the Thevinin voltage source magnitude due to Vs is
(shorting VC source)
R2
Vths = Vs
R1 + R2
= αV s
R2 RR
where α = and Rth = R1 // R2 = 1 2
R1 + R2 R1 + R2
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Similarly, thevinising the circuit in fig.8.16 at B, the Thevinin source due to VC is
(shorting Vs).
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R1
Vthc = VC
or
R1 + R2
R1 R2
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Rthc = R1 // R2 =
R1 + R2
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R2 R1
Vthc = (1 − α )VC = (1 − )VC = VC
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R1 + R2 R1 + R2
Redrawing the circuit and replacing the diode by its linear model we have.
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R3 = Rf
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Vo
Now define the gain of the transmission gate A, as the ratio of during transmission
Vs
period. The control and small diode voltages donot contribute to any current in RL.
R
The open circuit voltage between P and ground is α Vs and the Thevinin resistance is 3 .
2
RL
Vo = αVs
R3
RL +
2
Vo RL
A= =α
Vs R
RL + 3
2
R2
But α =
R1 + R2
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R RL
∴A= ×
R1 + R2 R + R3
L
2
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Minimum control voltage VC(min) required to keep diodes D1 and D2 in forward
or
bias:
Suppose that the signal voltage attains a maximum voltage Vs. Then tthere is a minimum
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control voltage that is required to ensure that both diodes will continue to conduct.
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Consider only gating signals are present. The amplitude and polarity of the gating signals
are such that both the diodes D1 and D2 conduct, and equal currents flow in these two
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diodes. Under such conditions, the net voltage drop is zero and there is no pedestal.
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Let Vs be positive signal. As the amplitude of the signal goes on increasing, the current in
D1 goes on increasing and that in D2 goes on decreasing. As Vs increases further, the
current in D2 becomes zero (i.e. D2 is OFF). Thus there is a minimum control voltage VC
that will keep both the diodes ON. To calculate this VC(min), let D2 be just stopped
conducting i.e. the diode current has become zero, the drop across R3 is zero. Therefore
the output voltage across RL is the open circuit voltage.
Vo when D2 is OFF
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Vo = [αVs − (1 − α )VC ]
Now, calculating the output due to the left hand side signal source Vs and control signal
(1 − α )VC , with the assumption that Vr << Vs (i.e. Vr ≈ 0).
Vo when D1 is ON
RL
Vo = [αVs − (1 − α )VC ]
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RL + R3
Above two equations represent Vo ,hence
[αVs − (1 − α )VC ] RL = αVs − (1 − α )VC
R L + R3
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RL RL
αVs (1 − ) = (1 − α )VC + 1
R L + R3 R L + R3
or
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RL RL
αV s ( ) = (1 − α )VC + 1
RL + R3 RL + R3
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αVs R3 = (1 − α )VC ( R3 + 2 RL )
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R2 R2 R1
α= and 1 − α = 1 − =
R1 + R2 R1 + R2 R1 + R2
R2 R3 R1
Vs = ( R3 + 2 RL ) VC
R1 + R2 R1 + R2
R R3
VC(min) = 2 × Vs
R1 R3 + 2 RL
VC(min) decreases with increasing RL.
Minimum control voltage Vn(min) to ensure that D1 and D2 are off
To calculate the minimum control voltage Vn(min) that is needed to keep D1 and D2 OFF
when no sampling takes place consider the voltage at point P is zero i.e. at ground
potential.
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R2
∴Vn (min) = Vs
R1
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In practice VC(min) and Vn(min) are larger by 25%.
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When the control voltages are VC and –VC, D3 and D4 are reverse biased and are OFF.
Sm
However, D1 and D2 are ON because of +V and –V. The signal is connected to the load
through R2 and the conducting diodes as shown below
When the signal is transmitted, as D3 and D4 are OFF, even if there is a slight imbalance
in the two control voltages +VC and -VC, there is no pedestal at the output.
On the otherhand, when the control voltages are at Vn and –Vn respectively, D3 and D4
conduct. As a result D1 and D2 are OFF. Now the output is zero.
When D3 and D4 are OFF, the circuit is similar to a two diode gate and A is the same
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Also the minimum value of voltage Vmin is the same as VC(min) except for the fact that VC
and –VC are replaced by V and –V.
R1 R3
∴ Vmin = × ×V s
R2 R3 + 2 RL
Calculating the voltage at the cathode of D4 due to sources –V and Vs using the
superposition theorem
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RC R2
∴ Vn (min) = Vs × −V×
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R2 + RC R2 + RC
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other form of four diode gate
When the control signals are VC and -VC, D1,D2,D3 and D4 are ON.
Consider only VC and -VC sources (Vs = 0),
V
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V
In this arrangement, C is the total current and C is the current in each arm.
RC 2 RC
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Now,when considering the signal source Vs only(VC = 0),
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The voltages VC and -VC depend on the amplitude of Vs of the signal, that satisfies the
condition that all the diodes are conducting i.e. current flows in the forward direction.
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The net current in the diodes is due to the sources VC and Vs.
V
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The current in each diode due to the VC sources is C and this is a forward current.
2 RC
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On the otherhand, the current due to Vs source flows in the reverse direction in D3 and
V V V
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R
Rf +
I = I1 × 2
R
Rf + Rf +
2
R
Rf +
V 2
= C ×
RC R
2R f +
2
V 2 ( 2 R f + R)
= C ×
RC 2(4 R f + R )
VC 4 R f + 2 R)
=
(4 R f + R )
2 RC
R
1+
VC 2 R f
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=
2 RC R
1 + 4 R
f
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VC 1
I≈
2 RC R
or
1 + 4 R
f
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V V
I2 = S + S
RC 2 RL
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For VC to be VC(min), the forward current due to VC (I) and the reverse current due to Vs
(I2) must just be equal.
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VS VS VC 1
+ =
RC 2 R L 2 RC R
1 + 4 R
f
VC (min) V V R
= S + S 1 +
2 RC
RC 2 R L 4 R f
R R
VC (min) = 2VS + V S × C 1 +
R L 4 R f
R R
∴ VC (min) = V S 2 + C 1 +
R L 4 R f
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This is similar to the four diode gate shown earlier except that two more diodes D5 and
D6 are included.
During transmission, D5 and D6 are OFF and this six diode gate is equivalent to the four
If the diodes D5 and D6 are remain OFF for a signal amplitude Vs, then
VC(min) = Vs
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The minimum required value of Vn is Vn(min) and is equal to Vs since the transmission
Hence Vn(min) = Vs
Sometimes it becomes necessary to amplify a signal v that has very small dv/dt
and that the amplitude of the signal itself is very small, typically of the order of
millivolts. Neither, ac amplifiers using large coupling condensers nor dc amplifiers with
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the associated drift would be useful for such an application. A chopper stabilized
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LOGIC CIRCUITS
Introduction ;
control or digital communication system a few basic operations are needed. These are
four circuits known as OR, AND, NOT and flip-flop. These are called logic gates or
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Logic System :
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In a de-or level-logic system a bit is implemented as one of two voltage levels as
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shown below.
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In fig (a) more positive voltage is the level 1 and the other is the level 1 and the
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In fig(b) more negative voltage state is represented with 1 and more positive with
of a pulse.
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In a dynamic positive logic system, positive pulse indicates 1 and its absence or
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no pulse signifies 0.
or absence specifies 0.
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OR gate :
The output of an OR assumes 1 state if any one of the inputs assumes 1 state. The
N input logic circuit with output y is represented as shown below. Truth table for 2 input
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In the circuit, since the diodes only are used, it is called diode logic (DL) system.
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Here upper and lower voltages are represented with V (0) and V (1) respectively, it is a
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negative logic system. If all inputs are applied by V (0) , the the voltage across each diode
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is V (0) −V (0) = 0 . Hence no diode is forward biased by at least the cut voltage Vγ and
none of the diode conducts. Therefore the output voltage is V0 = V (0 ) and so the gate is
If one of the inputs, say A, is changed to 1 state and for negative logic system, the
level V (1) makes that diode forward bias. So diode D1 conducts and hence current flows
R
V0 = V (0 )[V (0 ) − V (1) − Vγ ]
R + RS + R f
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V0 = V (1) + Vγ
So the output voltage exceeds the more negative level V (1) by Vγ that means
output voltage is smaller by Vγ than the change in input voltage. If for any reason the
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level V (1) is not identical for all inputs then the most negative value of V (1) (for negative
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logic) appears at the output. A positive logic OR gate can also be designed but this is
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same as above circuit except all diodes must be reversed.
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AND gate :
Definition :
The output an AND assumes the 1 state if and only if all the inputs assume the
1state. A diode (DL) configuration for a negative AND gate is shown below with truth
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To understand the operation simply, assume that all source resistances RS are zero and
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that the diodes are ideal. If any input is at the 0 level V (0) , the diode connected to this
If all the inputs are at the 1 level V (1) , then all diodes are reverse biased and
V0 = V (1) or y = 1 .
can determine the output of the circuit for positive logic system. Assume in inputs out of
n are at V (1) and hence in diodes are reverse biased. The remaining n-m diodes conduct
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and hence the effective circuit of these diodes in parallel consists of (RS + R f ) (n − m ) in
series with a voltage Vγ . Then the output is
R
V0 = V (1) − [V (1) − V (0 ) − Vγ ]
(RS + R f )
R +
n−m
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i.e., V0 = V (0 ) + Vγ
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In the circuit if VR > V (1) , all diodes conduct when all inputs are at V (1) , and the output
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will be clamped to V (1) .
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If VR = V (1) , all diodes are cut off the output impedance is high (equal to R). If
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for any reason all the inputs are not at the same upper level V (1) , then the output will be
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equal V (1)max .
Similarly, if VR < V (1) , and all the inputs are at 1, then all diodes will be cut off
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The NOT logic circuit has a single input and single output. It is defined as the
output of a NOT circuit takes on the 1 state if and only if the input does not take on the 1
state.
The following transistor circuit performs the logic NOT operation in the dc
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If the input is low, Vi = V (0 ) , then the parameters are chosen so that in Q is OFF
When the input is changed to high state i.e., V (1) , then the circuit parameters are
the saturation voltage will be very low i.e., a few tentsa of a volt and that can be
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neglected.
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Problem :
Find the output levels for input levels of 0 and 12V if the silicon transistor shown
below has a minimum value of hFE of 30 .
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Sol. Assume V BEsat = VCEsat = 0V , For Vi = V (0 ) = 0V . The open circuited base votlage
or
VB is
15
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V B = (− 12 ) = −1.56V
15 + 100
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This makes the npn transistor cutoff. Since 0v is adequate for a silicon emitter
junction.
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If we take the actual value of V BEsat & VCEsat as 0.7V & 0.3V respectively for a
silicon transistor, then
12 − 0.3
IC = = 5.31mt ; (I B )min = 5.31 = 0.18mA
2 .2 30
12 − 0.7 0.7 − (− 12 )
I1 = = 0.75mA and I 2 = = 0.13mA
15 100
And I B = 0.75 − 0.13 = 0.62 which is greater than (I B )min
Hence the transistor with these values are also in the saturation region. Hence
V0 = VCE = 0.3V ≅ 0V
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NAND Gate
A negation following an AND gate is called a NOT-AND or NAND gate. A
positive NAND circuit is implemented by a cascade of diode AND and a transistor NOT
as shown in the circuit. Truth table for two input NAND circuit is mentioned.
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Similarly a NOR circuit can also be designed by cascading a diode NOT with a
resistacne OR But the positive NAND gate is same as that of a negative NOR. Thse
NAND and NOR circuits are involving with diodes and transistors, these are also called
In the above DTL configurations, the same can be implemented by omitting the
diodes. Then logic gates are called transistor resistor logic TRL or Resistor-Transistor
Logic RTL. If these resistors are shunted with capacitors then they are called as Resistor-
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Capacitor-Transistor (RCTL) logic circuits.
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this period, V0 = 0. i.e the output is zero for the first quarter cycle since D conducts . The
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input falls after the first quarter cycle. Vi<Vm, the charge on the capacitor. As a result the
diode is reverse biased by a voltage (Vi -Vm). Hence D is OFF .
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∴ V0=Vi - Vm -------- 1
The voltage across C remains unchanged.
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The input to this circuit is a sinusoidal with zero reference level. The output is referenced
to –Vm and the positive peak is clamped to zero.
When the input decreases, to clamp the positive peak to zero level, the voltage across the
capacitor should change to the peak amplitude of the new input. But there is no discharge
path for the capacitor to discharge. For this a resistance R is provided in shunt with the
diode D fig.3
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(c)
At t = t1, if the input amplitude is abruptly reduced, as the voltage across the capacitor
cannot change instantaneously, the positive peaks will not reach zero level. But now as
the charge on C is going to discharge, as the voltage across the capacitor varies
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exponentially with a time constant τ =RC, the output reaches zero level at t = t2, the
positive peak is again clamped to zero, after few cycles.
Fig.5 Output with expanded time scale in the neighborhood of a positive peak
In the vicinity of a positive peak D conducts and at t = t 2' , V0=0. If there were to be no
diode, the output should have followed the dashed line with the peak at t = t2. But
because of the diode, the output in zero from t 2' to t2 and in the subsequent cycles the
positive peaks of the sinusoidal are clamped to zero.
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When the input is applied, the output reaches the steady-state value after a few cycles and
the positive peaks are clamped to zero. consider the equivalent circuits
(i) When the diode is ON, fig.ii) and (ii) When the diode is OFF, Fig.iii)
(i) When the diode is ON
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Fig.ii) Circuit when the diode is ON
As Rf << R, this circuit reduces to
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This circuit, for the purpose of computing the output may be redrawn as fig.iv
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Problem on clamping
To illustrate how the output reaches the steady-state in a negative clamp let us consider a
specific example.
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0.1K
V0(0+) =20V × = 10V
0.1K + 0.1K
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When the input abruptly jumps by 20V, the output jumps by 10V . As the input is
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constant during the period 0 to T/2, the output decays exponentially with the time
constant
τ = (Rf+Rs)C =0.2 × 103 × 1 × 10-6 = 0.2msec
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T/2 = 0.1msec, T = τ
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−T −1
Hence ,V0(T/2) = 10 e 2τ = 10 e 2 = 6V
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At t = T/2, the input falls to 0V, the diode is OFF and the equivalent circuit of Fig.4.8a
is used
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The output falls to -8V suddenly. As the input has remained constant from T/2 to T, the
or
−T
2τ '
V0(T) = -8 e ≈ - 8V
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i.e. the output remains constant. In the interval T/2 to T, as the output has remained
constant, the voltage across the capacitor has remained unchanged. At t = T, the input
abruptly rises to 20V. D is ON, as the voltage across C is 8V, V0 = 6V and in the interval
3T
T to decays.
2
3T
V0 ( ) = 6e-1/2 = 3.6V
2
∴ Voltage across C = 20 – (3.6+3.6) = 12.8V
3T
and t = , V0 = -12.8V
2
3T
As the voltage is not going to change much during the interval to 2T, at t = 2T, the
2
output again returns to 3.6V
5T
At t =
2
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−1
V0 = 3.6 e 2 = 2.2V
∴ VA = 20 – (2.2+2.2) = 15.6V
5T
The output remains at -15.6V during the interval to 3T. This again returns to 2.2V at
2
7T
t = 3T and decays during the interval 3T to
2
−1
7T
V0 ( ) = 2.2 e 2 = 1.32V
2
This procedure is repeated. It is seen that the output reaches the steady-state in a few
cycles. i.e. the positive peaks of the input are clamped to nearly zero level at the output.
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(b) output
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In single diode clipping circuit, the wave form is selected either above or below(but not
on both sides) reference level. Two diode clippers may be used in parallel, series, or
series-parallel to limit the output at two independent levels.
The transfer curve has two break points, one at Vo = Vi = VR1 and a second at Vo = Vi =
VR2 has the following characteristics Vo
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Input voltage Output voltage Diode states
A combination of a positive peak clipper and a negative peak clipper, clipping the input
symmetrically at the top and the bottom is called a limiter.
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Transfer characteristic of a Limiter with input and output
Two avalanche diodes in series opposing, as indicated in fig below constitutes another
or
voltage in the forward direction is Vy, then the transfer characteristic is as shown below.
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Transfer characteristic
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COMPARATORS:
A comparator circuit is one which may be used to mark the instant when an
arbitrary waveform attains some reference level. Consider the simple clipping circuit
for comparison operation.
For the sake of explanation let the input signal be a ramp as shown below.
This input crosses the voltage level vi = VR at time t = t1.
The output remains quiescent at vo = VR until t = t1 after which it rises with the input
signal
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Fig Diode comparator
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There is a sudden change in the slope of the output at the instant the input reaches VR.
But due to ageing and due to temperature variations the diode, may not switch from
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OFF to ON at exactly t = t1 .It may switch state at any instant after t1 and before t2.
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if r = R
∆ Vo R 1
∴
∆ Vi
=
R+R 2
=
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So the improvement is only half.
If a device is connected at the output of the comparator, this is required to be activated
or
when the diode current is say, I and has a drop across R as IR.
If now an amplifier is connected at the output of the comparator so that this amplifier
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Let the amplifier have a gain A. During ∆ t = t2 – t1, the output changes by
∆t (t − t )
or 2 1
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Let the amplifier only amplify the change in the comparator input but not the reference
voltage. The device to be activated is activated only when the drop across R is IR.But
now I = I/A, Hence the device is activated when the drop across R is RI/A since the diode
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current is amplified by A and the diode resistance is r = η VT/I i.e the dynamic resistance
which varies inversely with current. Therefore it is evident that, the device to be activated
by the comparator will respond at a current such that r = RA
∆V o R AR A
∴ =A = =
∆V i r+R R + RA 1 + A
∆V o
As A → ∞, → 1
∆V i
∆V o
Without an amplifier (the transmission gain) was ½ and with an amplifier
∆V i
∆V o
connected , is 1.Which says that there is no marked improvement in the response of
∆V i
the comparator arrangement .
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In the comparator shown before, if VR1 is the reference level in the first
comparator (double differentiator) then a pulse is generated with a peak at t = t1. If
VR2 is the reference level set in a second comparator then the pulse is generated with
peak at t = t2.
Then the time difference between the two pulses is simply
t2 – t1 = (VR2- VR1)/ α
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If a sine wave is applied as input, when the input reaches VR output of the comparator
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is high till again the input reaches VR. Differentiate and clip negative spikes. We have
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(iii) Phase meter: Let two sinusoidal inputs having a phase difference be applied to a
comparator whose reference voltage is zero.
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The output pulses are differentiated and the time difference between the outputs
spikes is proportional to the phase difference.
(iv) Square waves from sine waves: In regenerative comparator (Schmitt trigger) if
the reference voltage is + Vref, the output goes to +V or -V.
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