Generic Built-in Self-Repair Architectures for SoC
Logic Cores
Marcel Balaz, Stefan Kristofik, Maria Fischerova
Institute of Informatics
Slovak Academy of Sciences
Bratislava, Slovak Republic
E-mail: {marcel.balaz, stefan.kristofik, maria.fischerova}@savba.sk
Abstract—The built-in self-repair (BISR) concept is utilized
and proven by industry mainly in regular structures of system-
on-chips (SoCs) memory cores. On the other hand, the idea of
self repair concept for logic cores introduced and developed in
several papers is relatively new, as the irregular structure of
these types of cores represents a serious limitation. However,
there is a need of a complex BISR architecture that can be
widely used on different types of logic cores in order to support
further the reliability of SoCs. This paper presents a generic
BISR architecture based on reconfigurable logic blocks (RLBs)
applicable for any logic core inside a SoC together with in detail
defined basic requirements guiding the architecture development
and also algorithms handling fault detection and localization
procedure.
Index Terms—built-in self-repair, reconfigurable logic, logic
core, system-on-chip, reliability.
I. I NTRODUCTION
Regarding predictions and experiences with complex
system-on-chips (SoCs) reliability has become important and
self repair is required for manufacturing long time dependable
systems [1], [2]. Dominant silicon area of these days SoCs
is represented by memory cores of different types; therefore
investigation and development during the last decade were
mostly targeted to improve the reliability of these cores [3].
Several redundant design methods by means of duplicate
elements are widely used to detect and repair the variety of
fault types by early discovering and substituting faulty memory
elements with the backup elements. However, other types of
cores should not be neglected neither in order to guarantee the
fault tolerant behavior of the whole SoCs. Defects occurring in
logic cores caused by new technologies are also very important
to be handled. Logic cores with the ability of self-repair offer
the opportunity to target these issues.
In order to support the reliability of SoC also from the
perspective of logic cores fully automated methods and generic
architectures are required, though, the random (irregular)
structure of logic cores raises the complexity of built-in self-
repair (BISR) to much higher levels than memory elements.
Several papers have presented basic principles, suggestions
for BISR architecture design or dealt with core’s specific
implementation of ad hoc methods.
In this paper a generic BISR architecture for logic cores
is presented. The main motivation was to provide capability
for improving reliability parameters of any logic core inside
978-1-4799-4558-0/14/$31.00 ©2014 IEEE
SoCs. The work identifies four basic requirements which guide
a core design development of the BISR architecture with
minimal area overhead that could be implemented in any
logic core. Moreover, four algorithms that are able to handle
fault detection and localization procedure were proposed. Each
algorithm aims at fulfilling different goals; therefore variety of
usage is covered with the proposed architecture.
The rest of the paper is organized as follows. Section II
contains the related work. Section III introduces a set of
requirements to achieve feasible reliability characteristics of
the generic BISR architecture, together with algorithms driv-
ing a fault detection and localization procedure. Section IV
summarizes the achieved results and Section V concludes the
paper.
II. R ELATED WORK
The BISR principle for logic cores was published in [4].
The logic core gains BISR capabilities by transforming it
into several reconfigurable logic blocks (RLBs). The RLB
ensures the repair of the assigned part of the logic core. The
assigned part consists of identical functional blocks (FBs)
for which a backup block (BB) with the same function is
added to the RLB. One BB is considered for several identical
FBs in order to reduce the area overhead. The most common
configuration is 3+1 - three FBs and one BB. If one of the
FBs becomes faulty then all inputs and outputs of the block
will be redirected to the BB, so that BB replaces the faulty
FB, i.e. the logic core is repaired by partial reconfiguration.
The replacement and isolation of the faulty FB is performed
by the switches assigned to each input and output port of
the FB. The given RLB should also contain some simple
controller for storing the current block configuration (which
FB is faulty or, otherwise, all FBs are fault-free) and to
drive control signals for switches. The test generation, test
response evaluation and reconfiguration are governed by the
global control unit [4]. Analogy between BISR of logic cores
and memory cores can be found easily. Rows/columns of the
memory matrix can be interpreted as FBs and the backup
row/column (assigned to several rows/columns) as the BB.
However, the random (irregular) structure of logic cores makes
the implementation of BISR capabilities more difficult. This
is the main reason why only ad hoc methods exist in this area
and the BISR architecture was introduced only for specific
cores [5]–[7] and not as a generic architecture. Research was
conducted to estimate the reliability of BISR architectures
(considered again in the context of superscalar processors) [8].
The published estimation is based on the chip area occupied
by BBs and switching elements (ratio to the chip area without
backup is computed). Various results are offered with different
reliabilities and area overheads (the selection can be made
based on the preferences between architectures with higher
reliability or smaller area overhead).
There are only two known works conducted to analyze the
structure of random logic cores [9], [10]. The first work [9] has
assigned into FBs most of the logic gates of the benchmark
circuits. The search was guided by the assumption that bigger
FBs will probably result in better BISR architectures (with
better reliability and smaller area overhead). However, the
impact of unassigned logic gates on the BISR architecture
was not investigated. The second work [10] is automatic
generation of BISR architectures for random logic cores where
the generation based on the genetic algorithm is guided by two
key characteristics of the core: mean time to failure and area
overhead. It presents the fully automated handling of arbitrary
random logic cores and the possibility to generate architectures
based on various BISR principles. The achieved average size
of FBs is low (10 — 20 transistors) due to assumption to
assign each logic gate into RLB and the relative complexity
of benchmark circuits. The ideal FB size is not exactly set. It
vary with the structure of the circuit and should be set to find
feasible ratio between additional area overhead and desired
reliability.
The area overhead is a very crucial characteristic of BISR
architecture. The previously predicted 250 – 300% [11] of
BISR architecture overhead is much closer to real experiments.
The cores with area overhead close to and beyond the 300%
has just marginal improvements in reliability parameters, and
sometimes the reliability could be worse than reliability of the
original core without the BISR architecture applied. Therefore,
BISR architecture should be designed in a manner to get the
smallest possible additional area and with a set of requirements
to ensure such a low area overhead.
III. BISR ARCHITECTURE REQUIREMENTS AND PROPOSAL
The repair function of a logic core architecture based on
BISR principles is achieved by employing a RLB structure [4],
[11]. Recent published works give overview about basics of
this structure. On the other hand, there is no standardized
RLB architecture, no requirements set for its control, and the
number of FBs and BBs inside RLB can vary (e.g. 3+1, 1+1,
2+1). The principal RLB structure includes testing ports but
no testing architecture nor principle are described. The BISR
circuitry besides the RLBs is not mentioned at all.
A. Architecture requirements
To build a logic core with BISR capabilities fundamental
requirements have to be set to design the core provided by
an advantageous self repair function. The new generic BISR
architecture presented in this paper was developed to meet
Figure 1: TG and its logic level carry-over
Figure 2: Two-transistor switch [4]
four introduced requirements for architecture designers with a
strong focus on the size of the additional area.
Requirement 1. RLB switches which performed reconfigura-
tion inside RLB should be implemented by transmission gates
(TGs) or their functional equivalents.
TG is composed of two transistors and designed to carry
properly both logic values (Figure 1) [12]. Usage of TGs
is more recommended than usage of simple two-transistor
switches from the RLB structure described in [4] (Figure 2),
since those can cause 30% signal level degradation on output
for one of the logic values (depends whether PMOS or NMOS
transistors are used) [12]. Two TGs are required for one bit
switch that means four transistors are needed (compared to
two transistors originally needed), however the proposed RLB
structure does not cause any signal loss and does not degrade
functional performance of the core. Switches on functional
inputs behave like a demultiplexer and switches on functional
outputs like a multiplexer. In each FB, one input switch is
needed for each input bit and one output switch is needed for
each output bit. For example, the configuration RLB3+1 with
3 input bits and 2 output bits per FB needs a total of 9 input
switches and 6 output switches. The proposed RLB structure
is shown in Figure 3. To simplify the figure FBs are depicted
with one input and one output bit.
Requirement 2. The BISR architecture should only contain
RLBs with structure 3+1 or 1+1.
RLB3+1 (Figure 3) has 4 possible states of input and output
switches (Table I). RLB state 0 is fault-free state, where all
three FBs are used. In RLB states 1, 2 and 3 one of the FBs
is faulty, therefore a BB has to be employed. Analogically,
RLB1+1 has 2 states: A fault-free state 0 and a state where
a faulty FB is substituted by a BB. Maximum number of
repairable blocks in both types of RLB is 1. All RLBs are
controlled by the BISR controller by dedicated control signal
for each RLB. The requirement 2 narrows down the RLB
structures due to their numbers of states (4 and 2 respectively).
 c1 c2 c3

Reconfigurable logic blocks (RLBs) were introduced in [1]. This architecture enables fault isolation by using
RLB3+1
switching elements at both inputs and outputs. RLB consists of a number of identical functional blocks (FB) with
c1 c1
one of them FB1set up as backup block (BB).
FB1 In case any FB is faulty, BB can substitute its functionality. Maximum
FB
number of repairable blocks1 in each RLB is 1. Repair function cannot be guaranteed when more FBs are faulty.
I1 O1
!c 1 !c1
BB BB

c1 c1
D
SET
Q
c2 c2
FB2 FB2
FB2 rst Q
CLR

I2 O2
!c2 !c2
BB BB

c2 c2 D
SET
Q
c3 c3
FB3 FB3
FB3 CLR Q
rst

I3 O3
!c3 !c3
BB BB
BB (a) (b)
c3 (c) c3
cvm rst*

Fig. 1. (a) RLB 3+1 architecture, (b) input switch, (c) output switch.
c1-c3 c1-c3 Figure 4: State controller – RLB control logic
state controller
We use RLB architecture with 3 functional blocks (FB1, FB2 and FB3) and 1 backup block (BB), i.e. RLB 3+1,
which is shown in Fig. 1 (a). RLB
cv RLB 3+1 has 4 logic states as is shown in
Requirement Table
1
4. Testing RLB
I. In state 0,2 backup
should RLBn
block is
be performed on a core as a
unused, whereas in states 1, 2 and 3, backup
Figure 3: RLB of structure 3+1 block is used instead
whole. of FB1, FB2 and FB3, respectively.
I1 FBs O1 I2 FBs O2 In FBs On
The aimBBof the requirement BB is to simplify the BB entire repair
Table I. States of RLB 3+1
Table I: States of RLB 3+1
procedure and consequently to reduce area overhead. In re-
c c c c c c c c c
RLB Control bits spect to low area overhead the proposed
1 2 3 1
. . . RLB does not contain
2 3 1 2 3

FB1 FB2 FB3 BB test inputs SC and outputs forSCBB testing. The regular testing of
state c1 c2 c3 SC
0 used used used unused 0 0 0 the core is performed as for the core without repair capability.
1 unused used used used 1 0 0 The BISR cv 1 logic shouldcvbe able to start thecvtest and to get the
2 n

2 used unused used used 0 1 0

3 used used unused used 0 0 1
test result: faulty or non-faulty. Testing is performed several
times on variousB configurations
B of RLBs, which B can detect,
1
. . .
2 n

localize and isolate

Input and output switches can be implemented using tri-state buffers as is shown in Fig. 1 (b) and (c), arisen faults. Detailed explanation of the
If RLBs test and repair procedure
respectively. Input switches determine which triple of functional blocks is used. Output switches determine
with variety of state numbers are allowed, complexity is given in Subsection III-C.
of theoutputs
controloflogic willtriple
which be higher and consequently
of functional the area
blocks are routed to theB.outputs
Generic of the
BISRRLB.
v(1) v(2) Behavior
. . . v(n) of the switches is
architecture
overhead will grow. The BISR control logic is explained
shown in Table II. If a block is unused, its inputs are driven toThe in highbasic
impedance v(1..n)
and its outputs rst save
and the most crucial are
partignored
of the by the
proposed BISR
detailsoutput
later in Subsection
switch. III-B. Fault detection/localization procedure
architecture is a RLB design according to four architectural
BISR controller
Requirement 3. RLBs should have only one control input, requirements. The go_nogo
proposed RLB architecture is depicted in
which Table
switches between
II. Input allswitch
and output fourbehavior
(for 3+1 structure) or two Figure 3. The number of RLBs present in the core is not
result_valid
test_enable
(1+1 structure)input RLBswitch
states. output switch limited, moreover the number is a very specific parameter of
control input to_FB to_BB control from_FB from_BB output
each BISR realization and a proper structural analysis of the
The state
0 controller
0 0 (SC) Z of each0 RLB holds 0 the Xstate 0
0 1 the RLB1 Z 0 The function
1 core
1 should precede [10] (the structural analysis of logic cores
which determines configuration. ofX the
1 0 Z 0 1 X 0 is0 beyond the scope of the paper).
circuitry1is shown 1
in Figure
Z
4. 1A change 1
of the Xstate is driven
1 1 If a fault occurs in RLB3+1 , it has to be localized, i.e. a
by signal cv from the BISR control
Z – high impedance, X – don't care logic in a cyclic order.
faulty FB has to be identified and replaced. Assuming that the
State 0 is followed by state 1, 2, 3 and state 0 again. Logic
RLB was in state 0, i.e. a BB was unused, faulty FB detection
value In
0 iseach
present on signal
FB, one cv during
input switch the functional
is needed phasebit
for each input of and one output switch is needed for each output bit. For
is performed in several steps. First, the RLB is switched to
the core. When the state change is required short impulse of
example, in the RLB 3+1 setting, if the FB has 3 input bits and state2 1output
and thebits,core
a total of 9 input
is tested. switches
If the RLB isand no6longer faulty,
logic 1 appears on the signal which switches to the consecutive
output switches will be needed. Input and output
state by driving signals c1 , c2 and c3 according to Table I. The
switches operate
FB1 is based on
the faulty the values
block andofthethenew
control signals.
fault-free A of the RLB
state
total of 3 control signal bits are needed to switch between is states
the 1. If, of
however,
RLB the State
3+1. RLB switching
is still faulty,
is its state is switched
done
circuitry could contain optional synchronous reset signal (rst)
to cstate 2 and tested again. If the RLB is no longer faulty, it
whichaccording
sets the RLB to theinto
Table I. Asserting
state 0. The reset control
signal signals , c2 b and
couldc1save 3 disconnects FB1, FB2 and FB3 blocks,
respectively, and connects the BB block indicates that FB2 is the faulty block and the new fault-free
the time of reconfiguration in cases when onlyinstead.
one particular
state of the RLB is 2. If, however, the RLB is still faulty,
state needs to be tested in all RLBs.
its state is switched to 3 and tested for faults once more. If
If a fault is detected in RLB 3+1, it has to be localized, i.e. failing FB has to be identified. Assuming that the
RLB was in state 0, i.e. BB was unused, faulty FB detection can be done in several steps. First, RLB is switched
to state 1 and tested for faults. If RLB is no longer faulty, FB1 is the failing block and the new fault-free state of
 cvm RLB1 RLB2 RLBn

I1 FBs O1 I2 FBs O2 In FBs On

BB BB BB

c1 c2 c3 c1 c2 c3 c1 c2 c3
. . .

D
SET
Q SC SC SC

rst Q
CLR

cv1 cv2 cvn

save v(m) rst*

B1 B2 . . . Bn
Figure 5: Circuitry to preserve repaired state in RLB

Table II: Behavior of the circuitry to preserve repaired state

in RLB v(1) v(2) . . . v(n)
v(1..n) rst save
Current Next Output
v(m) rst save Fault detection/localization procedure
state state cvm
normal  0 0 normal 
normal  0 0 normal 
BISR controller
go_nogo
normal  0 1 normal 0
result_valid
normal  0 1 blocking 0 test_enable
blocking X 0 X blocking 0
blocking X 1 X normal 0 Figure 6: Proposed BISR architecture
 - rising edge,  - falling edge

circuitries (B) and a fault detection/localization procedure

the RLB is no longer faulty, FB3 is the faulty block and the (FDLP) are present. The FDLP unit controls the entire test
new fault-free state of the RLB is 3. If, however, the RLB is and repair process by asserting a control vector v(1..n), signal
still faulty, it may indicate the occurrence of multiple faults save and an optional signal rst. For a state change in RLB1 the
in more than one FB. In that case the repair function of the FDLP unit generates short impulse of logic 1 on signal v(1)
RLB3+1 architecture
[1] Koal, T.,can no longer
Vierhaus, H. T.:be guaranteed.
Built-in Self Repair for Logic Structures.
and for aIn:state
Design and Test Technology
preservation for Dependable
the impulse on v(1) is Systems-on-Chip.
generated IGI Glob
By following the aforementioned faultyVierhaus
10.4018/978-1-60960-212-3.ch010. FB detection
kapitolapro- again with active level on signal save. Notice that only one
cess and considering only one fault is present in RLB, the 1-bit signal save is needed in the proposed BISR architecture.
new fault-free state is identified. To prevent further change, the The FDLP also interfaces with a tester circuitry. When the
state should be blocked and never changed. The function of a core needs to be tested, the FDLP asserts signal test_enable
proposed state blocking circuitry is shown in Figure 5. When and waits for the signal result_valid. While waiting for the
the signal save is inactive, the output signal cvm copies the test results, the repair process is paused. When testing is done,
input control signal v(m). If signal save is active, the circuitry the signal result_valid from a tester is asserted and the result
is switched to preserve an actual state in RLBm on the falling of the test, i.e. whether the system is faulty or fault-free is
edge of the input signal v(m). In the blocking state, output of indicated by the value of signal go_nogo. The tester circuit is
the circuitry (signal cvm ) is set to 0 regardless of the values on expected to finish the test and provide the result in finite time
input ports. The behavior of the circuitry is shown in Table II. or additional error signal could be used to indicate there was
The number of the state blocking circuitries depends on the an error during testing.
number of RLBs present in a core. For each RLB one state The optional signal rst is intended to reset an BISR archi-
blocking circuitry is needed. The circuitry can be reset to tecture to the basic configuration. It sets all RLBs to the state
unblock the RLB state by asserting optional reset signal rst. 0 (all FBs are employed) and resets all blocking circuits to
If the reset signal is implemented in the design its behavior enable propagation of control signals v(1..n) to signals cv1..n .
is synchronous, where signal v(m) is the clock signal. As a
consequence of this design the BISR controller (which drives C. Fault detection/localization procedure
both signals) could reset arbitrary state blocking circuitry by During the functional phase of the core, the BISR architec-
asserting reset signal rst and a relevant signal v(m). ture is inactive. The fault detection and localization procedure
The whole proposed BISR architecture for n RLBs is shown only runs test occasionally on the core to ensure it is fault-free.
in Figure 6. The architecture comprises of n RLBs, each The interval of inactivity could be implemented in different
containing the state controller circuitry (SC) and a BISR ways and is dependent on the function of the core (e.g. if it is
controller. Inside of the BISR controller n state blocking a processor the test could be launched during inactive phase).
 Assume a core with the proposed BISR architecture consist-
ing of multiple RLB3+1 , which is tested for faults as a whole.
If a fault occurs during the occasional test a faulty RLB has
to be identified as well as the faulty FB within the RLB. Fault
detection/localization procedure can be done in different ways.
We have proposed four approaches which can repair one fault
at time:
• Serial approach – takes one RLB at a time and changes
its state. After each change the test must be employed. If
the core is faulty after all four possible states of the RLB
were tested the RLB state is set to 0 and the next RLB is
examined in the same way. This process is repeated until
faulty RLB and faulty FB are identified.
• Parallel approach – changes states of all RLBs at a time
until the core is fault-free.
• Parallel-then-serial approach – consists of two stages.
In the first stage a fault-free state is determined. States
of all RLBs are changed all in once until the core is
fault free. It means that FBs on the same position in all
RLBs are replaced by BB and one of the replaced FBs
is faulty. This fault-free state is marked and all RLBs are
reset to state 0. Consequently, in the second stage of the
approach the faulty FB is going to be localized. All RLBs
are investigated successively, one at a time, but this time
with the marked fault-free state only until the faulty RLB
is identified.
• Partitioning approach – divides RLBs into two halves and
cycles states of the first half until the core is fault-free.
If fault-free state is found, this half is further divided
into two halves and the first one is investigated again.
Dividing and state cycling are repeated until the faulty
RLB and the faulty FB are identified. If fault-free state
was not found by cycling the states of the first half, the
dividing and cycling process is repeated with the second
half until a faulty RLB and a faulty FB are identified.
The serial approach is easy to implement and has small area
overhead, but takes the longest time to detect a faulty FB. It
is also able to repair as many faults as the number of RLBs in
the core. The parallel approach is even easier to implement
and its advantage is the minimal time to detect faulty FB with
even smaller area overhead. However, this approach is unable
to identify the faulty RLB and is able to repair only one fault in
the core. The parallel-then-serial approach is in average faster
than the serial approach, due to the quick first stage which
determines the fault-free state. When RLBs are investigated
independently in the second stage of the approach not all four
states need to be checked. Number of possible repaired faults
in the core is equal to the number of RLBs. The partitioning
approach is difficult to design since it needs logical dividing
the RLB array into smaller partitions. However, it is much
faster in a fault localization than both serial and combined
approaches and also guarantees the repair of the same amount
of faults as the number of RLBs present in the core.
IV. E XPERIMENTAL RESULTS
The proposed architecture was implemented according to
the proposed requirements for cores of various functions with
different numbers of RLBs. For each implementation the core
was divided into the appropriate number of RLBs without
changing the functionality of the core. In all cases testing was
performed by external tester, which was triggered by the BISR
controller. There were two main parameters examined: (1) the
area of the BISR architecture after synthesis as the most crucial
parameter of reliability and (2) the time needed to repair when
a fault occurs.
The additional area A is computed as
n
A = (n × ASC + n × AB + AF DLP ) + si
i=1
where n is the number of RLBs in the core, ASC is the
area of the state controller circuitry SC, AB is the area of the
state blocking circuitry, AFDLP is the area of the FDLP unit
and si represents area of the input and output switches within
RLBi . The area of the BISR architectures with 5 different
numbers of RLBs is shown in Table III. Both ASC and AB are
core independent parameters and for different fault localization
approaches are the same. The area of SC  is 134 transistors and
the area of B is 64 transistors. Columns for all approaches
are the sum of n × ASC , n × AB and AF DLP . It should
be noted that the total area does not include the area nof the
core itself and area of the input and output switches i=1 si .
The parameter si is highly specific for each core and core
partitioning and as the only one could not be formulated
generally. AFDLP is dependent on the number of RLBs and
on the implemented fault localization approach. Although the
areas of all approaches are increasing with the rising number of
RLBs, the increase is linear and not exponential. The Parallel
approach has the smallest area but this approach can repair
only one fault in the core. The serial approach has smaller
area than both the parallel-then-serial and the partitioning
approach. However, the differences are shrinking with the
additional RLBs in the core (e.g. the summary area of the
partitioning approach is 12% higher than serial approach for
32 RLBs compared with 28,5% for 7 RLBs).
The time of the repair as the second parameter is inves-
tigated on all four approaches in the Table IV. There are 9
sizes of BISR architecture with the number of RLBs3+1 from
4 to 32. The columns min. contain the minimal number of
test runs for each approach, the columns max. represent the
maximal number of test runs and avg. represent the average
number of test runs. The parallel approach is the quickest
(with only two test runs in average) and with the minimal area,
however it can repair only one fault in the core. This approach
can be used when the area is the most crucial parameter of
the design. The serial approach takes only one test run to
localize fault in the first FB of the first RLB. The worst case
can be computed as k × n, where n is the number of RLBs
and k the number of FBs in one RLB. The average number
 SC BISR Controller SC BISR Controller 
(n) 
(n × ASC) (n × AB) AFDLP (n × ASC) (n × AB) AFDLP
7 938 448 850 2236 938 448 1184 2570
12 1608 768 982 3358 1608 768 1554 3930
16 2144 1024 1078 4246 2144 1024 1606 4774
24 3216 1536 1172 5924 3216 1536 1800 6552
32 4288 2048 1416 7752 4288 2048 1984 8320
Table III: Experimental results
Transistor count
# of
same for all 4 approaches Serial Parallel Parallel-then-serial Partitioning
RLBs
SC B FDLP FDLP FDLP FDLP
(n)    
(n × ASC) (n × AB) AFDLP AFDLP AFDLP AFDLP
7 938 448 914 2300 456 1842 1284 2670 1570 2956
12 1608 768 1014 3390 456 2832 1380 3756 1780 4156
16 2144 1024 1164 4332 456 3624 1432 4600 1790 4958
24 3216 1536 1244 5996 456 5208 1668 6420 2152 6904
32 4288 2048 1488 7824 456 6792 1872 8208 2428 8764

Table IV: Comparison of number of test launches for proposed localization algorithms
Parallel-then-serial Partitioning
# of Serial approach Parallel approach
approach approach
RLBs # of test runs # of test runs
# of test runs # of test runs
(n)
min. max. avg. min. max. avg. min. max. avg. min. max. avg.
4 1 12 6,5 1 3 2 2 7 4,5 2 8 5
6 1 18 9,5 1 3 2 2 9 5,5 3 9 5,83
7 1 21 11 1 3 2 2 10 6 3 9 5,71
8 1 24 12,5 1 3 2 2 11 6,5 3 9 6
10 1 30 15,5 1 3 2 2 13 7,5 3 9 6,5
12 1 36 18,5 1 3 2 2 15 8,5 4 10 6,83
16 1 48 24,5 1 3 2 2 19 10,5 4 10 7
24 1 72 36,5 1 3 2 2 27 14,5 5 11 7,83
32 1 96 48,5 1 3 2 2 35 18,5 5 11 8

Transistor count
of test runs can be computed # of as
n×k+1
. This
2 Serial approach is
approach Partitioning approach
R EFERENCES
RLBs
suitable for smaller BISR architectures SC where BISRthe time of the
Controller [1] BISR Controller
SC “International technology roadmap for semiconductors, 2012 update,”
(n) 
repair process is not very crucial.(nFor bigger
× ASC ) (n ×architectures
AB) AFDLP last (n × ASC2012,
) (nhttp://www.itrs.net/Links/2012ITRS/Home2012.htm
× AB) AFDLP [Online, ac-
7 938 448
two approaches are more suitable. The parallel-then-serial 850 2236 938 cessed: 448 1184
1.14.2014]. 2570
12 1608 768 982 3358 1608 768
[2] M. L. Shooman, 1554 3930of Computer Systems and Networks: Fault
Reliability
approach has the average 16 number2144 of test 1024runs on level4246
1078 of 2144 Tolerance, 1024Analysis,
1606 and4774
Design. Wiley-Interscience, 2001.
30–40 % of the serial approach24 for bigger 1536
3216 architectures.
1172 5924 The 3216 [3] M. Fischerová
1536 and
1800E. Gramatová,
6552 “Memory testing and self-repair,” in
partitioning approach is not 32 very 4288
suitable 2048 1416 BISR
for smaller 7752 4288 Design2048
and Test1984
Technology
8320 for Dependable Systems-on-Chip, R. Ubar,
J. Raik, and H. T. Vierhaus, Eds. IGI Global, 2011, pp. 155–174, doi:
architectures due to higher area but it is the best solution for 10.4018/978-1-60960-212-3.ch007.
the biggest BISR architectures where repair process needs to Transistor [4] T. Koal,
countD. Scheit, and H. T. Vierhaus, “A concept for logic self repair,”
# of in 12th Euromicro Conf. Digital System Design: Architectures, Methods
be performed quickly. RLBs
same for all 4 approaches Serial Parallel Parallel-then-serial Partitioning
and Tools, DSD 2009, 2009, pp. 621–624, doi: 10.1109/DSD.2009.238.
SC B FDLP FDLP FDLP FDLP
The reliability of the core(n)is highly dependent
(n × ASC)
on
(n × AB)
the addi-
AFDLP
 [5] A. Benso,
AFDLP
 S. Di Carlo, G. Di
AFDLP
 Natale, and P. Prinetto,
AFDLP
 “Online self-repair
tional area and the chosen number of RLBs inside the914core.2300 456 of FIR filters,” IEEE Des. Test, vol. 20, no. 3, pp. 50–57, 2003, doi:
7 938 448 1842 1284 2670 1570 2956
10.1109/MDT.2003.1198686.
Therefore the reliability improvement
12 could not768
1608 be investigated
1014 3390 456 2832 1380 3756 1780 4156
[6] T. Koal and H. T. Vierhaus, “A software-based self-test and hardware
16 2144 1024
on the generic architecture. However, all our implementations 1164 4332 456 3624 1432 4600 1790 4958
reconfiguration solution for VLIW processors,” in 13th IEEE Int. Symp.
24 3216 1536 1244 5996 456
have 100 – 200 % overhead which is noticeably lower than Design5208 1668
and Diagnostics 6420 2152 6904
of Electronic Circuits and Systems, DDECS
32 4288 2048 1488 7824 456
2010, 6792
2010, pp.1872 8208
40–43, doi: 2428 8764
10.1109/DDECS.2010.5491821.
the previously predicted 250 – 300% [11]. [7] M. Ulbricht, M. Schölzel, T. Koal, and H. T. Vierhaus, “A new
hierarchical built-in self-test with on-chip diagnosis for VLIW pro-
cessors,” in 14th IEEE Int. Symp. Design and Diagnostics of Elec-
V. C ONCLUSION tronic Circuits and Systems, DDECS 2011, 2011, pp. 143–146, doi:
10.1109/DDECS.2011.5783067.
[8] T. Koal and H. T. Vierhaus, “Optimal spare utilization for reliability and
The generic BISR architecture for logic cores was presented mean lifetime improvement of logic built-in self-repair,” in 14th IEEE
Int. Symp. Design and Diagnostics of Electronic Circuits and Systems,
in the paper. The main motivation was to provide possibility DDECS 2011, 2011, pp. 219–224, doi: 10.1109/DDECS.2011.5783083.
to improve reliability parameters for any logic core inside a [9] C. Gleichner, T. Koal, and H. T. Vierhaus, “Effective logic self repair
SoC. The four basic requirements, which guide a core designer based on extracted logic clusters,” in 14th IEEE Conf. Signal Processing:
Algorithms, Architectures, Arrangements, and Applications, SPA 2010,
to develop a simple BISR architecture with minimal area 2010, pp. 10–15.
overhead implementable for any logic core were proposed. [10] R. Dobai, M. Balaz, and M. Fischerova, “Automated generation of built-
Moreover, four simple algorithms to handle the fault detection in self-repair architectures for random logic soc cores,” in Digital System
Design (DSD), 2012 15th Euromicro Conference on, 2012, pp. 73–78,
and localization procedure were presented. Each algorithm doi: 10.1109/DSD.2012.29.
aims to fulfill different goals, therefore the proposed architec- [11] T. Koal and H. T. Vierhaus, “Built-in self repair for logic structures,” in
ture can be implemented in a variety of cores with different Design and Test Technology for Dependable Systems-on-Chip, R. Ubar,
J. Raik, and H. T. Vierhaus, Eds. IGI Global, 2011, pp. 216–240, doi:
design restrictions. 10.4018/978-1-60960-212-3.ch010.
This work has been supported by Slovak national project [12] R. J. Baker, CMOS Circuit Design, Layout, and Simulation, 3rd ed.
VEGA 2/0034/12. Wiley-IEEE Press, 2010.