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Field Effect Transistors PDF
Field Effect Transistors PDF
BJTs
Similarities:
• Amplifiers
• Switching devices
• Impedance matching circuits
1
FETs vs. BJTs
Differences:
• FETs are voltage controlled devices. BJTs are
current (IB) controlled devices.
2
FETs vs. BJTs
Differences:
• FETs have a higher input impedance. BJTs
have higher gains.
• FETs are less sensitive to temperature
variations and are more easily integrated on ICs.
3
The Term FETs
In FET, the electric field is established by the
charges present, which controls the conduction
path of the output circuit without the need for
direct contact between the controlling and
controlled quantities.
4
FET Types
5
JFET Construction
There are two types of JFETs
7
JFET Operation: The Basic Idea
8
JFET Operating Characteristics
9
JFET Operating Characteristics
10
JFET Operating Characteristics
Case-1: VGS=0 V and VDS has some positive value
11
JFET Operating Characteristics: VGS = 0 V
Three things happen when VGS = 0 and VDS is increased from 0 to a more positive voltage
12
JFET Operating Characteristics:
Characteristics: Saturation
13
JFET Operating Characteristics: Pinch Off
14
JFET Operating Characteristics:
Characteristics: Saturation
At the pinch-off point:
ID is at saturation or maximum. It is
referred to as IDSS - Drain to Source
Current with Source Shorted with
Gate.
15
Effect on JFET Cht. due to level of VGS
Case-2: VGS< 0 V and VDS has some positive value
For n-channel device, the controlling voltage VGS is
made more and more negative from its VGS =0 V.
16
JFET Operating Characteristics
VGS Controls ID
As VGS becomes more negative:
17
JFET Operating Characteristics
VGS Controls ID
• The level of VGS that
results in ID =0 mA is
defined by VGS = Vp with
VP being a negative
voltage for n-channel
devices and a positive
voltage for p-channel
JFETs.
18
JFET Operating Characteristics
Also note that at high levels VGS Controls ID
of VDS the JFET reaches a
breakdown situation. ID
increases uncontrollably if
VDS > VDSmax. (Breakdown
Region)
19
JFET Operating Characteristics:
Voltage--Controlled Resistor
Voltage
The region to the left of the pinch-
off point is called the Ohmic region
or voltage controlled resistor region.
region.
ro
rd =
2
V GS
1 −
V P
r0 is the resistance with VGS=0 V
rd is the resistance at particular VGS
20
N-Channel JFET Symbol
21
p-Channel JFETS
The p-channel JFET behaves the same as
the n-channel JFET, except the voltage
polarities and current directions are
reversed.
22
p-Channel JFET Characteristics
23
JFET Transfer Characteristics
Transfer Characteristics of FET is the Plot of Drain Current versus Gate – Source
Voltage for a fixed Drain - Source Voltage, beyond Ohmic Region.
24
JFET Transfer Curve
This graph shows the value of ID
for a given value of VGS.
25
Plotting the JFET Transfer Curve
Using IDSS and Vp (VGS(off)) values found in a specification sheet, the transfer
curve can be plotted according to these three steps:
Step 1
2
V
I D = I DSS 1 − GS
VP
Solving for VGS = 0V ID = IDSS
Step 2
2
V
I D = I DSS 1 − GS
VP
Solving for VGS = Vp (VGS(off)) ID = 0A
Step 3
2
V
Solving for VGS = 0V to Vp I D = I DSS 1 − GS
VP
26
For a given IDSS and VP in Datasheet, ID can be
found for any value of VGS
Shorthand Method: Four Points using Shockley's
equation to quickly draw the transfer characteristics
curve
2
V GS
I D = I DSS 1 −
V P
Common FET Biasing Circuits
• Fixed – Bias
• Self-Bias
• Voltage-Divider Bias
28
Basic Current Relationships
For all FETs:
• Device Specific Equations.
IG ≅ 0A • Do not alter so long device
ID = IS is in Active Region
• Graphical approach will be
For JFETS and D-Type MOSFETs:
used to examine the dc
analysis for FET because it
2
V is most popularly used
I D = I DSS 1 − GS
VP rather than mathematical
approach
For E-Type MOSFETs:
I D = k ( VGS − VT ) 2
29
Fixed Bias Configuration
The configuration includes the ac levels Vi and Vo and
the coupling capacitors.
The resistor is present to ensure that Vi appears at the
input to the FET amplifier for the AC analysis.
Fixed Bias Configuration
For the DC analysis,
Capacitors are open circuits
IG ≅ 0A and V RG = I G R G = ( 0 A ) R G = 0V
The zero-volt drop across RG permits replacing RG by a short-circuit
Fixed Bias Configuration
V GS 2
I D = I DSS (1 − )
VP
Fixed Bias Configuration
• Using Graphical Method Draw the Graph of
Transfer Characteristics.
• The fixed level of VGS has been
superimposed as a vertical line a VGS=-VGG
• At any point on the vertical line, the level of
VG is –VGG the level of ID must simply be
determined on this vertical line.
• The point where the two curves intersect is
the common solution to the configuration –
commonly referrers to as the quiescent or
operating point.
• The quiescent level of ID is determine by
drawing a horizontal line from the Q-point to
the vertical ID axis.
33
Fixed--Bias Configuration
Fixed
Output Loop
VDS = VDD − I D RD VDS = VD − VS
VS = 0V
VD = VDS VGS = VG − VS
VG = VGS
VGS = −VGG
Example: For a given Fixed Bias Configuration,
Determine VGSQ, IDQ, VDS, VD, VG and VS
37
Self--Bias Configuration
Self
Gate Resistor RG does not affect the bias
because it has essentially no voltage drop
across it; Hence VG = 0;
Mathematical Approach
VS = ISRS = IDRS
VGS = VG – VS = 0 – IDRS
VGS = – IDRS
VD = VDD – IDRD
VDS = VD – VS
2
V VDS = VDD – IDRD – IDRS
I D = I DSS 1 − GS VDS = VDD – ID (RD + RS)
VP
2
I D RS
I D = I DSS 1 +
VP
2
I D + K1I D + K 2 = 0 38
Self--Bias Configuration –Q Point
Self
39
Self--Bias Configuration – Finding RS for
Self
desired Q Point
40
Self--Bias Configuration – Finding RS for
Self
desired Q Point
41
Self--Bias Configuration
Self
• Graphical approach to get Q Point for Given Value
of Rs
– Draw the device transfer characteristic
– Draw the network load line
VGS = −I D RS
• Use to draw straight line.
I D = 0, VGS = 0
• First point,
• Second point, any pointI from ID = 0 to ID = IDSS. Choose
DSS
ID = then
2
I DSS RS
VGS = −
2
44
Self--Bias Calculations
Self
iD (mA)
VGS = − I D R S iDSS = 10
When ID = 0
5.07
When ID = IDSS
0
Determine Q Point
46
Example: Determine VGSQ, IDQ,VDS,VS,VG and VD.
• Take ID = 0 mA and ID=4 mA
• Calculate VGS= - IDRS
• Draw Load Line Connecting two points.
• Use Shorthand Method and draw transfer
curve.
• Intersection of Transfer Curve and Load Line
gives the Q Point for the given network.
Voltage--Divider Bias
Voltage
• IG = 0 A
• ID responds to changes in VGS.
• The arrangement is the same as BJT but the DC analysis is different
• In BJT, IB provide link to input and output circuit, in FET VGS does the
same
Voltage--Divider Bias Calculations
Voltage
All Capacitors are replaced with open circuit for DC Analysis.
• The source VDD is separated into two
equivalent sources to permit a further
separation of the input and output regions of
the network.
• IG = 0A ,Kirchhoff's current law requires that
IR1= IR2 and the series equivalent circuit
appearing to the left of the figure can be used
to find the level of VG.
• The voltage VG, equal to the voltage across
R2, can be found using the voltage divider rule
as follows: R V
2 DD
VG =
R1 + R 2
Using Kirchhoff’s Law:
VG – VGS – VRS = 0 The Q point is established by plotting a line that
So, VGS = VG -VRS intersects the transfer curve.
V GS = V G − I D R S
49
Voltage--Divider Q-
Voltage Q-point
V GS = V G − I D R S
Step 1
Plot the line by plotting two points:
•VGS = VG, ID = 0 A
•VGS = 0 V, ID = VG / RS
Step 2
Plot the transfer curve by plotting
IDSS, VP and the calculated values
of ID
Step 3
The Q-point is located where the
line intersects the transfer curve
50
Voltage--Divider Bias Calculations
Voltage
Using the value of ID at the Q-point, solve for the other variables in the voltage-
divider bias circuit:
VDS = VDD − I D (R D + R S )
VD = VDD − I D R D
VS = I D R S
VDD
I R1 = I R2 =
R1 + R 2
51
Voltage--Divider Bias Calculations
Voltage
ID = (VDD – VD) / RD
VS = ID RS
VG = VDD R2 / (R1 + R2)
VGS = VG - VS
52
Example: Determine IDQ, VGSQ, VD, VS, VDS and VDG
R 2 V DD
VG =
R1+ R2
VGS = VG − I D RS
• Place ID=0 and VGS=0 and get
two points.
• Draw Straight Line, which
Intersects the Transfer Curve at
• IDQ= 2.4 mA and
• VGSQ= -1.8 V
Then,
VD = VDD − I D RD = 10.24
VS = ID RS = 3.6
VDS = VDD − I D (R D + R S ) = 6.64
Effect of increasing values of RS
Increasing values of RS result in
• lower quiescent values of ID and
• more negative values of VGS.
FET Amplifiers
FETs provide:
56
FET Small-
Small-Signal Model
The ac analysis of an FET configuration requires that a small-signal ac
model for the FET be developed.
Transconductance
The change in Drain current that will result from a change in gate-
to-source voltage can be determined using the transconductance
factor gm in the following manner:
∆I D
gm =
∆V GS
57
Graphical Determination of gm
Slope of the characteristics at the point of operation.
58
Mathematical Definitions of gm
Alternative Approach: The derivative of a function at a point is equal
to the slope of the tangent line drawn at that point.
∆I D Take Derivative of ID with respect to VGS using Shockley’s
gm = Equation,
∆VGS
2I DSS VGS
gm = 1 −
VP VP
Mathematical Definitions of gm
2I DSS VGS
gm = 1 −
VP VP
2I DSS
Where VGS =0V g m0 =
VP
V
g m = g m0 1 − GS
VP
Where 1 − VGS = ID
Shockley’s Equation
VP I DSS
VGS ID
g m = g m0 1 − = g m0
VP I DSS
Plot of gm versus VGS
VGS ID
g m = g m0 1 − = g m0
VP I DSS
Input impedance:
impedance: Very large
63
FET Impedance
The output impedance is defined on the characteristics of Fig. as the
slope of the horizontal characteristic curve at the point of operation.
• The more horizontal the curve, the greater the output impedance.
• If perfectly horizontal, the ideal situation is on hand with the output
impedance being infinite (an open circuit) an often applied
approximation.
FET AC Equivalent Circuit
65
Common--Source (CS) Fixed-
Common Fixed-Bias Circuit
• The input is on the gate and the output is on the drain.
• Capacitors Act as Short Circuit. They Also Isolates DC
Biasing from Circuit. So, VGG and VDD are Short
Circuited
• gm and rd are determined from small signal analysis.
66
Calculations
Input impedance: Zi = RG
Output impedance:
Zo ≅ R D
rd ≥ 10R D
Voltage gain:
V Vo
A v = o = − g m (rd || R D ) Av = = −g m R D
rd ≥ 10R D
Vi Vi
Example
For Fixed Bias Configuration
With Operating Point
• VGSQ= - 2V and IDQ= 5.625
mA,
• IDSS = 10 mA VP= - 8V
• Yos = 40 μS
Common--Source (CS) Self
Common Self--Bias Circuit
• This is a common-source amplifier
configuration, so the input is on the
gate and the output is on the drain.
• Rs can play Role in Biasing, But in AC
Analysis, Capacitor Cs Shorts Rs and
thus same circuit as in Fixed Bias.
69
Calculations
Input impedance:
Zi = RG
Output impedance:
Z o = rd || R D
Zo ≅ R D
rd ≥ 10R D
Voltage gain:
A v = − g m (rd || R D )
A v = −g m R D
rd ≥ 10R D
70
Common--Source (CS) Voltage
Common Voltage--Divider Bias
This is a common-source
amplifier configuration, so the
input is on the gate and the
output is on the drain.
71
Impedances
Input impedance:
Z i = R 1 || R 2
Output impedance:
Z o = rd || R D
Zo ≅ R D
rd ≥ 10R D
Voltage gain:
A v = − g m (rd || R D )
A v = −g m R D
rd ≥ 10R D
72
Source Follower (Common-
(Common-Drain) Circuit
In a common-drain amplifier
configuration, the input is on the gate,
but the output is from the source.
Input impedance:
Zi = RG
Output impedance:
1
Z o = rd || R S ||
gm
1
Z o ≅ R S || r ≥ 10R S
gm d
Voltage gain:
Vo g m (rd || R S )
Av = =
Vi 1 + g m (rd || R S )
Vo gmRS
Av = = r ≥ 10
Vi 1 + g m R S d
75
Source Follower (Common-
(Common-Drain) Circuit
To Find Zo
76
Source Follower (Common-
(Common-Drain) Circuit
77
Source Follower (Common-
(Common-Drain) Circuit
78
Common--Gate (CG) Circuit
Common
79
Calculations
Input impedance:
r + RD
Z i = R S || d
1 + g m rd
1
Z i ≅ R S || r ≥ 10R D
gm d
Output impedance:
Z o = R D || rd
Voltage gain:
Z o ≅ R D rd ≥ 10
RD
g
m D R +
Vo rd A v = g m R D rd ≥ 10R D
Av = =
Vi RD
1 +
rd
80
JFET Specifications Sheet
Electrical Characteristics
JFET Specifications Sheet
Maximum Ratings
82
Case and Terminal Identification
83
MOSFETs
Metal Oxide Semiconductor Field Effect Transistor
• Depletion-Type
Depletion-
• Enhancement--Type
Enhancement
84
Depletion--Type MOSFET Construction
Depletion
The Drain (D) and Source (S) connect to
the to n-doped regions. These n-doped
regions are connected via an n-channel.
85
Basic MOSFET Operation
• Gate-to-source voltage is set to zero.
• voltage VDS is applied across the drain-
to-source terminals.
• Result is an attraction for the positive
potential at the drain by the free
electrons of the n-channel and a current
similar to that established through the
channel of the JFET.
• VGS > 0 V
• ID increases above IDSS due to collision of particles creating carriers 2
• The formula used to plot the transfer curve still applies: V
I D = I DSS 1 − GS
Note that VGS is now a positive polarity VP
D-Type MOSFET in Enhancement Mode
91
Specification Sheet
Maximum Ratings
Specification Sheet
Electrical Characteristics
E-Type MOSFET Construction
• The Drain (D) and Source (S) connect
to the to n-doped regions.
• There is no channel
94
Basic Operation of the E-
E-Type MOSFET
The enhancement-
enhancement-type MOSFET operates only in the enhancement mode.
I D = k ( VGS − VT ) 2
Where:
VT = threshold voltage
or voltage at which the
MOSFET turns on
VDsat = VGS − VT
p-Channel E-Type MOSFETs
101
MOSFET Symbols
102