Stacked plate capacitor design technique for transmission line is used.

transmission line is used. Therefore, the parasitic effects for the SPC
filters constructed on multilayer substrates
Ke Cao and Chonghu Cheng✉
A stacked plate-capacitor design technique for filters constructed on
multilayer substrates is proposed. With this technique, the parasitic
effects between capacitors and grounds as well as the parasitic
effects between different capacitors can be significantly reduced. The
proposed layout can be used in multlayered filters design as a block
and the design procedure for filters can be simplified. The proposed
layout is analysed in detail. A multilayered filter is designed to demon-
strate the design procedure. Both simulation results and measurement
results show the effectiveness of the proposed technique.
Introduction: Vertical-integrated-capacitors (VICs) are usually used in
multilayered filters design because of its large capacitance and small
size [1]. However, the via-holes in VICs may result in parasitic inductors
and parasitic resonances. Many works have been carried out on VICs to
reduce the parasitic effects and improve the performance. In [2], alter-
nate fingers of interdigital capacitors are shorted to eliminate the spur-
ious spikes. In [3], by connecting the open ends of interval fingers of
VIC, the spurious spikes are suppressed. In [4], a vertical and horizontal
interdigitated capacitor is proposed. Compared with the VIC, the capaci-
tance per unit area is obviously increased.
In multilayered filters design, capacitors are usually designed one by
one according to theoretical values. A reasonable space between adja-
cent capacitors is required for less coupling and transmission lines are
used for connections. This design technique is widely used [3–6] and
it may be called the conventional technique. Filters designed with this
technique have two disadvantages. One is the parasitic grounding
capacitors, which may be introduced by any component that is directly
placed above the ground. The other is transmission line, which intro-
duces both parasitic inductors and parasitic grounding capacitors.
These parasitic effects may introduce parasitic resonances and make
the overall response unexpected.
C1 C2
port 1 port 2
L1 C3
a very compact.
are reduced significantly. These improvements are demonstrated by
electromagnetic (EM) simulations and equivalent circuit. A multilayered
filter is designed to demonstrate the design procedure. The measurement
results agree well with the desired results. No obvious parasitic reson-
ance is observed until 6 GHz. These facts show the effectiveness of
the proposed technique.
SPC design technique: Take the circuit shown in Fig. 1a as the
example. The theoretical component values are C1 = C2 = 2 pF, C3 =
6 pF, and L1 = 2.8 nH. Based on this circuit, two physical layouts are
designed using the materials given in [5]. The layout shown in
Fig. 1b is the proposed SPC layout. The layout shown in Fig. 1c
comes from [5], which will be called the conventional layout.
Fig. 2 compares the EM simulation results of the SPC layout and the
conventional layout. The response of the SPC layout agrees very well
with the circuit response, except for a transmission zero locates at
0.06 GHz. Since this transmission zero is far away from the resonant fre-
quency, its influence is very limited. Besides this transmission zero, no
other parasitic resonance is observed. For filter composed of SPC
layouts, due to the parasitic effect reduction, its response may agree
well with desired circuit response. However, the response of the conven-
tional layout does not agree well with the circuit response. Due to the
parasitic effects, several undesired resonances are observed. For filters
composed of conventional layouts, these undesired resonances may
have great influences on the overall response.
0
–20
S21, dB –40
–60
–80
circuit
–80 –100
SPC layout
–100 conventional layout
0.04 0.08
0 1 2 3 4 5 6
frequency, GHz
Fig. 2 Frequency response of SPC layout and conventional layout
In this example, the size of the SPC layout and the conventional
layout are about 3.4 × 3.7 × 0.43 mm3 and 4.1 × 4.2 × 0.53 mm3,
respectively. Since no transmission line is used, the SPC layout is

layer 5 (ground) CC
C3
layer 4 LP1 C1 C2 LP2
port 1 port 2
C2
port 1 L1 CL1 C3
layer 3
C1
port 2
layer 2 a
0

L1 C3 layer 1 (ground) –20

via 1 –40 –80

S21, dB

via 2
b –60
–100
–80
L1 0.04 0.08 SPC layout
port 1 –100 equivalent circuit
TX line 2

0 1 2 3 4 5 6
C1 C3 }six layers frequency, GHz
b
C2
TX line 1 Fig. 3 Equivalent circuit of SPC layout and its frequency response
port 2
a Equivalent circuit of SPC layout
c b Frequency response of equivalent circuit

Fig. 1 Circuit example and multilayered layouts
a Circuit example
b Proposed SPC layout
c Conventional layout
To overcome these disadvantages, a stacked plate-capacitor (SPC)
design technique is proposed in this Letter. The SPC is a combination
of several capacitors and inductor. It can be used in multilayered
filters design as a block and the design procedure for filters can be sim-
plified. In the SPC, capacitors are arranged on different layers and no
The parasitic effect reduction of the SPC layout can be explained by
its equivalent circuit, as shown in Fig. 3a. In the SPC layout, L1 is com-
posed of a meandered inductor and two via-holes (via 1 and via 2 in
Fig. 1b). The meandered inductor introduces parasitic grounding capaci-
tor (noted as CL1 in Fig. 3a). For C1, C2, and C3, each of them is
designed as two identical parallel metal-insulator-metal sub-capacitors.
The electrodes on layers 2 and 4, which are connected by via 1, are
shared by C1, C2, and C3. The parasitic inductor of via 1 is a part of
L1, so it is desired. C1 and C2 are sandwiched by the sub-capacitors
of C3, so they do not introduce parasitic grounding capacitor. The

ELECTRONICS LETTERS 29th September 2016 Vol. 52 No. 20 pp. 1695–1697

coupling between C1 and C2 is noted as CC and it can be decreased by Fig. 4a as the example. The theoretical component values are L =
increasing the distance between C1 and C2. The parasitic grounding 4.1 nH, C1 = 0.66 pF, C2 = 0.18 pF, C3 = 0.15 pF, C4 = 1.77 pF, C5 =
capacitors of ports are ignored because they are very small. The parasitic 2.2 pF, and k = 0.05% [6]. Fig. 4b shows the proposed filter layout,
inductors of ports are noted as LP1 and LP2. which is composed of four SPCs. Due to the symmetry, only a part of
components are marked. Notably, each of C2 and C3 are designed as
C1 C2 C3 C2 C1 two series capacitors. These two series capacitors are placed in two adja-
port 1 port 2 cent SPCs, respectively. As a result, no additional via-hole is used for C2
k and C3. In each SPC, the coupling between two series capacitors is
C4 L C5 L L C5 L C4 reduced by increasing their distance.
k Due to the limitation of experiment conditions, PCB technology was
a used to fabricate the experimental prototype. The selected substrate is
C5 1 mm-thickness Rogers 5880 (εr = 2.2). All layers are manually
L
stacked and fixed. The core size of the filter is about 1.94 × 10−4 l3g .
The measurement was performed with a Rohde & Schwarz ZVA67
C3
port 1 vector network analyser. The measurement results and simulation
results are shown in Fig. 5a. The photograph of the experimental proto-
C1
type is shown in Fig. 5b.
C4 Good agreement between the measurement results and simulation
results can be observed. The measured central frequency and bandwidth
k
C2 are 1.57 GHz and 140 MHz, respectively. The designed central fre-
port 2 quency and bandwidth are 1.567 GHz and 157 MHz, respectively.
The differences between them are mainly caused by the stacking shift.
b The measured out-of-band suppression near the passband is about
36 dB. Due to the parasitic effect reduction, no obvious resonance is
Fig. 4 Filter circuit and proposed filter layout observed. The measured out-of-band suppression from 2 to 6 GHz is
a Fourth-order filter circuit better than 28 dB. The good agreement between desired response and
b Proposed filter layout
measurement response and the good out-of-band suppression means
that the parasitic effects in the filter are obviously reduced.
0
circuit
Conclusion: An SPC design technique for filters constructed on multi-
EM simulation
–20
layer substrates is proposed. A physical layout for filters based on the
S parameter, dB

S11 measurement
–40 S21
proposed technique is presented and analysed in detail. A multilayered
filter is used to demonstrate the design procedure. Good agreements
–60 between measurement results and desired results can be observed.
Due to the parasitic effect reduction, the out-of-band suppression is
–80 better than 28 dB until 6 GHz and no obvious resonance is observed.
0 1 2 3 4
frequency, GHz Acknowledgment: This work was supported by the National Natural
a Science Foundation of China (NSFC) under Grant 61071020.

© The Institution of Engineering and Technology 2016

Submitted: 28 April 2016 E-first: 14 September 2016
doi: 10.1049/el.2016.1519
Ke Cao and Chonghu Cheng (School of Electronic Science and
b Engineering, Nanjing University of Posts and Telecommunications,
Nanjing, People’s Republic of China)
Fig. 5 Results and photograph of experimental prototype ✉ E-mail: chengch@njupt.edu.cn
a Measurement results and simulation results
b Photograph
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ELECTRONICS LETTERS 29th September 2016 Vol. 52 No. 20 pp. 1695–1697