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MAP8802 MagnaChip
MAP8802 MagnaChip
The MAP8802 is an active power factor correction Near Unity Power Factor
(PFC) controller for boost PFC applications that operates No Input Voltage Sensing Requirement
in critical conduction mode (CRM) Latching PWM for Cycle-by-Cycle on time
In CRM operation, the on time is constant during the ac Control (Voltage Mode)
line cycle and the off time varies with the instantaneous Trans-conductance Amplifier
input voltage. High Precision Voltage Reference
The voltage mode CRM PFC controller does not need the (±1.6% Over the temperature range)
input voltage sense line. It can reduce power loss. CRM Very low startup current consumption (≤35uA)
operation is an ideal choice for medium power Low typical operating current consumption
(100W~300W) PFC boost stages with the zero current Source 500mA / Sink 800mA Totem pole gate
switching of DCM operation. driver
MAP8802 provides protection functions such as Under-voltage lockout with hysteresis
overvoltage protection, under-voltage protection, open Pin-to-Pin compatible with industry standards
feedback loop protection, overcurrent protection, PFC This is a Pb-Free and Halide-Free Device
output/bypass diode short protection, ZCD winding short ZCD Short protection
protection.
MAP8802 is a available in an SOP-8 Pin package. The
device operates over the -40°C ~ 125°C temperature.
ranges.
Protection function
Applications
Boost diode short Protection
AC Adapter
Bypass diode short Protection.
Ballast, Solid State Lighting
ZCD winding short Protection
LCD TV, Monitor
Overvoltage Protection
PDP TV
Overcurrent Protection
SMPS
Undervoltage Protection
Open/Floating feedback Protection
Ordering Information
Top Ambient
Part Number Package Pb-Free
Marking Temperature Range
MAP8802 MAP8802 -40°C~125°C 8-Lead Small Outline Package (SOP-8 Pin) YES
1 FB Vcc 8
2 CT DRV 7
3 CONTROL GND 6
4 CS ZCD 5
MAP8802
Figure 1. Pin configuration (Top View)
Pin Description
Pin
Name Description
NO
The FB pin is the inverting input of the internal error amplifier. The output voltage of the boost PFC
1 FB
converter should be resistively divided to 2.5V.
The CT pin sources a current to charge an external timing capacitor. The circuit controls the power
2 CT
switch on time by comparing the CT voltage to an internal voltage derived from VCONTROL
The Control pin is the output of the internal error amplifier. A compensation network is connected
3 CONTROL
between the control pin and ground to set the loop bandwidth.
The CS pin limits the cycle-by-cycle current through the power switch. When the CS voltage
4 CS exceeds VILIM , the drive turns off. The sense resistor that connects to the CS pin programs the
maximum switch current.
The ZCD pin is the zero current detection pin. When the voltage of this pin goes lower than 0.7, the
5 ZCD
MOSFET is turned on.
The VCC pin is the positive supply of the controller. The controller is enabled when V CC exceeds
8 VCC
VCC(ON) and is disabled when VCC decreases to less than VCC(OFF).
ZCD ZCD
OVP (TRIG) (ARM)
8 Vcc
UVLO
UVP
POK VCC VDD
FB 1 ZCD
Gm Clamp
R Q
OUT
CONTROL 3
VEAH S Q
Clamp Vcc
Error R Q
detection Freq.
Vcc S Q 7 OUT
limit
PWM
Ct Gen w R Q
CT 2 Off set
Reset
OUT Off Timer S Q
OCP
LEB R Q
OUT
CS 4
VILIM S Q
VDD
VDSP 6 GND
R Q POK
Application Diagram
DC OUTPUT
AC
VCC
MAP8802
VCC OUT
ZCD CS
CT FB
Control GND
Notes:
1. Human Body Model(HBM) per JESD22-A for all pins / Machine Model(MM) per JESD22-A 115 for all pins.
Notes:
2. This parameters are not production tested: Guaranteed by design correlation.
3. This parameter is influenced by board pattern. So we are recommended that connect to bid at MOSFET drain current path.
34
2.52
32
VREF REFERENCE VOLTAGE[V]
2.51 30
ICCSTARTUP[mA]
28
2.50
26
2.49 24
22
2.48
20
-40℃ -20℃ 0℃ 25℃ 50℃ 85℃ 100℃ 125℃ -40℃ -20℃ 0℃ 25℃ 50℃ 85℃ 100℃ 125℃
TJ, JUNCTION TEMPERATURE[℃] TJ, JUNCTION TEMPERATURE[℃]
200
5.0
180
Figure 5. Startup Current Consumption vs.
VCT(MAX), CT PEAK VOLTAGE[V]
tSTART, MAXIMUM OFF TIME[us]
160
4.9 Junction Temperature
140
4.8
Figure 4. Reference Voltage vs.
120
100 4.7
80
4.6
60
-40℃ -20℃ 0℃ 25℃ 50℃ 85℃ 100℃ 125℃ -40℃ -20℃ 0℃ 25℃ 50℃ 85℃ 100℃ 125℃
Figure 6. Maximum off time in Absence of ZCD Figure 7. Ct Peak Voltage vs.
Transition vs. Junction Temperature Junction Temperature
108.0 107
OVERVOLTAGE DETECT THRESHOLD[%]
107.5
Figure
106 5. Startup Current Consumption vs.
107.0 Junction Temperature
105
106.5
OVP_H,
OVP_L,
105.0
102
104.5
104.0 101
-40℃ -20℃ 0℃ 25℃ 50℃ 85℃ 100℃ 125℃ -40℃ -20℃ 0℃ 25℃ 50℃ 85℃ 100℃ 125℃
Figure 8. Overvoltage High Detect Threshold Figure 9. Overvoltage Low Detect Threshold
vs. Junction Temperature vs. Junction Temperature
0.54
0.38
0.32
0.50
VUVP,
0.30
0.28
0.26 0.48
0.24
0.22 0.46
0.20
-40℃ -20℃ 0℃ 25℃ 50℃ 85℃ 100℃ 125℃ -40℃ -20℃ 0℃ 25℃ 50℃ 85℃ 100℃ 125℃
Figure 10. Undervoltage Detect Threshold vs. Figure 11. Current Sense Voltage Threshold vs.
Junction Temperature Junction Temperature
20 -6
18 Figure
-8 5. Startup Current Consumption vs.
Junction Temperature
16 -10
IEASOURCE[uA]
14 -12
IEASINK[uA]
10 -16
8 -18
6 -20
-40℃ -20℃ 0℃ 25℃ 50℃ 85℃ 100℃ 125℃ -40℃ -20℃ 0℃ 25℃ 50℃ 85℃ 100℃ 125℃
Figure 12. Error Amplifier Sink Current vs. Figure 13. Error Amplifier Source Current vs.
Junction Temperature Junction Temperature
150 10
9
140 Figure 5. Startup Current Consumption vs.
Junction Temperature
TRANSCONDUCTANCE [umho]
130 8
gm, ERROR AMPLIFIER
7
120
RFB[Mohm]
110
6 Figure 4. Reference Voltage vs.
5
100
4
90
3
80
2
-40℃ -20℃ 0℃ 25℃ 50℃ 85℃ 100℃ 125℃ -40℃ -20℃ 0℃ 25℃ 50℃ 85℃ 100℃ 125℃
TJ, JUNCTION TEMPERATURE[℃] TJ, JUNCTION TEMPERATURE[℃]
Figure 14. Error Amplifier Transconductance Figure 15. Feedback Pin Internal Pull-Down
vs. Junction Temperature Resistor vs. Junction Temperature
2.508
50
2.506
0
2.504
-50 2.502
CURRENT[uA]
2.500
-100
2.498
-150
2.496
-200 2.494
2.492
-250
2.490
0.0 0.5 1.0 1.5 2.0 2.5 3.0 12 13 14 15 16 17 18 19 20
Figure 16. Error Amplifier Output Current vs. Figure 17. Feedback Voltage vs. VCC Voltage
Feedback Voltage
1. Start up The FB is floating. The internal pull down resistor RFB pulls
Generally, if the VCC voltage goes to VCC(ON), the IC’s down the FB voltage below VUVP. The UVP comparator
internal blocks are enabled. The low startup current detects an UVP fault, the drive and error amplifier are
consumption (<35uA) enables minimized standby power disabled.
dissipation. The VCC voltage should be higher than 9.5V
under normal conditions after start-up.
3. Ct Block
8 The MAP8802 controls the on time with the capacitor
connected to the Ct pin. A current source charges the Ct
UVLO Vcc capacitor to a voltage derived from the Control pin voltage
(VCt(off)). When VCt(off) is reached, the drive turns off.(Figure
20. Turn on Time Regulation) The Ct capacitor is sized to
Vcc
ensure that the required on time is reached at maximum
output power and the minimum input voltage condition. The
Ct pin discharges the external timing capacitor at the end of
the on time.
9.5V 12V
Control VCONTROL-Ct(offset)
12V 3
9.5V VCC
Ct(offset) PWM
tON
Ct 2 OUT
Figure 18. Startup circuit OUT
2. FB Block
PWM Block
Scaled-down voltage from the output is the input for the FB
pin. The used trans-conductance amplifier is good for the Ton(MAX)
implementation of OVP and disables functions. The output
current of the amplifier varies according to the voltage
difference. The MAP8802 features comprehensive protection Ct
Slope
against open feedback loop conditions by including OVP, =
ICHARGE
UVP, and FBP. Figure 19 illustrates three conditions in which
the feedback loop is open.
TPWM
OVP Ct(offset) VEAH
FB 1
4. Control Block
Gm The scaled output is compared with the internal reference
tISS voltage and sinking or sourcing current is generated from the
VREF
control pin by a trans-conductance amplifier. The error
amplifier output is compared with the saw-tooth waveform
Control created at the Ct. When load is heavy, output voltage
3 decreases, scaled output decreases, Control voltage
VEAH Error increases to compensate low output. The maximum of
Clamp detection VCONTROL is limited to 5.5V and switching stops when Ct(offset)
is lower than 0.65V. The pre-converter is compensated to
ensure stability over the input voltage and output power
range. To compensate the loop, a compensation network is
connected between the Control and ground pins.
Figure 19. Open Feedback Loop Protection To ensure high PF, the bandwidth of the loop is set below
20Hz. Compensation network is selected for this design to
The UVP comparator detects an UVP fault, the drive and increase the phase margin.
error amplifier are disabled. The compensation network is shown in Figure 21.
The OVP comparator detects an OVP fault and the drive is
disabled.
FB
OCP
250umho
CS 4
VILIM
VDSP
Figure 22. Gain Change
Ton(MAX)
Toff
TSW
Vcc
OUT
UVLO
UVLO
VDD
OUT IN
VAUX
Short
MP8802
8 VCC Out 7
5 ZCD
CS 4
2 Ct
FB
3 Control 1
GND
VCC(ON)
VCC(OFF)
TSTART_Timer
150us TSTART Timer : 16Cycle
TSTART Timer : 150us TSTART Timer : 150us
2. Operating information.
3. Transformer information.
3.1 Winding specification
PIN WIRE TURNS
Np 4,5 → 2,3 0.1φ*60 49
Insulation Tape 0.05mm 3
Naux 7→9 0.5φ*1 6
Insulation Tape 0.05mm 3
4. Application Schematic
DP102
600V 3A
DP103
600V 8A DC OUTPUT
200uH
BDP101
600V,15A RP105
CP103 22k LP101
0.68uF, EER3124
630Vdc RP106 VAUX RP113
RP107 BD101
300,2W 300,2W 4.3M
RP104 CP106 RP109
ZDP101
68k,2W 12nF 100
1N4746A RP114
QP101
DP101 4.3M
LF102 MDF
N.C UF4007 ICP101 18N50
MAP8802
CP102 8 VCC RP110 DP104
Out 7 RP115 CP112 CP113
680nF 4.7 1N4148 RP117
5 ZCD 4.3M 100uF, 100uF,
CS 4 4.7
LF101 450V 450V
23mH RP108 CP111
2 Ct
20k FB 1nF
CP101 3 Control 1 ZDP102
220nF CP105 GND
N.C
0.1uF, 6 RP116
RP101 RP103 50V CP107 82k
1M-J RP111
1M-J RP102
1nF 10k CP110
1M-J
470pF
ZNR101
10D471
TH101
FP101 5D15 CP104 CP109 CP108 DP105 RP112
250V,5A 47uF,50V 2.2uF 0.68uF 1N4148 0.05, 5W
AC INPUT
IC MOSFET
MagnaChip MagnaChip
ICP101 MAP8802 QP102 MDF18N50
(8-SOP) (TO-220)
NTC Zener Diode
ZDP101 1N4746
TH101 5D-15 ZDP102 N.C Fairchild
ZDP103 1N4746
Resistor Capacitor
RP101
1/8W
RP102 1M-J CP101 220nF/275Vac X - Capacitor
(SMD-2012)
RP103
1/4W
RP105 22K-J CP103 680nF/630Vdc Box capacitor
(SMD3216)
RP106
300-J 2W CP104 47uF /50V Electrolytic Capacitor
RP107
1/8W
RP108 20K-J CP105 0.1uF/50V Chip Capacitor
(SMD-2012)
1/8W
RP109 47-J CP106 12nF/50V Film Capacitor
(SMD-2012)
1/8W
RP110 4.7-J CP107 1nF/50V Chip Capacitor
(SMD-2012)
1/8W
RP111 10K-J CP108 0.68uF/16V Chip Capacitor
(SMD-2012)
Connector
CN101
YHW396-03V
CN102
DISCLAIMER:
The products are not designed for use in hostile environments, including, without limitation, aircraft, nuclear power
generation, medical appliances, and devices or systems in which malfunction of any product can reasonably be
expected to result in a personal injury. Seller’s customers using or selling Seller’s products for use in such
applications do so at their own risk and agree to fully defend and indemnify Seller.
MagnaChip reserves the right to change the specifications and circuitry without notice at any time. MagnaChip does not consider responsibility
for use of any circuitry other than circuitry entirely included in a MagnaChip product. is a registered trademark of Magnachip
Semiconductor Ltd.