A

Write-up
Submission for the evaluation of Preparatory work of
Dissertation (SVE-601P)

MASTER OF TECHNOLOGY
In
VLSI DESIGN
By
SANJAY KUMAR SINGH
(Roll No. 31711215)
Under the Guidance of
Dr. Gaurav Saini
(Asst. Professor, SVE)

SCHOOL OF VLSI DESIGN AND EMBEDDED SYSTEM

NATIONAL INSTITUTE OF TECHNOLOGY
KURUKSHETRA-136119
SESSION 2017-19
Dissertation Title-:
To design low drop out (LDO) voltage regulator.
Objectives -:
To design LDO regulator with-
1. Lower dropout voltage
2. Improved load regulation
3. Low power dissipation
Tool Required -: Cadence Virtuoso 6.1.7
Literature Survey -:
The massive proliferation of battery-operated portable devices, such as cellphones, laptops or
wireless sensor networks, has made power management one of the IC industry major concerns.
In this scenario, low-dropout (LDO) voltage regulators have turned into the preferred choice for
low-voltage on-chip power management solutions, because of their fast response, simplicity and
low cost of implementation.

An LDO is a linear voltage regulator with a common source (or common emitter) output stage,
showing improved efficiency over the conventional linear regulators at the cost of higher
complexity. These regulators normally require an external capacitor of the order of µF to operate
properly, which makes them unsuitable deployment in applications SoC (system on chip). The
LDO regulator must supply a constant, noisefree, accurate and load-independent voltage level,
with particular DC, AC and transient characteristics, such as load and line regulation, stability
and transient response, which will depend on the actual application.

Low Dropout (LDO) Voltage Regulators are commonly used in IC design because of their
performance, low cost and simplicity [3]. They can be applied to battery-operated circuits,
medical, industrial and automotive applications, among others. Figure 1.2 shows the classical
topology of an LDO voltage regulator with a PMOS transistor as pass device.

Fig 1: LDO block diagram

Component Of LDO Regulator
 LDO Regulator mainly consist of these elements
▪ Pass element
▪ Error amplifier
▪ Voltage reference
▪ Feedback resistor
▪ Compensating circuit

Error Amplifier
Error amplifier takes the voltage scaled down by the voltage divider composed of resistors R1
and R2 , compares it with the reference voltage and adjusts the resistance of the pass element to
drive the error signal (VERR = VP − VREF ) as close to zero as possible. The DC open loop gain
should be high under all load conditions to ensure accuracy of the output. Bandwidth of the
amplifier should be large enough to react fast upon changes of the load conditions and input
voltages.

Voltage Reference
Voltage reference sets the operating point of the error amplifier, thus it is the starting point of all
regulators. In most cases this voltage reference is of the band-gap type, because it provide ability
to work at low supply voltages.

Fig.2 voltage reference output

Pass Element
Pass element is transferring large currents from input to the load and is driven by the error
amplifier in a feedback loop. For pass element we can choose either NMOS or PMOS transistor.

LDO Parameter
There are many parameters that decide performance of LDO regulator-:
▪ Drop-out voltage
▪ Quiescent current
▪ Efficiency
▪ Power supply rejection ratio
▪ Line regulation
▪ Load regulation

Drop-out voltage -: Dropout voltage represents the differential voltage between input and
output node of the voltage regulator at which the circuit ceases to regulate against further
decrease of the input voltage.

Quiescent Current -:Quiescent, or ground current is the difference between input and output
currents. Low quiescent current is needed to maximize efficiency, especially in low power
systems.

Efficiency -: LDO regulator efficiency is limited by the quiescent current and input to output
voltages as stated in following equation.
Efficiency = IoVo/(Io + Iq)Vi× 100 [%]
High efficiency can be achieved by minimizing the dropout voltage and quiescent current.

Power Supply Rejection Ratio -:Power supply rejection ratio (PSRR), also known as ripple
rejection is regulator’s ability to prevent fluctuation of regulated output voltage caused by input
voltage variation.
PSRR equation is the same as for line regulation, but the whole frequency spectrum is taken into
consideration.
PSRR = 20 · log10A(w)/Asupply(w) [dB]

Line Regulation -: Line regulation is a parameter defining the ability of the regulator to
maintain the desired output voltage with varying input voltage .

Load Regulation-: Load regulation is a parameter defining the ability of the regulator to
maintain the desired output voltage with varying load current.

Research Issues -: Major issues involved in the design of LDO voltage regulator are
stability and transient response.
Stability-: Presence of multiple poles definitely degrades the stability of any closed loop
system. The uncompensated capacitor less LDO consists of multi poles which are causes
instability.
Transient Response-: Transient response consists of two parts: undershoots/overshoots and
settling time. While there is a change in load current demand, error amplifier cannot change the
pass transistor gate input voltage quickly due to limited current (power consumption) and large
gate capacitance and this causes large settling time which are undesirable.

Existing Technique
Technique for improving stability-: which is achieved through appropriate compensation
techniques.Compensation can be external or internal.Generally, external compensation is
achieved with a high value capacitor in the order of µF. As for internal compensation, Miller
compensation is one of the most widely used technique. Amplifiers with a single-pole behavior
in the frequency domain are always stable because their phase margin is never lower than 90. In
the case of multi-pole amplifiers, stability might be compromised and the amplifier could
become unstable.For that reason, there are some methods that modify the open-loop transfer
function in order to turn the amplifier stable, which is called frequency compensation.
The transient response of an LDO is determined by both the loop gain bandwidth and the slew-
rate at the gate of pass transistor (SRG) [1]. Increasing the bandwidth makes the compensation
process more difficult and, therefore, the bandwidth of LDOs is generally low[1]. SRG should be
increased in order to have a proper transient response. Using a high slew-rate current-mode error
amplifier instead of a voltage-mode one, which suffers from limited slew-rate, can improve the
transient response while also decreasing power consumption [1].

Work Done -:

In LDO design there are mainly three components which have to be designed separately and
then merge them.
▪ Designing of voltage reference has been completed.
▪ Designing of error amplifier also completed.
▪ Pass element is decided and also designed.
▪ Compensating circuit is completed but still some improvement is required.

Results-:

(I) DC-response

Fig.3
(II) AC-response

Fig.4

(III) Power Supply Rejection Ratio

Fig.5

(IV) Noise Analysis

Fig.6
(V) Transient Response

Fig.7
(VI) Line Regulation

Fig.8
(VII) Load Regulation

Fig.9
Future Scope -:

➢ The future scope of this project is to improve transient response to make LDO regulator
more fast and stable.
➢ To make Layout of LDO.

References
[1] R. J. Milliken, J. Silva-Martinez and E. Sanchez-Sinencio, "Full On-Chip CMOS Low-
Dropout Voltage Regulator," in IEEE Transactions on Circuits and Systems I: Regular Papers,
vol. 54, no. 9, pp. 1879-1890, Sept. 2007..
[2] Ka Nang Leung and P. K. T. Mok, "A capacitor-free CMOS low-dropout regulator with
damping-factor-control frequency compensation," in IEEE Journal of Solid-State Circuits, vol.
38, no. 10, pp. 1691-1702, Oct. 2003.
[3] A. Suresh, S. R. Patri, D. Dwibedy, S. Bhat, K. Gaurav and K. S. R. Krishnaprasad, "Fully
On chip area efficient LDO voltage regulator," TENCON 2014 - 2014 IEEE Region 10
Conference, Bangkok,2014,pp.1-5 doi: 10.1109/TENCON.2014.7022464
[4] Wang L, Zhan C, Tang J, Li G. An amplifier‐offset‐insensitive and high PSRR subthreshold
CMOS voltage reference. Int J Circ Theor Appl. 2018;46:259–271.