Lecture #12: Verilog: From Nand To Tetris

Lecture #12:
Verilog
From Nand to Tetris
www.nand2tetris.org
Elements of Computing Systems, Nisan & Schocken, MIT Press, www.nand2tetris.org , Chapter 2: Boolean Arithmetic slide 1
Outline
•  History of hardware design languages

•  Data types
•  Structural Verilog
•  RTL FA FA FA FA
•  Combinational
•  Sequential module adder( input [3:0] A, B,
output cout,
output [3:0] S );
wire c0, c1, c2;
FA fa0( A[0], B[0], 1’b0, c0, S[0] );
FA fa1( A[1], B[1], c0, c1, S[1] );
FA fa2( A[2], B[2], c1, c2, S[2] );
FA fa3( A[3], B[3], c2, cout, S[3] );
endmodule
Slides adapted from UCSD CSE 141L – Taylor

Originally designers used
breadboards for prototyping
Number of Gates
in Design
107
Solderless
Breadboard
106
105
tangentsoft.net/elec/breadboard.html
No symbolic 104
execution or
testing 103
Printed circuit board 102
home.cogeco.ca 10
HDLs enabled logic level
simulation and testing
Number of Gates
Gate Level in Design
Description
107
Simulate
Test 106
Results
Manual 105
104
103
102
HDL = Hardware Description Language 10
Designers began to use HDLs
for higher level design
Number of Gates
in Design
Behavioral Simulate 107
Test
Algorithm Results 106
105
Simulate
Register Test
Transfer Level Results 104
103
Simulate
Test
Gate Level Results 102
10
Manual
For us:
Behavioral == Truth table
RTL == Interface
GL == HDL
HDLs led to tools for
automatic translation
Number of Gates
in Design
Behavioral Simulate 107

Test
Algorithm Results
106
Manual
Simulate 105
Register Test
Transfer Level Results
104
Logic Synthesis
Simulate 103
Test
Gate Level Results 102
Auto Place + Route
10
HDLs: Verilog, VHDL…
Tools: Spice, ModelSim,
DesignCompiler, …
Raising the abstraction
further…
Simulate Number of Gates
Guarded Atomic Test in Design
Actions Results
107
GAA Compiler
Simulate 106
Register Test
Transfer Level Results
105
Logic Synthesis
Simulate 104
Test
Gate Level Results
103
Auto Place + Route
102
10
Current Situation
C, C++, Behavioral RTL
MATLAB
SystemC Verilog, VHDL,
SystemVerilog
Structural RTL
Register Verilog, VHDL,
Transfer Level
SystemVerilog
Logic Synthesis
Gate Level
Simulators and other tools
are available at all levels but
not compilers from the
behavioral level to RTL
Data Type (Bit-vector)
A bit can take on one of four values

Value Meaning
0 Logic zero

1 Logic one
X Unknown logic value
Z High impedance, floating
An X bit might be a 0, 1, Z, or in transition. We can set

bits to be X in situations where we don’t care what the
value is. This can help catch bugs and improve
synthesis quality.
“wire” is used to denote a
hardware net
wire [15:0] instruction; Absolutely no

wire [15:0] memory_req; type safety when
wire [ 7:0] small_net; connecting nets!
memory_req
small_net
instruction
instruction
Bit literals Binary literals
n 8’b0000_0000

n 8’b0xx0_1xx1
Hexadecimal literals
4’b10_11

n 32’h0a34_def1

n  16’haxxx
Underscores
are ignored
(readability) Decimal literals

Base format n 32’d42
(d,b,o,h)

We’ll learn how to Decimal

actually assign number
literals to nets a representing
little later size in bits

Structural Verilog
•  Verilog is a big language with many

features not concerned with synthesizing
hardware.
•  The code you write for your processor
should only contain the languages
structures discussed in these slides.
•  Anything else is not synthesizable,
although it will simulate fine.
A Verilog module has a
name and a port list
A B

module adder( A, B, cout, sum );
4 4 input [3:0] A;
input [3:0] B;
output cout;
adder output [3:0] sum;

// HDL modeling of
4
// adder functionality
cout sum endmodule
Ports must have a

direction and a Note the semicolon
bitdwidth (if none, at the end of the port
defaults to 1 bit) list!
Alternate syntax
A B Traditional Verilog-1995 Syntax
(previous slide)

4 4

module adder( A, B, cout, sum );

input [3:0] A;
adder input [3:0] B;
output cout;
4 output [3:0] sum;
cout sum
ANSI C Style Verilog-2001 Syntax

module adder( input [3:0] A,
input [3:0] B,
output cout,
output [3:0] sum );
A module can instantiate
other modules cout
a b
cin
A B FA
c
adder FA FA FA FA
cout S
module adder( input [3:0] A, B,

output cout,
output [3:0] S );
wire c0, c1, c2;
FA fa0(
... ); module FA( input a, b, cin
FA fa1(
... ); output cout, sum );
FA fa2(
... ); // HDL modeling of 1 bit
FA fa3(
... ); // full adder functionality
endmodule
endmodule
Connecting modules
A B
adder FA FA FA FA
cout S
module adder( input [3:0] A, B,

output cout,
output [3:0] S );
wire c0, c1, c2;
FA fa0( A[0], B[0], 1’b0, c0, S[0] );
FA fa1( A[1], B[1], c0, c1, S[1] );
FA fa2( A[2], B[2], c1, c2, S[2] );
FA fa3( A[3], B[3], c2, cout, S[3] );
Carry Chain
endmodule
Alternative syntax
Connecting ports by ordered list

FA fa0( A[0], B[0], 1’b0, c0, S[0] );

Connecting ports by name (compact)

FA fa0( .a(A[0]), .b(B[0]),
.cin(1’b0), .cout(c0), .sum(S[0]) );

Argument order does not matter when ports
are connected by name
FA fa0 Connecting ports by name

( .a (A[0]), yields clearer and less
.cin (1’b0),
.b (B[0]), buggy code.
.cout (c0),
.sum (S[0]) );
Simple Behavior
•  A module’s behavior can be described in many
diﬀerent ways but it should not maCer from outside

Example: mux4
Mux4:
Gate-level structural Verilog
module mux4(input a,b,c,d, input [1:0] sel, output out);
wire [1:0] sel_b;
not not0( sel_b[0], sel[0] );
not not1( sel_b[1], sel[1] );
b d a c sel[1]sel[0]
wire n0, n1, n2, n3;
and and0( n0, c, sel[1] );
and and1( n1, a, sel_b[1] );
and and2( n2, d, sel[1]);
and and3( n3, b, sel_b[1]);
wire x0, x1; Looks
nor nor0( x0, n0, n1 ); familiar….
nor nor1( x1, n2, n3 );
wire y0, y1;
or or0( y0, x0, sel[0] );
or or1( y1, x1, sel_b[0] );
nand nand0( out, y0, y1 );
endmodule
out
Mux4:
Using continuous assignments to
generate combinational logic
Language defined
module mux4( input a, b, c, d operators
input [1:0] sel,
output out );
wire t0, t1;

assign out = ~( (t0 | sel[0]) & (t1 | ~sel[0]) );
assign t1 = ~( (sel[1] & d) | (~sel[1] & b) );
assign t0 = ~( (sel[1] & c) | (~sel[1] & a) );
endmodule
The order of these continuous

assignment statements does not matter.
They essentially happen in parallel!
Mux4: Behavioral style
(Conditional Statement)
// Four input multiplexer If input is

module mux4( input a, b, c, d undefined
input [1:0] sel,
output out ); we want to
assign out =(

sel == 0 ) ? a :
propagate that
( sel == 1 ) ? b : information.
( sel == 2 ) ? c :
( sel == 3 ) ? d : 1’bx;
endmodule
mux4: Using “always block”
module mux4( input a, b, c, d
input [1:0] sel,
output out );

reg out, t0, t1; //notice reg!
always @( a or b or c or d or sel ) //could use always @(*)

begin
t0 = ~( (sel[1] & c) | (~sel[1] & a) );
t1 = ~( (sel[1] & d) | (~sel[1] & b) );
out = ~( (t0 | sel[0]) & (t1 | ~sel[0]) );
end
endmodule
The order of these procedural

assignment statements DOES matter.
They essentially happen sequentially
inside begin/end block!
“Always blocks” permit more
advanced sequential idioms
module mux4( input a,b,c,d module mux4( input a,b,c,d
input [1:0] sel, input [1:0] sel,

output out ); output out );

reg out; reg out;

always @( * ) always @( * )
begin begin
if ( sel == 2’d0 ) case ( sel )
out = a; 2’d0 : out = a;
else if ( sel == 2’d1 ) 2’d1 : out = b;
out = b; 2’d2 : out = c;
else if ( sel == 2’d2 ) 2’d3 : out = d;
out = c; default : out = 1’bx;
else if ( sel == 2’d3 ) endcase
out = d; end
else endmodule
out = 1’bx;
end
endmodule
What happens if the case
statement is not complete?
module mux3( input a, b, c
input [1:0] sel,
output out );
reg out;

always @( * ) If sel = 3, mux will output
begin the previous value!
case ( sel )
2’d0 : out = a; Why?
2’d1 : out = b;
2’d2 : out = c; What have we done?!
endcase
end

endmodule
What happens if the case
statement is not complete?
module mux3( input a, b, c
input [1:0] sel,
output out );
reg out;

always @( * )
begin We CAN prevent creating
case ( sel ) state with a default
2’d0 : out = a;
statement
2’d1 : out = b;
2’d2 : out = c;
default: out = 1’bx;
endcase
end

endmodule
Parameterized mux4
module mux4 #( parameter WIDTH = 1 ) default value
( input[WIDTH-1:0] a, b, c, d
input [1:0] sel,
output[WIDTH-1:0] out );
wire [WIDTH-1:0] out, t0, t1;
assign t0 = (sel[1]? c. : a);

assign t1 = (sel[1]? d. : b);
assign out = (sel[0]? t0: t1); Instantiation Syntax
endmodule
mux4#(32) alu_mux
( .a (op1),
Parameterization is a good .b (op2),
.c (op3),
practice for reusable modules
.d (op4),
Writing a muxn is challenging .sel (alu_mux_sel),
.out (alu_mux_out) );
Verilog Registers “reg”
•  Wires are line names – they do not represent storage and
can be assigned only once
•  Regs are imperaKve variables (as in C):
–  “nonblocking” assignment r <= v
–  can be assigned mulKple Kmes and holds values between
assignments
•  Blocking Statements
–  must be executed before the execuKon of the
statements that follow it in a sequenKal block.
•  Nonblocking Statements
–  Use whenever you want to make several register
assignments within the same Kme step without regard to
order or dependence upon each other
–  resemble actual hardware more than blocking
assignments
flip-flops
module FF0 (input clk, input d,
output reg q); next_X D Q X
always @( posedge clk ) clk
begin
q <= d;
end
endmodule
module FF (input clk, input d,

input en, output reg q);
always @( posedge clk )
begin
if ( en ) next_X D Q X
q <= d; clk
end
endmodule enable
flip-flops with reset
always @( posedge clk) reset
begin next_X D Q X
if (reset)
Q <= 0; clk

else if ( enable ) enable
Q <= D;
end synchronous reset
What is the difference?

always @( posedge clk or
posedge reset)
begin
if (reset)
Q <= 0;
else if ( enable )
Q <= D;
end Asynchronous reset
Sync vs. Async Resets
Advantages: Advantages:
•  Flip-Flop less complex, smaller •  reset has priority over other signals
•  Circuit completely synchronous •  occurs with or w/o clock

Disadvantages: Disadvantages:
•  gets complex in combinaKonal logic •  reset value must clear in less than a
•  resets may not occur in same clock clock cycle
cycle •  reset line sensiKve to glitches
•  requires clock
Latches versus flip-flops
module latch module flipflop
( (
input clk, input clk, input
input d, d, output
output reg q reg q
); );

always @( clk or d ) always @( posedge clk )

begin begin
if ( clk ) q <= d;
q <= d; end
end Edge-triggered
endmodule
always block
endmodule
Register
module register#(parameter WIDTH = 1)

(
input clk,
input [WIDTH-1:0] d,
input en,
output [WIDTH-1:0] q
);
always @( posedge clk )

begin
if (en) q <= d;
end
endmodule
Register in terms of
Flipflops
module register2 module register2
( input clk, ( input clk,
input [1:0] d, input [1:0] d,
input en, input en,
output [1:0] q ); output [1:0] q

);
always @(posedge clk) FF ff0 (.clk(clk), .d(d[0]),
begin .en(en), .q(q[0]));

if (en)
q <= d; FF ff1 (.clk(clk), .d(d[1]),
end .en(en), .q(q[1]));
endmodule endmodule
Do they behave the same?

yes
Three abstraction levels for
functional descriptions
Behavioral
Algorithm V Abstract algorithmic
description
Manual
Register Describes how data flows

Transfer Level V between state elements for each
cycle
Logic Synthesis
Low-level netlist
Gate Level V of primitive gates
Auto Place + Route

Source: http://www.asic-world.com/verilog/
Verilog Operators verilog_one_day1.html#Data_Type
Hello, Verilog World!
Hello World program:
•  Open your favorite text editor module main;
•  Code to place inside of hello.v initial
•  Compiling program: begin
–  Open Command Prompt window $display("Hello, World!");
•  Start, then type cmd, $finish ;
then hit Enter end
–  Navigate to where hello.v is stored endmodule
–  Type following command:
•  iverilog –o hello hello.v
•  Running program:
–  vvp hello
•  Output in console:
–  Hello, Verilog World!
Testbench
How do we build/run chips like we did in HDL?
•  Equivalent of Chip file (.hdl) == Verilog file of chip (.v)
•  Simulator == vvp (command line)
•  Test files (.tst) == Testbench (.v with test only)
//counter_tb.v //counter.v
module counter_tb; module counter(out, clk, reset);
parameter WIDTH = 8;
/* Make a reset that pulses once. */
reg reset = 0;
initial begin output [WIDTH-1 : 0] out;
# 17 reset = 1; input clk, reset;
# 11 reset = 0;
# 29 reset = 1; reg [WIDTH-1 : 0] out;
# 11 reset = 0;
wire clk, reset;
# 100 $stop;
end
always @(posedge clk)
/* Make a regular pulsing clock. */ out <= out + 1;
reg clk = 0;
always #5 clk = !clk; always @reset
wire [7:0] value;
if (reset)
counter c1 (value, clk, reset); assign out = 0;
else
initial deassign out;
$monitor("At time %t, value = %h (%0d)",
$time, value, value); endmodule // counter
endmodule // counter_tb
Testbench
•  Compiling modules
•  Running testbench
•  Ending simulation
–  type finish and hit Enter
Perspective •  Waveform simulators + viewers:
Perspective
•  Other HDL (VHDL):

Lecture #12: Verilog: From Nand To Tetris

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Lecture #12:

• History of hardware design languages

Slides adapted from UCSD CSE 141L – Taylor

Printed circuit board 102

HDL = Hardware Description Language 10

Behavioral Simulate 107

A bit can take on one of four values

An X bit might be a 0, 1, Z, or in transition. We can set

wire [15:0] instruction; Absolutely no

(readability) Decimal literals

We’ll learn how to Decimal

• Verilog is a big language with many

Ports must have a

module adder( A, B, cout, sum );

ANSI C Style Verilog-2001 Syntax

module adder( input [3:0] A, B,

module adder( input [3:0] A, B,

Connecting ports by name (compact)

FA fa0 Connecting ports by name

wire t0, t1;

The order of these continuous

// Four input multiplexer If input is

always @( a or b or c or d or sel ) //could use always @(*)

The order of these procedural

reg out; reg out;

wire [WIDTH-1:0] out, t0, t1;

assign t0 = (sel[1]? c. : a);

module FF (input clk, input d,

What is the difference?

module register#(parameter WIDTH = 1)

always @( posedge clk )

Do they behave the same?

Register Describes how data flows

Auto Place + Route

Verilog Operators verilog_one_day1.html#Data_Type

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•  History of hardware design languages

•  Verilog is a big language with many

assign t0 = (sel[1]? c. : a);