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IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS
A Low-Voltage Radiation-Hardened 13T SRAM
Bitcell for Ultralow Power Space Applications
Lior Atias, Student Member, IEEE, Adam Teman, Member, IEEE, Robert Giterman, Student Member, IEEE,
Pascal Meinerzhagen, Member, IEEE, and Alexander Fish, Member, IEEE
Abstract— Continuous transistor scaling, coupled with the
growing demand for low-voltage, low-power applications,
increases the susceptibility of VLSI circuits to soft-errors,
especially when exposed to extreme environmental conditions,
such as those encountered by space applications. The most
vulnerable of these circuits are memory arrays that cover large
areas of the silicon die and often store critical data. Radiation
hardening of embedded memory blocks is commonly achieved
by implementing extremely large bitcells or redundant arrays
and maintaining a relatively high operating voltage; however,
in addition to the resulting area overhead, this often limits
the minimum operating voltage of the entire system leading to
significant power consumption. In this paper, we propose the
first radiation-hardened static random access memory (SRAM)
bitcell targeted at low-voltage functionality, while maintaining
high soft-error robustness. The proposed 13T employs a novel
dual-driven separated-feedback mechanism to tolerate upsets
with charge deposits as high as 500 fC at a scaled 500-mV supply
voltage. A 32×32 bit memory macro was designed and fabricated
in a standard 0.18-µm CMOS process, showing full read and
write functionality down to the subthreshold voltage of 300 mV.
This is achieved with a cell layout that is only 2× larger than
a reference 6T SRAM cell drawn with standard design rules.
Index Terms— Critical charge, low voltage, radiation effects,
radiation hardening, single-event upset (SEU), soft errors,
space applications, static random access memory (SRAM),
subthreshold, ultralow power (ULP).
I. I NTRODUCTION
P OWER dissipation is one of the most important aspects
of current nanoscale VLSI design. Ultralow power (ULP)
operation is of particular importance in VLSI chips for space
applications, where available energy resources are limited.
Future small, low-cost satellites have an even lower power
budget, as the total satellite weight is often reduced by
restricting the use of heavy batteries and power supplies. The
most efficient way to achieve ULP operation in integrated
Manuscript received July 28, 2015; revised November 27, 2015; accepted
January 6, 2016. This work was supported by the Tashtiyot Program through
the Israeli Ministry of Science.
L. Atias, R. Giterman, P. Meinerzhagen, and A. Fish are with Emerging
Nanoscaled Integrated Circuits and Systems Laboratories, Faculty of Engi-
neering, Bar-Ilan University, Ramat Gan 5290002, Israel (e-mail: lioratias25@
gmail.com; robertgi316@gmail.com; pascal.meinerzhagen@gmail.com;
alexander.fish@biu.ac.il).
A. Teman was with the Telecommunications Circuits Laboratory, Institute
of Electrical Engineering, Swiss Federal Institute of Technology Lausanne,
Lausanne 1015, Switzerland. He is now with Emerging Nanoscaled Integrated
Circuits and Systems Laboratories, Faculty of Engineering, Bar-Ilan
University, Ramat Gan 5290002, Israel (e-mail: adam.teman@biu.ac.il).
Color versions of one or more of the figures in this paper are available
online at http://ieeexplore.ieee.org.
Digital Object Identifier 10.1109/TVLSI.2016.2518220
1063-8210 © 2016 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission.
See http://www.ieee.org/publications_standards/publications/rights/index.html for more information.
1
circuits is to aggressively reduce the supply voltage (VDD)
and operate all components of the chip in the near-threshold
or subthreshold region [1], [2], thereby significantly reduc-
ing both static and dynamic power consumption. However,
in addition to the well-known challenges of a low-voltage
circuit design, such as increased delay, sensitivity to process
variations, and temperature fluctuations, low-voltage circuits
are much more susceptible to radiation effects than circuits
powered at nominal supply voltages [3].
Soft errors or single-event upsets (SEUs) caused by
radiation strikes are the primary causes of failure in VLSI cir-
cuits operating within a highly radiating environment. Accord-
ingly, maintaining data integrity in light of SEUs has become
an integral aspect of memory cell design [4]. Soft errors
occur when an energetic particle hits and passes through a
semiconductor material, potentially causing a bit flip in the
memory cell [5], [6]. The energetic particle frees electron–
hole (e–h) pairs along its path in the material as it loses
energy. When the particle hits a reverse-biased p-n-junction,
such as a transistor diffusion-bulk junction, the injected charge
is transported by drift and causes a transient current pulse that
changes the node voltage. Data loss occurs when the collected
charge (Q coll ) exceeds the critical charge (Q crit ) that is stored
in the sensitive node. The charge deposited by a particle strike
can be calculated from the integral of the transient current
pulse, and Q crit is defined as the minimum charge deposited
in a sensitive node that results in a memory bit flip [7].
SEUs and other similar single-event effects (SEEs) are often
considered when designing for space applications and other
high-radiation environments. However, due to the reduction
of Q crit with technology scaling [8], SEUs can also occur
in standard terrestrial environments at nonnegligible rates [9].
Architectural solutions, such as error correction coding and
triple modular redundancy (TMR) [10], [11], are often not
effective for small arrays in ULP systems operated at low
supply voltages, due to their high complexity and the resulting
performance penalty. Technology solutions, such as silicon-on-
insulator and other process techniques, can improve the data
reliability but do not entirely solve the SEE problems, and
often high volume manufacturing is not feasible [12]. Previ-
ously proposed bitcell solutions, such as the Dual Interlocked
storage Cell (DICE) [13], are designed for superthreshold
operation and fail when operated at low voltages.
In this paper, for the first time, a radiation tolerant bitcell,
specifically designed for low-voltage operation, is proposed.
The 13T dual-driven separated-feedback bitcell employs
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2 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS
several novel techniques to achieve robust SEU suppression,
and is shown to tolerate upsets with charge deposits as
high as 500 fC when operated at a scaled 500-mV supply
voltage. Careful layout considerations were incorporated to
further improve multiple-node strikes, while maintaining a
unit cell size that is only 2× larger than a standard 6T static
random access memory (SRAM) bitcell, implemented in the
same 0.18-µm CMOS process. Extensive dynamic and static
analyses were carried out to prove functionality and upset
tolerance. Silicon measurements of a 32 × 32 (1 kb) memory
macro show full functionality down to 300 mV.
The rest of this paper is organized as follows. Section II
presents the issue of SEUs in SRAM cells. Section III
describes the design and architecture of the 13T bitcell.
In Section IV, the radiation tolerance of the proposed
bitcell is described, based on a unique self-correction mecha-
nism. Section V presents the considerations in constructing
the bitcell layout, followed by test chip measurements in
Section VI. Section VII concludes this paper.
The contributions of this paper are as follows.
1) The proposed radiation-hardened bitcell is a pioneer
solution for embedded memories in low-power space
applications.
2) Implementation of SRAM arrays based on the proposed
bitcell reduces area and power consumption by 30%
compared with the common TMR approach.
3) The proposed solution shows high stability under
varying voltage and process parameter variations, an out-
standing advantage over the conventional 6T SRAM cell.
4) High-radiation tolerance is achieved under scaled
supply voltages, into the subthreshold region.
5) The novel dual-driven separated-feedback mechanism
is introduced and implemented, in order to improve the
bitcell robustness.
II. S TANDARD SRAM U NDER SEUs
SRAM blocks occupy the majority of the chip area
and are the primary contributors to leakage power in
many modern systems, including those intended for space
applications [14]–[16]. These trends lead to two major
conclusions. First, due to their static power consumption,
scaling the supply voltage of the SRAM macros is an efficient
method to reduce total chip power. Second, the probability of
a radiation strike on an SRAM bitcell is relatively high due
to the large area that the SRAM core occupies. Therefore,
SRAM soft-error mitigation has become essential for robust
system design.
The conventional 6T SRAM memory cell, shown
in Fig. 1(a), utilizes an active feedback loop between two
cross-coupled inverters in order to retain its stored data value.
This structure of the SRAM cell is very sensitive to SEUs,
as any upset that causes one of the data nodes to cross the
switching threshold of the adjacent inverter will result in a bit
flip. When operating at low voltages, the switching threshold
decreases, thereby increasing the soft-error susceptibility of
the circuit.
To demonstrate an SEU causing a failure in 6T SRAM
bitcell, the following example will assume that an energetic
Fig. 1. (a) Conventional 6T SRAM cell. (b) Example of an SRAM bit flip
caused by an SEU.
particle strikes a circuit storing a logic 1 (Q = VDD and
Q B = 0 V). If the particle strikes the drain of the cutoff
pMOS transistor, M3, charge will be generated, temporarily
changing the state of Q B. For notation purposes, we will refer
to this type of positively charged strike as a 0 to 1 upset at
node Q B, as opposed to a negatively charged strike, which
we will refer to as a 1 to 0 upset at this node. Before the
deposited charge can be evacuated to the power supply through
the conducting transistor of the feedback inverter (M1), the
feed-forward inverter (M2 and M4) switches and discharges Q.
This, in turn, enforces the wrong state at Q B, thereby latching
the error into the memory cell, as shown in Fig. 1(b).
The amount of charge needed in order to exceed Q crit is
two orders-of-magnitude smaller than the charge that can be
deposited by an energetic particle strike in space. Since Q crit
decreases with both voltage and technology scaling, both
of these trends impair the SEU tolerance of the SRAM.
Therefore, the typical cross-coupled inverter structure cannot
achieve sufficient radiation tolerance under low supply
voltages. Considering static-noise margin as a baseline metric
for measuring the stability of an SRAM cell [17], simulations
show that a typical 6T bitcell implemented in a 0.18-µm
CMOS process and operated at 500 mV has ∼190 mV of
margin. For this margin, a deposited charge of ∼3 fC can
already cause a bit failure. However, the charge generated
by a particle in space can reach up to several hundreds
of femtocoulomb [4]. To overcome particle strikes of this
magnitude, an alternative cell topology must be considered.
III. P ROPOSED 13T R ADIATION T OLERANT B ITCELL
A. Bitcell Design
SRAM design for low-voltage operation has become
increasingly popular in the recent past. Various bitcell designs
and architectural techniques have been proposed to enable
operation deep into the subthreshold region [15], [18]–[21].
These designs generally incorporate the addition of a number
of transistors into the bitcell topology, compared with
the baseline 6T SRAM bitcell, trading off density with
robust, low-voltage functionality. However, these bitcells were
designed for operation under standard operating environments,
and thereby, do not provide sufficient robustness to SEUs
under high-radiation conditions. In addition, the design
architecture of these cells is based on the standard 6T cell;
therefore, the 6T cell has the same hardening ability to most,
if not all, these unprotected cells. As shown in Section II,
the radiation hardening ability of the 6T cell is extremely low,
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ATIAS et al.: LOW-VOLTAGE RADIATION-HARDENED 13T SRAM BITCELL
Fig. 2. Schematic of the proposed 13T radiation-hardened bitcell.
especially when compared with radiation hardening solution
designs.
The proposed bitcell is specifically designed to enable
robust, low-voltage, ULP operation in space applications
and other high-radiation environments. This is achieved by
employing a dual-feedback, separated-feedback mechanism
to overcome the increased vulnerability due to supply voltage
scaling. The schematic representation of the proposed 13T bit-
cell is shown in Fig. 2. The storage mechanism of this circuit
comprises five separate nodes: Q, Q B1 , Q B2 , A, and B,
with the acute data value stored at Q. This node is driven by
a pair of CMOS inverters made up of transistors N3, P3, N4,
and P4 that are, respectively, driven by the inverted data level,
stored at Q B1 and Q B2 . Q B1 and Q B2 are, respectively,
driven to VDD or GND through devices P1, P2, N1, and N2
that are controlled by the weak feedback nodes A and B that
are connected to Q through a pair of complementary devices
(P5 and N5) gated by Q B2 . By driving the acute data level
by a pair of equipotentially driven, but independent, inverters,
a strong, dual-driven feedback mechanism is applied with
node separation for SEU protection. This setup effectively
protects Q from an upset, while achieving a high critical
charge at node Q, as shown in Section IV.
B. Storage Mechanism (Hold)
The proposed 13T bitcell features two stable states, repre-
senting a logic 1 and a logic 0, defined as the voltage level at
node Q. The ON / OFF states of the devices and the resulting
voltage state at the internal nodes are shown in Fig. 3. Similar
to a standard cross-coupled inverter structure, inverted voltage
levels are held at the internal data nodes. Starting with the
logic 1 state [Fig. 3(a)], the low level at Q B2 enables Q to
charge A to VDD through P5, thereby cutting off P1 and P2 and
eliminating any pull-up currents to Q B1 and Q B2 . Leakage
currents from the strongly driven Q node through N5 charge
node B, thereby turning ON N1 and N2 and enabling a
3
Fig. 3. Stable states of the 13T bitcell. For simplicity, devices N6–N8 were
omitted from this figure.
discharge path to assist in holding Q B1 and Q B2 at 0. Note
that both nodes A and B are driven to a predetermined level
during the write operation, as described below, and therefore
are not reliant on the aforementioned leakage currents to set
the initial storage level of the cell.
An almost symmetric process occurs in the logic 0 state,
as shown in Fig. 3(b). In this case, Q B2 is high, allowing B
to discharge through N5 to Q and cutoff the pull-down paths
from Q B1 and Q B2 through N1 and N2, respectively. Any
charge stored at node A will leak through P5 to Q, enabling
pull-up paths through P1 and P2 to Q B1 and Q B2 in order to
replenish any charge lost at these nodes.
C. Inherent SEU Tolerance
Two basic principles provide the proposed bitcell with
inherent SEU tolerance.
1) The data are read out from node Q, such that any
temporary upset on other nodes can be tolerated.
2) The assisting nodes are designed with redundancy
to ensure that any upset will be mitigated by the
other nodes.
When a radiation strike causes a value change on any node
of the bitcell, the other four internal nodes are designed, so
that the state change at this node cannot flip the cell and the
disruption is suppressed within a deterministic recovery time.
For example, an upset at Q will quickly be suppressed through
the dual-driven mechanism created by the internal inverters.
Due to their separated nature, upsets at Q B1 and Q B2 will
not be able to change the state at Q and will return to their
original state. Detailed analysis of these disruptions, as well
as every other possible node upset, is provided in Section IV.
In addition, careful layout positioning considerations were
taken to protect the bitcell from multiple-node upsets (MNUs),
as described in Section V.
D. Write Operation
Standard SRAM topologies, such as the 6T bitcell, write
data by driving the new level directly into the storage nodes,
and therefore are required to overcome the circuit’s strong
internal feedback. In contrast to this method, the proposed cell
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4 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS
Fig. 4. Write stability demonstrated through 3-D phase portraits for both
write operations.
achieves writes by driving the weak feedback nodes (A and B),
thereby removing much of the ratioed contention, inherent to
direct access. A pair of write access transistors (N6 and N7)
connect a unified write bitline (WBL) to nodes A and B. These
devices are controlled by a write wordline (WWL), such that
when WWL is raised, A and B are pulled toward the level
driven upon WBL. This virtual connection between A and B
creates inverters out of the transistor pairs of N1, P1 and
N2, P2, driving Q B1 and Q B2 to the opposite level of WBL.
Accordingly, the written data level is driven back to Q through
the dual-driven feedback inverters, bringing the cell to a stable
state.
In order to demonstrate write stability of the proposed
bitcell, Fig. 4 shows the 3-D phase portraits of both types
of write operations (write 0 and write 1) with VDD = 500 mV.
These plots were assembled by initiating a write opera-
tion under the assumption of any given initial state in the
(Q B1 , Q B2 , and Q) state space. Write stability is achieved
when only a single stable output state is possible for any
initial condition, or more clearly, when all vectors converge
to the same point in the state space. This is the case for
both operations—the write 1 operation [Fig. 4(a)] converges to
(0, 0, and 0.5 V), and the write 0 operation [Fig. 4(b)]
converges to (0.5, 0.5, and 0 V), as required. Other than
the fact that this characteristic ensures a successful write
operation, it is also important in case of a particle strike during
the write access, as the write will still succeed, even though
Fig. 5. Statistical MC simulations of writing 0 to cell 1 and 1 to cell 2 on
a postlayout netlist.
Fig. 6. Distribution of write margin according to the WBL sweep method.
1000 MC samples were taken at VDD = 500 mV.
the strike will move the cell to a different point in the state
space.
Writeability of the cell is further shown with dynamic stabil-
ity simulations and write margin distribution according to the
WBL sweep method [22]. Dynamic stability is shown in Fig. 5,
showing successful write 0 and write 1 operations applied to
two separate cells and simulated over 1000 Monte Carlo (MC)
samples on a postlayout netlist. The average duration of these
write operations is 8 ns for write 0 and 15 ns for write 1 with
VDD = 500 mv. The write margin distribution of the cell at
this operating voltage is shown in Fig. 6 with a very robust
mean of 219 mV and a standard deviation of 12.4 mV.
E. Read and Half Select
The proposed 13T bitcell features single-ended readout
through the read access transistor (N8). This device is
controlled by a separate read wordline and connected to a
column-shared read bitline that is precharged prior to the
read operation and conditionally discharged, depending on
the voltage stored at Q. Due to the dual-driven feedback that
drives Q to its stable value, this read operation is both more
robust and faster than the read operation of standard SRAM
bitcells. Read failures in 6T SRAM cells occur when the
access transistor is stronger than the pull-down transistor due
to local variations. However, the proposed cell employs a pair
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ATIAS et al.: LOW-VOLTAGE RADIATION-HARDENED 13T SRAM BITCELL
Fig. 7. Half-select functionality for both, storing 1 (cell 1) and
storing 0 (cell 2), cases.
of pull-down transistors (N3 and N4), which significantly
decrease the probability of such a read failure, enabling robust
operation at low voltages. In addition, these two devices also
provide a lower resistance pull-down path to achieve a faster
bitline discharge. The separated read and write ports also
provide two-ported functionality, often required in memory
macros, such as those used for register files.
The majority of the previously proposed bitcells fea-
turing a single-ended read, such as the standard two-port
8T SRAM cell, suffer from susceptibility to half-select fail-
ures. Half-select situations occur during write operations when
only some of the bits that share the same wordline are to be
written. In a standard 6T SRAM cell that shares wordlines
and bitlines for both read and write operations, biasing the
bitlines for a read operation ensures that the cell will not
be written to. However, as read margin is often the limiting
factor in supply voltage scaling, single-ended readout is often
used as an alternative to the standard differential readout.
This either leaves the cell susceptible to half-select failures
or eliminates the option of partial row writes—a real problem
if bit-interleaving is desired for minimizing the probability of
multiple-bit failures.
In the case of the proposed cell, a half-select situation will
indeed occur during a partial row write. However, due to
the strong, dual-driven feedback mechanism and the indirect
write operation through the weak feedback nodes, the cell
provides robust half-select stability. During a bit-masked write
operation, the tristate WBL drivers of the nonselected cells
are set to their high-impedance state, floating the bitlines. In a
worst case situation, during which the nonselected WBL is
driven to the opposite level than that stored in the cell prior
to the half-select cycle, the floating charge will be discharged
through Q without causing a bit flip. This is shown in Fig. 7
for 1000 MC samples at VDD = 500 mV. Fig. 7 shows two
cells in the same row, storing 1 and 0, respectively, under
worst case half-select situations. Each WBL was initialized at
the voltage opposite to that stored in its bitcell, and at the
onset of a write operation (rising-edge of WWL), the WBLs
were floated. In all cases, only a slight disrupt can be seen
on Q, and this is quickly suppressed as the bitline charge is
discharged through A and/or B to Q.
To summarize and demonstrate the cell operation described
in this section, representative write, read, and upset
suppression events are shown in Fig. 8 with a 500-mV supply
5
voltage. In this scenario, a 1 is written into a cell initially stor-
ing a 0, followed by a 1-pC particle strike that discharges Q to
a negative voltage. This upset is quickly mitigated, such that
the subsequent read operation outputs the correct data. A sim-
ilar sequence follows with a 0 written into the cell, followed
by a 0 to 1 upset at Q B1 and a subsequent read operation.
This strike is also mitigated, resulting in a correct readout.
IV. SEU T OLERANCE
A. Disrupt Modeling
The proposed 13T bitcell was designed for robust, upset
tolerant operation in a high-radiation environment, such as that
encountered by space applications. When a particle strike, the
characteristic of such an environment, passes through a semi-
conductor material, a disrupt occurs due to the drift current
of the generated e–h pairs in a reverse-biased p-n junction.
If the particle hits an unbiased junction, the generated e–h
pairs will spontaneously recombine and not induce a current
pulse due to the absence of an electric field. However, a strike
on a reverse-biased junction causes a transient current [I (t)]
at the connected node, characterized by a fast rise time and
a gradual fall time. This current can be modeled according to
the double-exponential model [23]
 t 
Q coll −
e t f − e− tr
t
I (t) = (1)
t f − tr
where Q coll is the charge collected due to the particle strike,
tr is the rise time, and t f is the fall time. Q coll depends on
the type of the ionizing particle, trajectory, energy value, and
impact location. The technology-dependent rise and fall times
were taken as 10 and 200 ps, respectively, for the considered
0.18-µm process [3]. The critical charge is calculated from
the numerical integration of the injected current pulse that
causes a bit flip. Section IV-B describes the describes the
bitcell tolerance to a 500-fC disruption at each cell node for
relevant standby states.
B. Disrupt Tolerance
The multiple internal nodes of the proposed 13T circuit
and the possibility of strikes of both positive and negative
polarities require an analysis of each type of strike to evaluate
disrupt tolerance. As previously mentioned, a correct readout
only requires the data to be stable at node Q, and therefore,
it is sufficient to consider the voltage at this node for such an
evaluation. Fig. 9 shows the reaction of the storage node, Q,
to particle strikes at each of the internal nodes of the proposed
bitcell. A typical 500-fC strike with VDD = 500 mV is shown
for every node, and where applicable, the reaction to both
positive and negative charge strikes is shown. Note that there
are no plots shown for a negative upset at node A or a positive
upset at node B, as there is no reversed-biased p-n junction
connected to these nodes in the respective standby states. The
insets of each subfigure show the results of 1000 MC samples
for this type of particle strike, all resulting in a successful
recovery. The recovery mechanisms that successfully enable
the cell to recover and retain its initial state for every possible
upset are described hereafter.
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6 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS
Fig. 8. Subsequent write-upset-read events, demonstrating quick cell recovery. The waveforms were plotted for a 500-mV supply voltage with the particle
energies of 1 pC.
1) 0 to 1 Upset at Q: Following a positive particle
strike at node Q while holding 0 [Fig. 9(a)], both Q B1
and Q B2 remain high, quickly discharging the injected
charge through N3 and N4. During this upset event, B starts
to charge through N5, enabling N1 and N2 to discharge
Q B1 and Q B2 . However, since P5 remains in cutoff, A stays
low, causing P1 and P2 to successfully combat the discharge
of Q B1 and Q B2 until the injected charge to Q has been
discharged.
2) 1 to 0 Upset at Q: Following a negative particle strike
at node Q while holding 1 [Fig. 9(b)], both Q B1 and Q B2
remain low, quickly replenishing the lost charge at Q through
P3 and P4. During upset event, A starts to discharge through
P5, enabling P1 and P2 to charge Q B1 and Q B2 . However,
since N5 remains in cutoff, B stays high, causing N1 and N2
to successfully combat the charge of Q B1 and Q B2 until Q
has fully recovered. However, note that as shown in Fig. 8,
a 1 to 0 upset at Q causes node B to switch from 1 to 0.
This phenomenon occurs due to a higher than typical energetic
particle strike, which was intentionally used in this simulation
to demonstrate the cell recovery capability. In cases of highly
energetic particles, the double-exponential model of (1) can
often cause the voltage to drop below 0. In this example,
the voltage of Q drops below 0, and therefore, even though
the gate potential of N5 remains at 0, transistor N5 is now
conducting, since the difference between the gate potential and
the drain terminal of this transistor (node Q) is greater than
the threshold voltage of N5. However, even in this worst case
scenario of a drastic voltage drop in the storage node, Fig. 8
shows that the proposed cell is resilient and able to recover.
3) 0 to 1 Upset at Q B1 : A positive strike at Q B1 in a hold 1
state [Fig. 9(d)] will enable N3 to attempt to discharge Q.
However, P4 will remain ON, as Q B2 is not affected, thereby
limiting the temporary voltage drop at Q. The 0 level stored
at Q B2 also keeps N5 cutoff N5, maintaining the level of B
high. Therefore, N1 is able to discharge the current that was
injected into Q B1 , as P1 is cutoff due to the high level stored
on A.
4) 1 to 0 Upset at Q B1 : A negative strike at Q B1 in a
hold 0 state [Fig. 9(c)] will enable P3 to attempt to charge Q.
Combating this operation is N4, limiting the temporary voltage
rise at Q, as Q B2 is not affected and retains its high state.
In addition, the 1 level stored at Q B2 cuts off P5, such that
the level of A remains low. Therefore, P1 is able to replenish
the lost charge at Q B1 , while N1 is cutoff due to the low level
stored at B.
5) 0 to 1 Upset at Q B2 : A positive strike at Q B2 in a hold 1
state [Fig. 9(f)] will enable N4 to attempt to discharge Q.
Combating this operation is P3, limiting the temporary voltage
fall on Q, as Q B1 is not affected. Since Q B2 switches its
value to 1, it cuts off P5, maintaining the level of A high to
ensure that P1 and P2 remain close to keep Q B1 and Q B2
low. During this operation, B starts to discharge through N5,
closing N1 and N2. Since the two inverters are combating
each other, B would not completely close N1 and N2, and
this results a quickly discharge of Q B2 back to 0. Since Q B1
was always at 0, Q will charge back to 1.
6) 1 to 0 Upset at Q B2 : A negative strike at Q B2 in a
hold 0 state [Fig. 9(e)] will enable P4 to attempt to charge Q.
Combating this operation is N3, limiting the temporary voltage
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ATIAS et al.: LOW-VOLTAGE RADIATION-HARDENED 13T SRAM BITCELL 7

Fig. 9. Behavior of node Q under all possible SEUs with charge deposit of 500 fC and VDD = 500 mV. Insets: results of 1000 MC simulations.

rise on Q, as Q B1 is not affected. Since the value of Q B2 ensure that N1 and N2 remain close keeping the charge stored
changed to 0, A starts to charge to 1 through P5 closing at Q B1 to successfully combat the charge of Q by evacuating
P1 and P2. However, since N5 is in cutoff, B stays low, to the injected charge through N3.
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8 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS

TABLE I
Q crit OF B ITCELL N ODES

7) 1 to 0 Upset at A: Following a negative particle strike

at node A while holding 0 [Fig. 9(g)] will cut off P1 and P2.
However, both Q B1 and Q B2 remain high, and therefore,
P5 stays cutoff to prevent this upset from affecting Q. The
voltage at Q is only able to rise up to 70 mV and is quickly Fig. 10. Bitcell behavior under 1 to 0 SEUs at node Q with varying charge
deposits under (VDD = 500 mV).
discharge through N3 and N4. The cell data are always
available during this upset event. A would start to discharge
due to leakage currents through P5, reenabling P1 and P2 to
keep Q B1 and Q B2 charged. B is not affected during this
upset.
8) 0 to 1 Upset at B: Following a positive particle strike at
node B while holding 1 [Fig. 9(h)], N1 and N2 will both be
cutoff. However, both Q B1 and Q B2 remain low, and there-
fore, N5 stays cutoff, preventing this upset from affecting Q.
The voltage at Q drops to a lowest limit of 200 mV, and
its level is quickly replenished through P3 and P4. After this
upset event, B would start to charge due to leakage currents
through N5, reenabling N1 and N2 to keep Q B1 and Q B2
discharged. A is not affected during this upset.

C. Recovery Time and Critical Charge

Two important parameters to evaluate the tolerance of a
bitcell for particle strikes when operating in a high-radiation
environment are recovery time and critical charge. The recov-
ery time is the time it takes Q to return to its correct readable
data value following a particle strike, while critical charge, as
previously defined, is the minimum charge required to cause
a bit flip. Whereas a particle strike of a magnitude larger
than the critical charge is destructive and will lead to an
incorrectly stored data level, recovery time only characterizes a
temporal state, but can lead to an access failure if a subsequent
read is performed in close proximity to a disrupt. The joint
consideration of both parameters is essential to ensure reliable
functionality under SEUs.
The recovery time of the proposed bitcell was extracted
from the simulations shown in Fig. 9 for each one of the
possible node upsets. The resulting mean recovery time was
found to be approximately two orders-of-magnitude shorter
than the previously proposed DICE solution under the same
supply voltage [13]. Similarly, Q crit was extracted for each
node and disrupt polarity, as shown in Table I. Accordingly,
Q crit of the bitcell can be defined as 500 fC, the minimum
extracted value. In comparison with other bitcell solutions,
designed in the same 0.18-µm CMOS process, Q crit of the
proposed circuit is two orders-of-magnitude larger than other
SRAM solutions [24]–[27], and is at the same order-of-
magnitude as the DICE solution operated at a 500-mV supply
voltage.
To demonstrate the reaction to various induced charge
magnitudes, Fig. 10 shows positive strikes at node Q with
Fig. 11. Behavior of node Q under a particle strike on node Q B2 in 65-nm
technology. Results of 1000 MC simulations.
several particle energies, showing tolerance to charge deposits
as high as 1 pC under a 500-mV supply. This plot also shows
that the recovery time increases with the particle energy. Fig. 8
also shows the reaction to a 1-pC positive strike—first at
node Q, and subsequently at node Q B. This example clearly
shows the quick recovery of the cell, enabling a correct readout
during the following cycle. Note that the cell is not sensitive
to SEUs during a write operation, since at this time, the access
transistors are conducting and the values at A and B are
strongly held by the bit lines, as described in Section III.
The process technology node of the proposed cell was
chosen according to the specifications and requirements of
the targeted space and military applications, which most
often require very mature technologies. However, the proposed
bitcell architecture is fully compatible with technology scaling,
as shown in Fig. 11 for a 65-nm CMOS technology. Fig. 11
shows the recovery of node Q in the worst case scenarios
of a particle strike on node Q B2 . The robustness of the cell
under process variations, demonstrated through statistical MC
simulations, suggests that its radiation hardening capabilities
are maintained under technology scaling.
 This article has been accepted for inclusion in a future issue of this journal. Content is final as presented, with the exception of pagination.
ATIAS et al.: LOW-VOLTAGE RADIATION-HARDENED 13T SRAM BITCELL
Fig. 12. Bitcell layout.
V. L AYOUT C ONSIDERATIONS
Standard SRAM bitcells, intended for high-density integra-
tion, give the highest priority to minimum area layout, often
trading off size for stability and performance. However, when
designing a cell for high-radiation environments, silicon area
often takes a step back in favor of stability and soft-error
suppression. Accordingly, one of the most simple and efficient
solutions that has been proposed to mitigate SEUs is the TMR
solution, which utilizes three identical memory arrays and a
voting circuit to decide on the correct readout. This solution
clearly comes at a high area penalty—at least tripling the size
of a standard SRAM block. Ultimately, such a heavy area
overhead limits the memory integration density. Therefore, in
the design of the proposed circuit, one of the goals was to
provide a significant area benefit, as compared with a similar
sized TMR block.
The proposed layout for the 13T bitcell is shown in Fig. 12,
presenting a unit size of 7.5 µm × 4 µm, which is approxi-
mately 2× larger than a standard 6T SRAM cell in the same
technology process (0.18 µm) designed with standard rules.
Note that the majority of industry standard SRAM macros are
based on pushed-rule bitcells, which provide a significantly
reduced cell area. However, this also results in increased
sensitivity to soft errors, including the MNU rate of the cell,
making a pushed-rule bitcell a very bad candidate for radiation
hardening. Therefore, the vast majority of radiation-hardened
circuits are designed with standard rules.
The reduced size of the proposed cell in comparison with the
TMR solution was achieved by implementing a single n-well
9
per cell, placing all pMOS devices in a single row and sharing
diffusion through abutment, wherever possible. However, node
positioning had to be considered, as well, in order to reduce
the probability of multiple-node disrupts.
A single high-energy particle strike can disrupt several
nodes simultaneously, especially if the proximity between the
nodes is small. However, as previously explained, a transient
current pulse will only occur if the particle hits a reverse-
biased p-n junction. Therefore, by separating nodes that may
be simultaneously reverse-biased, the probability of a bitcell
failure can be significantly reduced. The layout of the proposed
bitcell was designed, such that every pair of these sensitive
nodes is separated either by distance or by placing an unbiased
junction in between them. For example, in a logic 1 state,
the two sensitive nodes, Q B1 and Q B2 , in the pMOS row at
the top of the unit cell are equal to 0; hence, both nodes are
reverse-biased. Therefore, an unbiased junction was positioned
between them for protection. If a particle hits the Q B1 pMOS
junction (top left in Fig. 12), the unbiased diffusions of transis-
tors P3 and P4, connected to VDD and to Q, respectively, will
block this upset from reaching the second sensitive reverse-
biased node, Q B2 . The same separation was also implemented
for the sensitive nodes in the nMOS row at the bottom of the
cell, since at any given time, only one of the storage nodes,
Q or Q B1 /Q B2 , will be reverse-biased. As such, for any hold
state of the cell, a sensitive node is protected by an unsensitive
node. In addition, nodes A and B are separated by distance
from the storage nodes.
While the cell functionality and radiation hardening
described in Section IV can be achieved with minimum-sized
transistors, the layout considerations and design, described
above, leave room for slight increases in transistor widths
without resulting in an overall increase in a cell area. This
feature was exploited to reduce the cell recovery time by
upsizing transistors P3 and N2, as shown in Fig. 12.
VI. T EST C HIP I MPLEMENTATION AND M EASUREMENTS
A 32 × 32 bit (1 kb) memory macro based on the proposed
cell was designed and integrated into a 0.18-µm test chip.
All devices were implemented with standard VT transistors to
provide complete logic process compatibility. The test chip
was designed to enable three primary test modes: 1) full,
at speed testing using an integrated built-in-self-test (BIST);
2) complete array control through a serial scan chain config-
uration; and 3) single-cycle external direct access to a portion
of the array. The test chip also included a 2-kb compiled
SRAM for data comparison and several other test components.
The BIST incorporates a finite-state machine for rigorous,
at-speed testing, utilizing an on-chip SRAM for comparison
of the data written to the custom array with the subsequent
readout values. These three test configurations were used to
test the functionality of the array and provide the presented
measurement data.
A micrograph of the bonded test chip is shown in Fig. 13
along with the layout of the entire chip and an enlarged image
of the 13T array layout. In order to test the cell’s functionality
under scaled voltage supplies, the radiation-hardened SRAM
 This article has been accepted for inclusion in a future issue of this journal. Content is final as presented, with the exception of pagination.
10
Fig. 13. Full chip layout and the 13T cell memory array.
Fig. 14. Combined shmoo plot of the minimal memory supply voltage as a
function of the maximal operating frequency, for 12 measured chips.
array was biased by a separate, low-voltage supply, (M VDD ),
keeping the digital voltage supply (VDD) at a nominal level
to ensure proper functionality of the BIST, compiled SRAM,
and other digital peripheral circuits of the test chip. In order to
test the impact of process variations, 12 dies were measured,
all of which were operated successfully over the full range of
supply voltages, from 300 mV to 1.8 V.
Fig. 14 shows the maximum measured frequency of the
test chips across the range of supply voltages. This result
is emphasized in Fig. 15, showing the average measured
frequency for each supply voltage in black. All measurements
were taken at room temperature. As expected, the performance
exponentially degrades as the voltage is scaled. However,
the array maintains functionality for write and read at
VDD = 300 mV for all packaged test chips. The measurement
of maximum frequency was limited by the test setup and
periphery, which was designed for low-frequency ULP
applications and not optimized for high-speed measurements.
In addition to the area savings of the proposed topology,
as compared with an alternative TMR solution, a significant
improvement is also achieved in static power consumption.
Fig. 16 shows the average leakage power per bit for each
of the packaged test chips with the average consumption
emphasized in black. For comparison, the leakage of a TMR
bit is displayed as a dashed line, consuming approximately
IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS
Fig. 15. Measured frequency versus VDD .
Fig. 16. Measured hold leakage power versus M VDD .
3× higher power than the proposed bitcell across the entire
operating range. This is without taking into consideration the
power of the specialized peripheral circuits that the TMR
solution would require in order to continue to function at such
a low operating voltage.
VII. C ONCLUSION
This paper proposed a 13T SRAM bitcell, designed for
robust, low-voltage, ULP operation in high-radiation envi-
ronments, such as those encountered by space applications.
The proposed circuit displays a novel dual-driven separated-
feedback mechanism to achieve high soft-error tolerance, for
robust operation down to 300 mV. Particle strike suppression
according to the double-exponential model was tested across
statistical MC simulations on a postlayout netlist for every
type of disrupt event, showing tolerance to upsets with the
magnitudes of up to 500 fC at a scaled, 500-mV operating
voltage. Layout techniques were implemented in order to
decrease SEU probability, while maintaining a bitcell area
much smaller than alternative solutions, such as the previously
proposed TMR, resulting in a unit cell area only 2× larger
than a standard 6T bitcell in the same process. A 1-kb test chip
was designed, fabricated, and tested, showing full functionality
over a large range of operating voltages, providing average
leakage power consumption of less than 5 pW per bit at
300 mV—over 3× lower than alternative proposals.
 This article has been accepted for inclusion in a future issue of this journal. Content is final as presented, with the exception of pagination.
ATIAS et al.: LOW-VOLTAGE RADIATION-HARDENED 13T SRAM BITCELL
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Lior Atias received the B.Sc. (magna cum laude)
degree in electrical engineering from Ben-Gurion
University, Be’er Sheva, Israel, in 2013, and the
M.Sc. degree from Ben-Gurion University, in 2014,
as part of a fast-track program for outstanding stu-
dents.
He is currently a Design and Verification Engi-
neer with Mellanox Technologies, Tel Aviv, Israel.
His current research interests include digital radia-
tion hardened circuits design for low-power space
applications, low-voltage embedded memories, and
SRAM design with an emphasis on improved stability.
Adam Teman received the B.Sc. degree in electrical
engineering and the M.Sc. degree from Ben-Gurion
University (BGU), Be’er Sheva, Israel, in 2006 and
2011, respectively, and the Ph.D. degree from the
VLSI Systems Center, BGU, in 2014, under Prof.
A. Fish, as a part of the Low Power Circuits and
Systems Laboratory.
He was a Design Engineer with Marvell Semicon-
ductors, Petah Tikva, Israel, from 2006 to 2007, with
an emphasis on physical implementation. From 2014
to 2015, he was a Post-Doctoral Researcher with
the Telecommunications Circuits Laboratory, École Polytechnique Fédérale
de Lausanne, Lausanne, Switzerland, under a Swiss Government Excellence
Scholarship. In 2015, he joined the Faculty of Engineering, Bar-Ilan Uni-
versity, Ramat Gan, Israel, in 2015, as a Tenure Track Researcher with the
Department of Electrical Engineering and as a Partner with the Emerging
Nanoscaled Integrated Circuits and Systems Laboratories Research Center.
His current research interests include low-voltage digital design, energy-
efficient SRAM, NVM, and eDRAM memory arrays, low-power CMOS image
sensors and low-power design techniques for digital and analog VLSI chips,
energy-efficient digital system implementation, approximate computing, and
significance driven computing for reliability and power optimization. He has
authored over 40 scientific papers and three patent applications, and has
presented excerpts from his research at a number of international conferences.
Dr. Teman was honored with the Electrical Engineering Department’s
Teaching Excellence recognition at Ben-Gurion University in 2010-2012,
and in 2011, he received the Outstanding Project Award at BGU. He
received the Yizhak Ben-Ya’akov HaCohen Prize in 2010, the BGU Rector’s
Prize for Outstanding Academic Achievement in 2012, the Wolf Foundation
Scholarship for Excellence of 2012, and the Intel Prize for Ph.D. Students
in 2013. His doctoral studies were conducted under a Kreitman Foundation
Fellowship. He is also an Associate Editor of the Microelectronics Journal
and a member of the technical and review boards of several conferences and
journals.
Robert Giterman received the B.Sc. degree in
electrical engineering from Ben-Gurion University,
Be’er Sheva, Israel, in 2013, and the M.Sc. degree
from Ben-Gurion University, in 2014, as a part
of a fast-track program for outstanding students.
He is currently pursuing the Ph.D. degree, under
Prof. A. Fish, as part of the Emerging Nanoscaled
Intergrated Circuits and Systems Laboratory at Bar-
Ilan University, Ramat Gan, Israel.
His current research interests include embedded
DRAM design and optimization for low-power and
high-performance operation, SRAM design with an emphasis on improved
stability, error-correction and fault-tolerant circuits, and development of mul-
tilevel embedded memories for use in low-power applications and high-end
processors.
 This article has been accepted for inclusion in a future issue of this journal. Content is final as presented, with the exception of pagination.
12
Pascal Meinerzhagen received the B.Sc., M.Sc.,
and Ph.D. degrees from the École Polytechnique
Fédérale de Lausanne (EPFL), Lausanne, Switzer-
land, in 2014, 2008, and 2006, respectively, all in
electrical engineering, and the joint M.Sc. degree in
micro and nanotechnologies for integrated systems
from Grenoble INP, Grenoble, France, Politecnico di
Torino, Turin, Italy, and EPFL, in 2008.
He was a Post-Doctoral Fellow and a Lecturer
with Bar-Ilan University, Ramat Gan, Israel, in 2014,
where he established the Advanced Digital VLSI
Design course. He is currently a Senior Research Scientist with Intel Laborato-
ries, Intel Corporation, Hillsboro, OR, USA, and a Visiting Lecturer with Bar-
Ilan University. His current research interests are broad, ranging from energy-
efficient and error-resilient circuits and systems in high-performance FinFET
CMOS technologies, to power delivery and power management techniques, to
conventional and emerging memory circuits, to ultralow power VLSI. He has
authored or co-authored two invited book chapters, 27 peer-reviewed journal
articles, and international conference papers, and holds four pending patents.
Dr. Meinerzhagen received an Intel Ph.D. Fellowship and two best paper
nominations. He is a Reviewer of 16 international journals and conferences,
including the IEEE T RANSACTIONS ON C IRCUITS AND S YSTEMS —PART
I, the IEEE T RANSACTIONS ON C IRCUITS AND S YSTEMS —PART II, the
IEEE J OURNAL ON E MERGING AND S ELECTED T OPICS IN C IRCUITS AND
S YSTEMS , and the IEEE Symposia on VLSI Technology and Circuits.
IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS
Alexander Fish received the B.Sc. degree in elec-
trical engineering from Technion–Israel Institute of
Technology, Haifa, Israel, in 1999, and the M.Sc. and
Ph.D. (summa cum laude) degrees from Ben-Gurion
University (BGU), Be’er Sheva, Israel, in 2002 and
2006, respectively.
He was a Post-Doctoral Fellow with the ATIPS
Laboratory, University of Calgary, Calgary, AB,
Canada, from 2006 to 2008. In 2008, he again
joined BGU, as a Faculty Member with the Electrical
and Computer Engineering Department, where he
founded the Low Power Circuits and Systems Laboratory, specializing in low-
power circuits and systems. In 2011, he was appointed as a Head of the VLSI
Systems Center at BGU. In 2012, he joined Faculty of Engineering, Bar-Ilan
University, as an Associate Professor, and the Head of the Nanoelectronics
Track. He also leads new Emerging Nanoscaled Integrated Circuits and
Systems Laboratories. His current research interests include development of
secured hardware, ultralow-power embedded memory arrays, CMOS image
sensors, and high-speed and energy-efficient design techniques. He has
authored over 100 scientific papers in journals and conferences, including
the IEEE J OURNAL OF S OLID S TATE C IRCUITS , the IEEE T RANSACTIONS
ON E LECTRON D EVICES , the IEEE T RANSACTIONS ON C IRCUITS AND
S YSTEMS , and many others. He also submitted 22 patent applications. He
has authored two book chapters.
Prof. Fish is a member of Sensory, VLSI Systems and Applications, and
Bio-medical Systems Technical Committees of the IEEE Circuits and Systems
Society. He was a co-author of papers that won the best paper finalist awards
at the IEEE ISCAS and ICECS conferences. He serves as the Editor in Chief
for the MDPI Journal of Low Power Electronics and Applications and an
Associate Editor of the IEEE S ENSORS , IEEE A CCESS , Microelectronics
and Integration (Elseiver), and VLSI Journals. He also served as a Chair
of different tracks of various IEEE conferences. He was a Co-Organizer of
many special sessions at the IEEE conferences, including IEEE ISCAS, IEEE
S ENSORS , and IEEE conferences.