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 Thesis for the degree of Doctor of Philosophy

Wireless Power Transmission Circuits

for Portable Devices

휴대용 기기를 위한 무선 전력 전송 회로

By

Young-Jin Moon

Hanyang University Graduate School

February 2015
 Thesis for the degree of Doctor of Philosophy

Wireless Power Transmission Circuits

for Portable Devices

Thesis Supervisor: Changsik Yoo

A Thesis submitted to the graduate school of Hanyang

University in partial fulfillment of the requirements for
the degree of Doctor of Philosophy

February 2015

Department of Electronics and Computer Engineering

Hanyang University Graduate School

Young-Jin Moon
 Abstract

Wireless Power Transmission Circuits for Portable Devices

Young-Jin Moon

Department of Electronics and Computer Engineering

Hanyang University Graduate School

Supervisor: Changsik Yoo

For wireless power transmission of mobile and wearable medical devices, this

dissertation presents wireless power receiver, wireless power transceiver, and

wireless power charger. In wireless power receiver for mobile devices, the reverse

leakage current of the active rectifier is prevented by a delay locked loop (DLL)

based delay compensation circuit. The buck converter of the wireless power receiver

operates in the discontinuous-conduction mode at the light load and its switching

frequency is automatically selected according to the amount of the load current to

improve the power efficiency. Also, the bi-directional DC-DC converter has been

developed for a wireless power transceiver which enables a mobile device to receive

and transmit power wirelessly. With the bi-directional DC-DC converter, the form-

factor of the proposed wireless power transceiver can be reduced. And the wireless

power charger has been implemented to charge the battery of the wearable medical

device. The status of the battery can be transmitted to the transmitter by the in-band

communication circuit.

i
 Table of Contents

Abstract ........................................................................................................................ i

Table of Contents ........................................................................................................ii

List of Figures ...........................................................................................................vii

List of Tables .............................................................................................................xii

1. Introduction........................................................................................................... 1

1.1. Motivation ....................................................................................................... 1

1.2. Thesis Organization ........................................................................................ 3

2. Overview of Wireless Power Transmission System ............................................. 4

2.1. Necessity of the wireless power transmission ............................................... 4

2.2. Simplified architecture of the wireless power transmission system ............. 5

3. Design Considerations of the Wireless Power Transmission System Circuit ..... 7

3.1. Wireless power transmitter ........................................................................... 7

3.1.1. Linear power amplifier and switching power amplifier ....................... 7

3.1.2. Class-D power amplifier ..................................................................... 11

3.1.3. Class-E power amplifier ..................................................................... 13

3.2. Wireless power receiver .............................................................................. 13

3.2.1. AC-DC converter of the wireless power receiver .............................. 14

ii
 3.2.2. DC-DC converter of the wireless power receiver .............................. 16

3.2.3. Battery charger ................................................................................... 19

4. Proposed wireless power receiver for mobile devices ...................................... 20

4.1. Motivation of the wireless power receiver for mobile devices ................... 22

4.2. Proposed active rectifier for wireless power receiver for mobile devices .. 24

4.2.1. Sub-circuit design of the proposed active rectifier ............................. 27

4.2.1.1. Phase detector and charge pump .................................................... 27

4.2.1.2. Voltage controlled delay line (VCDL) ........................................... 27

4.2.1.3. Band-gap reference ......................................................................... 30

4.2.1.4. Low-drop-out (LDO) regulator ...................................................... 31

4.2.1.5. Start-up operation ........................................................................... 31

4.3. Proposed buck converter with an automatic load-adaptive switching

frequency selection technique ....................................................................... 32

4.3.1. Necessity and background of the proposed buck converter ............... 32

4.3.2. Proposed load-adaptive frequency selection technique ...................... 34

4.3.3. Sub-circuit design of the proposed buck converter ............................ 42

4.3.3.1. Clock and ramp generator ............................................................... 42

4.3.3.2. DCM detection circuit .................................................................... 43

4.3.3.3. Dead time controller and driving buffer ......................................... 45

iii
 4.3.3.4. Protection circuit ............................................................................ 46

4.4. Measurement results ..................................................................................... 46

4.5. Follow-up research of the wireless power receiver ....................................... 53

5. Proposed Wireless Power Transceiver for Device to Device Wireless Power

Transmission ..................................................................................................... 62

5.1. Necessity of the wireless power transceiver ............................................... 62

5.2. Block diagram of the proposed wireless power receiver ............................ 63

5.3. Proposed bi-directional DC-DC converter .................................................. 65

5.3.1. Circuit design of the proposed bi-directional DC-DC converter ........ 66

5.3.1.1. VIN_HIGHER and VOUT selection circuit ............................................. 67

5.3.1.2. Error amplifier for output regulation voltage ................................. 68

5.3.1.3. Clock and ramp generator ............................................................... 69

5.3.1.4. Protection circuit ............................................................................ 70

5.3.2. Stability of the proposed bi-directional DC-DC converter ................. 70

5.4. Circuit design of the proposed wireless power transceiver ........................... 72

5.4.1. Impedance matching circuit ............................................................... 72

5.4.2. AC-DC converter ................................................................................ 74

5.4.3. Class-E power amplifier ..................................................................... 75

5.4.4. Analog switches .................................................................................. 76

iv
 5.4.5. Battery charger ................................................................................... 76

5.5. Measurement results ................................................................................... 80

6. Proposed Wireless Power Charger for Wearable Medical Devices with In-Band

Communication ................................................................................................. 82

6.1. Motivation of the wireless power charger ................................................... 82

6.2. Proposed wireless power charger IC for a wearable medical devices ........ 83

6.3. Circuit design of the proposed wireless power charger IC ......................... 85

6.3.1. Rectifier .............................................................................................. 85

6.3.2. Battery charger ................................................................................... 85

6.3.3. In-band communication circuit ........................................................... 89

6.3.4. Band-gap reference and low-drop-out regulator ................................ 90

6.3.5. Protection circuit ................................................................................ 91

6.4. Measurement results ................................................................................... 92

7. Conclusions......................................................................................................... 96

References ................................................................................................................. 99

Publications ............................................................................................................. 106

Patents ..................................................................................................................... 110

초록 ......................................................................................................................... 112

v
 List of Figures

Fig. 2.1. Simplified architecture of the wireless power transmission system ........... 5

Fig. 3.1. Basic schematic of the linear power amplifier .......................................... 10

Fig. 3.2. Voltage and current waveforms of the linear power amplifier ................. 10

Fig. 3.3. Basic schematic of the switching power amplifier .................................... 11

Fig. 3.4. Voltage and current waveforms of the switching power amplifier ........... 11

Fig. 3.5. Simplified schematic of the class-D power amplifier ............................... 12

Fig. 3.6. Voltage and current waveforms of the class-D power amplifier ............... 12

Fig. 3.7. Simplified schematic of the class-E power amplifier ................................ 14

Fig. 3.8. Voltage and current waveforms of the class-E power amplifier ............... 14

Fig. 3.9. Schematic of the AC-DC converter .......................................................... 16

Fig. 3.10. Waveforms of the AC-DC converter ...................................................... 16

Fig. 3.11. Various structures of the AC-DC converter ............................................ 17

Fig. 3.12. Basic structures of the power transistors of the buck converter .............. 19

Fig. 3.13. Simplified block diagram of the voltage-mode controlled DC-DC buck

converter .................................................................................................................. 20

Fig. 3.14. Simplified schematic of the (a) switching and (b) linear battery charger IC

................................................................................................................................... 21

Fig. 4.1. Block diagram of the wireless power transmission system ....................... 23

vi
Fig. 4.2. Schematic of the basic active rectifier ...................................................... 24

Fig. 4.3. Timing diagram of the conventional active rectifier ................................. 25

Fig. 4.4. Active rectifier employing the proposed comparator with zero delay ...... 27

Fig. 4.5. Timing diagram of the active rectifier with the proposed comparator with

zero delay ................................................................................................................ 28

Fig. 4.6. Phase detector ........................................................................................... 30

Fig. 4.7. Charge pump ............................................................................................. 30

Fig. 4.8. Voltage controlled delay line .................................................................... 31

Fig. 4.9. Band-gap reference ................................................................................... 32

Fig. 4.10. Low-drop-out regulator ........................................................................... 33

Fig. 4.11. Block diagram of the buck converter with the proposed automatic

frequency selection technique for improved power efficiency ............................... 37

Fig. 4.12. On-time detection circuit ........................................................................ 39

Fig. 4.13. Timing diagram of the on-time detection circuit when the load current (a)

decreases and (b) increases ...................................................................................... 40

Fig. 4.14. The state transition diagram of the frequency selection circuit ............... 41

Fig. 4.15. Clock and ramp generator ....................................................................... 44

Fig. 4.16. DCM detection circuit ............................................................................. 45

Fig. 4.17. Timing diagram of the on-time detection circuit when the load current (a)

decreases and (b) increases ...................................................................................... 46

vii
Fig. 4.18. Dead time controller and driving buffer .................................................. 47

Fig. 4.19. Chip microphotograph ............................................................................ 48

Fig. 4.20. Measured waveforms of the proposed active rectifier when the resonant

frequency is (a) 3.23-MHz and (b) 6.78-MHz ........................................................ 49

Fig. 4.21. Measured waveforms when the load current is (a) 300-mA, (b) 70-mA, (c)

35-mA, and (d) 15-mA for the input voltage of 9.0-V and output voltage of 5.0-V

................................................................................................................................... 50

Fig. 4.22. Measured waveforms when the load current changes (a) between 10-mA

and 500-mA (b) 10-mA and 100-mA ...................................................................... 51

Fig. 4.23. Measured power efficiency versus the load current when the input voltage

is (a) 6.0-V, (b) 9.0-V, and (c) 12.0-V .................................................................... 52

Fig. 4.24. Measurement set-up of the wireless power receiver charging a mobile

phone ....................................................................................................................... 54

Fig. 4.25. Power efficiency of the wireless power receiver versus the output power

................................................................................................................................... 54

Fig. 4.26. Schematic of the wireless power receiver for mobile devices of follow-up

research .................................................................................................................... 56

Fig. 4.27. Chip microphotograph of the wireless power receiver of follow-up

research .................................................................................................................... 57

Fig. 4.28. Test printed circuit board of wireless power receiver of follow-up research

................................................................................................................................... 58

viii
Fig. 4.29. Power efficiency of the wireless power receiver of follow-up research

versus the output power ........................................................................................... 58

Fig. 4.30. Measurement set-up of charging a mobile phone ................................... 59

Fig. 4.31. Measurement set-up of charging a tablet PC .......................................... 60

Fig. 4.32. Measurement set-up of charging a mobile phone with in-band

communication ........................................................................................................ 60

Fig. 4.33. (a) Block diagram and (b) measured waveform of the wireless power

receiver with in-band communication phone .......................................................... 61

Fig. 5.1. Simplified architecture of a wireless power transceiver ........................... 64

Fig. 5.2. Proposed wireless power transceiver with a bi-directional DC-DC converter

................................................................................................................................... 65

Fig. 5.3. Bi-directional DC-DC converter ............................................................... 66

Fig. 5.4. VIN_HIGHER and VOUT selection circuit ........................................................ 68

Fig. 5.5. Error amplifier ........................................................................................... 69

Fig. 5.6. Clock and ramp generator ......................................................................... 70

Fig. 5.7. The open loop gain and phase of the proposed DC-DC converter operates

in (a) receiver (b) transmitter mode. ........................................................................ 72

Fig. 5.8. Detailed architecture of a proposed wireless power transceiver. .............. 74

Fig. 5.9. Chip microphotograph . .............................................................................. 78

ix
Fig. 5.10. Power conversion efficiency when the bi-directional DC-DC converter

operates in (a) buck and (b) boost converter ........................................................... 79

Fig. 5.11. Wireless power transceiver in (a) the receiver mode and (b) the transmitter

mode ........................................................................................................................ 80

Fig. 5.12. Printed circuit board of the proposed wireless power transceiver .......... 81

Fig. 6.1. Wireless power charger IC for a wearable medical device ....................... 85

Fig. 6.2 Operational amplifier (EA1) of the linear battery charger .......................... 88

Fig. 6.3 In-band communication circuit ... ................................................................ 89

Fig. 6.4 Timing diagram of the in-band communication .......................................... 89

Fig. 6.5 Clock and ramp generator .......................................................................... 90

Fig. 6.6 Band-gap reference circuit ......................................................................... 91

Fig. 6.7 Low-drop-out regulator .............................................................................. 92

Fig. 6.8 Over-input voltage protection (OIVP) circuit ............................................ 93

Fig. 6.9 Chip microphotograph ............................................................................... 94

Fig. 6.10 Measurement set-up of the wireless power charger IC ............................ 95

Fig. 6.11 Measured waveforms of the in-band communication for the proper

connection of wireless power charger and charging pad ......................................... 95

x
 List of Tables

Table 4.1 Comparison with other control schemes for improved light load

efficiency ................................................................................................................. 42

Table 4.2 Performance summary of the proposed wireless power receiver ......... 55

Table 4.3 Performance summary of the wireless power receiver of follow-up

research .................................................................................................................... 62

Table 5.1 Comparison of the class-D and class-E power amplifier ..................... 76

Table 5.2 Performance summary of the proposed wireless power transceiver .... 82

Table 6.1 Performance summary of the proposed wireless power charger .......... 96

xi
 1. Introduction

1.1. Motivation

The resonant magnetic coupling can significantly improve the efficiency and

transmission range of a wireless power transmission (WPT) system [1] and the

probable applications of the WPT are now ranging from the charging of small

wearable medical devices to the powering of electric vehicles [2]. While the

efficiency of a WPT channel itself can be improved by the resonant magnetic

coupling, the overall power transmission efficiency of a WPT system, however, is

also limited by the efficiency of power transmitting and receiving circuitry. Because

the frequency of the transmitted AC power of a WPT system is much higher than

50~60 Hz of the conventional AC power, it is very challenging to get a high power

efficiency in the wireless power transmitting and receiving circuitry. Therefore, the

research for the wireless power receiver and transceiver must be required to increase

the overall power transmission efficiency of a WPT system.

Also, if a mobile device is capable of not only receiving but also transmitting

power wirelessly, it can be utilized as a mobile wireless power charging station for

another mobile device which is power-hungry. For example, a mobile phone can

charge a Bluetooth handset, hearing aid, or another mobile phone wirelessly with its

battery as the power source. For a mobile device to be capable of both receiving and

transmitting power wirelessly, a wireless power transceiver is required.

And also, wearable medical devices such as hearing aid, artificial pacemaker, and

glucose monitor are desired to operate without charging or changing battery as long

1
as possible [3]-[11]. If the battery of a wearable medical device can be charged

wirelessly, the user convenience can be greatly improved. Another requirement for a

wearable medical device is the capability of exchanging information with an

external host [12]. If the medical device monitors any bio-signal, the monitored bio-

signal has to be transmitted to the external host for a user or doctor to be informed of

it. The status of the battery of a wearable medical device has to be shared with the

power transmitter to maximize the battery life as well [13]. Because the size of a

wearable medical device is very critical, it is desired to transmit any information via

the same channel as the one used for the wireless power transmission, which is

known as the in-band communication.

The target of this fist research is to design a wireless power receiver for mobile

devices with the high efficiency active rectifier and DC-DC buck converter. The

reverse leakage current of the active rectifier is prevented by the proposed scheme.

Also the light load efficiency of the DC-DC buck converter can be improved with

the load-adaptive automatic frequency selection circuit. The wireless power

transceiver, which is capable of not only receiving but also transmitting power

wirelessly, is the target of the second research. The bi-directional DC-DC converter

has been proposed to reduce the form-factor of the wireless power transceiver. The

target of the final research is to design a wireless power charger with in-band

communication circuit for wearable medical devices. The high power efficiency can

be achieved with the proposed wireless power charger and the connection of the

wireless power charger with a charging pad (wireless power transmitter) and the

fully charged status of the battery are notified by the in-band communication circuit.

2
1.2. Thesis Organization

This thesis describes the theoretical background of the wireless power

transmission system and a controlling method of the wireless power receiver and

transceiver for mobile devices and wireless power charger for wearable medical

device. After describing the design issues of the wireless power receiver, transceiver,

and charger, the detailed circuit design will be presented. The thesis is organized as

following:

Chapter 2 introduces overview of the wireless power transmission system to help

understand the rest of the thesis.

Chapter 3 covers circuit design considerations of the wireless power transmission

system.

Chapter 4 presents a proposed wireless power receiver which combines a lot of

the design considerations for mobile devices.

Chapter 5 shows a proposed wireless power transceiver, which is capable of not

only receiving but also transmitting power wirelessly. And the detailed circuit level

design to improve the power efficiency is presented.

Chapter 6 describes a wireless power charger for wearable medical device. The

design issues and solutions are presented in this chapter.

Chapter 7 concludes this thesis.

3
 2. Overview of the Wireless Power

Transmission System

This chapter provides some basic background knowledge about wireless power

transmission system to help understand the rest of the thesis. The basic concept and

necessity of wireless power transmission is introduced.

2.1. Necessity of the wireless power transmission

The conventional use to charge the battery of the portable devices such as mobile

phone, tablet PC, and notebook is made possible through the charging cable.

However, wired power transfer has many problems, such as short circuit, wired

hazards, and inconvenience. If the battery of the portable devices can be charged

wirelessly, the user convenience can be greatly improved and safety.

Although the portable devices can be charged by the wired charging cable, the

wearable or implantable medical devices such as hearing aid, artificial pacemaker,

and glucose monitor may not be charged by the charging cable. To charge the battery

of implantable devices inside human body, the medical surgery must be required. In

addition, the hearing aid equipped rechargeable battery can be charged by wireless

charging PAD or mobile phone without any complicate battery replacement when

the wireless power transmission can be enabled.

To increases the user convenience and safety of human, wireless power receiver,

transceiver, and charger has been researched.

4
 Resonator

Charger
AC-DC DC-AC AC-DC DC-DC
Power and/or
converter converter converter converter
battery

Fig. 2.1. Simplified architecture of the wireless power transmission system.

2.2. Simplified architecture of the wireless power transmission

system

Fig. 2.1 shows the simplified architecture of the wireless power transmission

system. The AC-DC converter converts the input AC voltage to DC voltage. The

DC-AC converter of the transmitter delivers AC power to the resonator. Generally,

the magnitude of the transferred power is determined by the supply DC voltage of

the DC-AC converter. The wireless power receiver consisting of an AC-DC

converter and DC-DC converter provides the DC power to the battery charger and/or

battery. Because the frequency of the transmitted AC power of a WPT system is

much higher than 50~60 Hz of the conventional AC power, it is very challenging to

get a high power efficiency in the wireless power transmitting and receiving

circuitry. Therefore, the research for the wireless power receiver and transceiver

must be require to increase the overall power transmission efficiency of a WPT

system. Between the resonator and transmitter or receiver, the impedance matching

network can be added to ensure the proper resonance between the transmitter and

receiver.
5
 The key design of the wireless power transmission is the power efficiency,

because the power loss generates temperature heating. If mobile phone or hearing

aid equipped the wireless power transmission system has lower charging efficiency

due to the lower power efficiency of the wireless power transmission, user may

suffer burns or mobile phone may be malfunction by the temperature protection

circuits. In the case of implantable medical devices, adverse effect resulting from

low power efficiency may be serious.

The detailed design considerations including the power conversion efficiency of

the wireless power transmission system circuit will be explained in the following

chapter 3.

6
 3. Design Considerations of the Wireless Power

Transmission System Circuit

This chapter provides design considerations of the wireless power transmission

system circuit including wireless power transmitter, receiver, and charger.

3.1. Wireless power transmitter

The wireless power transmitter consists of AC-DC converter and power amplifier

(DC-AC converter). The input voltage may be power outlet AC voltage such as 220-

V/60-Hz, which can be converted to DC voltage by such as fly-back isolated

converter for user safety. Because the efficiency of the wireless power transmitter is

mainly determined by the power amplifier, the key design of the wireless power

transmitter is the power amplifier for higher power efficiency. In the following

subchapter, the benefits and control methods of the various power amplifiers are

presented in detail.

3.1.1. Linear power amplifier and switching power amplifier

The topology of the power amplifier is divided to linear power amplifier and

switching power amplifier. The linear power amplifier such as class-A, class-B,

class-AB, and class-C has good linearity, which is required when the signal contains

amplitude modulation or a combination of amplitude and phase modulation such as

SSB, TV video carriers, QPSK, and QAM. However, the linear power amplifier has

7
 VDD

VDS Output
IDS matching
RL

Fig. 3.1. Basic schematic of the linear power amplifier.

VDS (V) IDS IDS (A)

VDS

Time
Voltage and
current overlap

Fig. 3.2. Voltage and current waveforms of the linear power amplifier.

poor power efficiency due to the power dissipation of the power transistor which is

generated by overlap of the voltage and the current. Fig. 3.1 and Fig. 3.2 show the

schematic and voltage and current waveforms of the conventional class-AB power

amplifier. Because the overlap of voltage and current, the power amplifier has power

conversion efficiency of about 67-%

8
 VDD VDD

Resonator
VDS
IDS RL

Fig. 3.3. Basic schematic of the switching power amplifier.

VDS (V) VDS IDS IDS (A)

Time

Fig. 3.4. Voltage and current waveforms of the switching power amplifier.

The switching power amplifier such as class-D and class-E has higher power

conversion efficiency due to the reduced overlap of voltage and current and has ideal

efficiency of 100-%. Fig. 3.3 and Fig. 3.4 show the schematic and voltage and

current waveforms of the conventional class-D power amplifier.

In wireless power transmission, the switching power amplifier is proper selection

9
 VCC

CR LR
VD
VG ID RL
M1

Fig. 3.5. Simplified schematic of the class-D power amplifier.

VG

VD

ID

Fig. 3.6. Voltage and current waveforms of the class-D power amplifier.

because the switching power amplifier has higher power conversion efficiency and

the amplified signal does not contain the amplitude modulation.

However, in real implementation, the switching and component losses can

significantly degrade the power conversion efficiency. The conduction loss due to
10
the On-resistance of the transistors degrades the power efficiency. And the parasitic

capacitor such as drain-source capacitance of the transistors causes switching loss.

To drive the transistors, the driving circuit is required, which results in driving

power loss. Also, voltage and current overlap due to the limited turn-on and turn-off

speed of the transistors cause the switching loss. Therefore, the power losses must be

considered to design the switching power amplifier.

In the switching power amplifier types, class-D and class-E power amplifiers will

be explained including the control complexity, form-factor, and power efficiency is

better than others.

3.1.2. Class-D power amplifier

Fig. 3.5 and Fig. 3.6 show the simplified schematic and voltage and current

waveforms of the class-D power amplifier. When the gate driving signal VG is HIGH,

the transistor M1 is turned-on. Then the node VD is GND and current ID is flowing

through the transistor. On the contrary, the node VD is VCC and current ID is zero

when the transistor M1 is turned-off. Because the multiplication of the drain-source

voltage VD of the transistor M1 and current ID flowing through transistor M1 is

always zero, the power loss of the transistor can be zero. Therefore, the power

efficiency of the class-D power amplifier can be 100-%. However, the power

efficiency is degraded by the power losses. The node VD cannot be GND because the

MOS transistor has non-zero On-resistance. Therefore, the conduction loss is

generated, which degrades the power loss. If the size of the power transistor is

increased, the On-resistance can be decreased. However, the gate capacitance of the

11
 VCC

RFC
CR LR
VD
VG ID C1 RL
M1

Fig. 3.7. Simplified schematic of the class-E power amplifier.

VG

VD

ID

Fig. 3.8. Voltage and current waveforms of the class-E power amplifier.

power transistor is increased, which results in higher gate driving loss. Also, the

drain-source capacitance of the MOS transistor generates switching loss. To reduce

the switching loss due to the drain-source capacitance of the MOS transistor, the

class-E power amplifier is described in the following subsection.

12
3.1.3. Class-E power amplifier

Fig. 3.7 and Fig. 3.8 show the simplified schematic and voltage and current

waveforms of the class-E power amplifier. When the gate voltage VG of the

transistor is HIGH, the transistor M1 is turned-on. Then the node voltage is GND and

current ID is flowing through the transistor. Like the class-D power amplifier, the

multiplication of the drain-source voltage VD of the transistor M1 and current ID

flowing through transistor M1 is zero. Therefore, the higher power efficiency can be

achieved.

Because the drain-source capacitance of the transistor is used for output matching

network, the switching loss of the class-E power amplifier is lower than that of the

class-D power amplifier. In addition, the class-E power amplifier requires only one

MOS transistor, but the class-D power amplifier requires two MOS transistor and

non-overlapping driving signal generator to prevent the short-circuit leakage current.

Because the number of the transistors of the class-D power amplifier is twice that of

the class-E power amplifier, the class-E power amplifier may be proper choice to

design the power amplifier when the switching frequency is very high.

However, the voltage stress of the MOS transistor is higher than the class-D

power amplifier. In case of the class-D power amplifier, the voltage stress is only

VCC. The voltage stress is about 3.562  VCC in case of the class-E power amplifier.

Therefore, various design considerations must be considered to choice proper type

of the power amplifier.

3.2. Wireless power receiver

13
 D1 D2

VIN,AC COUT

D3 D4

Fig. 3.9. Schematic of the AC-DC converter.

VIN

VOUT
Vpk-pk–2*VDROP

Fig. 3.10. Waveforms of the AC-DC converter.

The wireless power receiver consists of AC-DC converter, DC-DC converter, and

battery charger. The AC-DC converter converts the received AC power to the DC

power for DC-DC converter. The DC-DC converter converts the rectified DC

voltage to appropriate DC voltage for battery charger. The detailed circuit design of

the wireless power receiver will be described.

3.2.1. AC-DC converter of the wireless power receiver

The name of the AC-DC converter can be named by rectifier, because the input

AC voltage is converted to rectified DC voltage. Fig. 3.9 and Fig. 3.10 show the

schematic and wave forms of the AC-DC converter. If the voltage drop of the diode

14
 DS1 DS2 MP1 MP2
MP1 MP2

VIN,AC COUT VIN,AC COUT VIN,AC COUT

DS3 DS4
MN1 MN2 MN1 MN2

(a) (b) (c)

Fig. 3.11. Various structures of the AC-DC converter.

is 0.7-V and the swing of the input AC voltage is 5-VPK-PK, the power efficiency can

be limited by 72-%. When the drop voltage of the diode is decreased, the power

conversion efficiency can be increased.

Fig. 3.11 shows the general structures of the AC-DC converter. Fig. 3.11-(a)

shows the passive rectifier which consists of four Schottky diodes. Because the

voltage drop of the Schottky diode is lower than that of the P-N diode, the power

conversion efficiency of the rectifier can be increased. Also, the reverse recovery

time of the Schottky diode is faster than that of the P-N diode. Therefore, the

Schottky diode is appropriate for wireless power transmission. Fig. 3.11-(b) shows

the active rectifier which consists of four active transistors. The drop voltage of the

diode can be removed by the active transistor. However, in real implementation, the

power losses such as conduction loss and driving loss degrade the overall power

conversion efficiency. There is trade-off relationship between conduction loss and

driving loss. If the size of the power transistors is increased, the conduction loss is

decreased. However, the driving loss may be increased due to increased gate

15
capacitance of power transistors. Also, the driving loss is proportional to the

resonant frequency of the wireless power transmission system. Therefore, the active

rectifier can be applied to the low resonant frequency even if the voltage drop of the

diode is reduced with the active transistor. Fig. 3.11-(c) shows the combination of

the Schottky diode and cross-coupled transistors. The diode voltage drop of low side

is reduced by cross-coupled transistors. Because of the soft switching of the power

transistors, the driving power loss can be decreased, which increases the overall

power conversion efficiency. Because each structure has advantages and

disadvantages according to the resonant frequency, input voltage swing level and

size, many simulation and research are required for appropriate scheme of the

rectifier according to the applications.

3.2.2. DC-DC converter of the wireless power receiver

The DC-DC converter converts the rectified DC voltage of proper DC voltage for

the battery charger. The received AC power and rectified DC voltage varies with the

efficiency of the resonator. For example, the rectified DC voltage is decreased when

the distance of the wireless power transmitter and receiver is shortening because the

efficiency of the resonator is increased. Therefore, the DC-DC converter must be

required to supply proper DC voltage for the battery charger.

Generally, the battery charger requires about 5.0-V and the rectified output

voltage level of the rectifier is higher than the voltage level of 5.0-V. Therefore, in

this chapter, the step-down buck converter is described. And also, only the switching

DC-DC converter is explained because the power conversion efficiency is very

16
critical issue of the wireless power transmission system.

Fig. 3.12 shows the basic structure of the power transistors of the buck converter.

Fig. 3.12-(a) and -(c) uses pMOS power transistor for high-side power transistor of

the buck converter. The ON-resistance of the pMOS power transistor is higher than

that of the nMOS power transistor and thus the buck converter consisting of nMOS

power transistor as shown in Fig. 3.12-(b) and -(d) for high-side power transistor has

higher power conversion efficiency. On the contrary, the nMOS high-side power

transistor requires bootstrap circuit consisting of a diode and capacitor, which

increases the form-factor. Because the nMOS power transistor for low-side power

transistor of the buck converter is not required any extra component, the nMOS

power transistor is better than the pMOS power transistor for low-side transistor.

VOUT VOUT
MP MN
L L

+ +
- VIN MN CO IO - VIN MN CO IO

(a) (b)

VOUT VOUT
MP MN
L L

+ +
- VIN DS CO IO - VIN DS CO IO

(c) (d)

Fig. 3.12. Basic structures of the power transistors of the buck converter.

17
 L
VOUT
+ MP IL
- VP
VIN MN CO ILOAD
RC2
VN CC2 R1

RC1 CC1 CC3

COMP1 VEA EA1 -

-
VFB

Dead time Q R + +
+ R2
Control
-
VRAMP VBGR
& Buffer S
ΦCLK

Fig. 3.13. Simplified block diagram of the voltage-mode controlled DC-DC buck

converter..
Although the Schottky diode can be used for low-side power transistor as shown in

Fig. 3.12-(d), the conduction loss of the Schottky diode is higher than that of the

nMOS power transistor.

Fig. 3.13 shows the simplified block diagram of the voltage-mode controlled DC-

DC buck converter. The resistor divided output VFB is compared with the reference

voltage generated by the band-gap reference circuit. The type-III compensation

circuit consisting of resistors and capacitors compensates the loop stability of the

buck converter. The comparator COMP1 compares the output of the error amplifier

EA1 with saw-tooth signal VRAMP generated by clock and ramp generator and

generates the pulse width modulation signal. To prevent the multiple pulses of the

pulse width modulation signal, the SR-latch is used. The dead-time control circuit

generates non-overlapping signal of the power transistors and the buffer drives large

size of the power transistor.

18
3.2.3. Battery charger

Fig. 3.14 shows the basic structures of the battery charger. Fig. 3.14-(a) shows the

switching charger and -(b) shows linear battery charger. The switching charger has

higher power efficiency but has large form-factor due to the inductor. Although the

inductor of the switching charge can be replaced by the on-chip inductor or small

size inductor, the efficiency would be degraded. The linear charger has small form-

factor due to the absence of the external inductor. However, the linear charger has

lower power conversion efficiency. For example, the conversion efficiency is limited

by 50-% when the input voltage of the linear charger is 4.0-V and the output

charging voltage is 2.0-V. Therefore, there must be careful selection of types of the

battery charger.

Switching charger IC Linear charger IC

M1 RSEN M1 RSEN
L1
M2 Battery Battery
C1 C2 C1
Current Current
Sensor Sensor

Controller Controller

(a) (b)

Fig. 3.14. Simplified schematic of the (a) switching and (b) linear battery charger IC.

19
 4. Proposed Wireless Power Receiver

for Mobile Devices

In this chapter, the proposed wireless power receiver for mobile application is

explained. The received AC power is rectified by a proposed active rectifier and

then converted to the desired DC level by a switching DC-DC converter. The

reverse leakage of the active rectifier is prevented by a delay locked loop (DLL)

based delay compensation circuit. And the switching buck converter with improved

efficiency at light-load condition is described. At heavy-load condition, the

converter operates in continuous conduction mode (CCM) and the switching

frequency is fixed. At light-load condition, the converter operates in discontinuous

conduction mode (DCM) and the switching frequency is automatically selected

among a pre-determined set of frequencies according to the load current without

any costly current sensing circuit. Because the turn-on-time of high-side power

transistor is a function of the load current, the magnitude of load current can be

sensed.

4.1. Motivation of the wireless power receiver for mobile devices

The resonant magnetic coupling can significantly improve the efficiency and

transmission range of a wireless power transmission (WPT) system [1] and the

probable applications of the WPT are now ranging from the charging of small

mobile devices to the powering of electric vehicles [2]. While the efficiency of a

20
 TX Wireless Power Receiver
Resonator

Power Impedance Active DC-DC Battery

PA
matching Rectifier Converter Charger

Fig. 4.1. Block diagram of the wireless power transmission system.

WPT channel itself can be improved by the resonant magnetic coupling, the overall

power transmission efficiency of a WPT system, however, is also limited by the

efficiency of power transmitting and receiving circuitry. Because the frequency of

the transmitted AC power of a WPT system is much higher than 50~60-Hz of the

conventional AC power, it is very challenging to get a high power efficiency in the

wireless power transmitting and receiving circuitry.

Fig. 4.1 shows the simplified block diagram of the WPT system of this work

which can charge mobile devices wirelessly. The power amplifier (PA) of the

transmitter delivers AC power to the magnetic resonator whose resonant frequency

is either 3.23-MHz or 6.78-MHz. The receiver consisting of an active rectifier and

switching DC-DC converter provides the DC power to the battery charger. Between

the magnetic resonator and the receiver circuit, the impedance matching network

ensures the proper resonance between the transmitter and receiver.

Because of the high power level and resonant frequency, it is not easy to get high

power conversion efficiency for the rectification of the received AC power input. If

a rectifier is implemented with passive diodes, its efficiency would be limited by

21
 IO_REC VO_REC
- Buffer Buffer -
+ +
MP1 MP2

VIN_A VIN_B
CO_REC
AC input
- Buffer Buffer -
VC1 VN
+ +
tD_BUFF MN1 MN2 tD_BUFF
tD_COMP tD_COMP

Fig. 4.2. Schematic of the basic active rectifier.

the forward voltage drop of the passive diodes [14], [15].

Fig. 4.2 shows the schematic of the basic active rectifier to increase the power

conversion efficiency. The diodes of the passive rectifier shown in Fig. 4.1 are

replaced by active transistors. Because the drop voltage of the active transistor is

much lower than the drop voltage of the P-N diode or Schottky diode, the power

conversion efficiency of the active rectifier may be higher than that of passive

rectifier. The comparator is used for diode operation of the active transistor. When

the drain node voltage of the nMOS power transistor is lower (higher) than source

node voltage, the transistor is turned-on (turned-off) for diode operation. The

driving buffer drives large size power transistors.

In real implementation, the power losses such as driving power loss, conduction

power loss, and reverse leakage current degrade the power conversion efficiency of

the active rectifier. If the size of the power transistor is increased, the conduction

22
 VIN_A

GND

tD_COMP tD_COMP
VC1

tD_BUFF tD_BUFF
VN

IO_REC

Reverse
leakage

Fig. 4.3. Timing diagram of the conventional active rectifier.

power loss can be decreased. However, the driving power loss is increased due to

the increased gate capacitance of the power transistor. Because of the trade-off

relationship between driving power loss and conduction power loss, there must be

many simulation for appropriate size of the power transistor.

Fig. 4.3 shows the timing diagram of the conventional active rectifier. The reverse

leakage is mainly due to the finite delay of the comparator and the buffer driving

the nMOS transistor. The turn-on and turn-off instants of the nMOS transistors MN1

and MN2 are delayed by tD_COMP + tD_BUFF from the zero crossing instants of the AC

input voltage where tD_COMP and tD_BUFF are the delays of the comparator and buffer,

respectively. The delayed turn-on of the nMOS transistor MN1 and MN2 is not

problematic because it does not cause any reverse leakage current. The delayed

turn-off, however, results in reverse current flow which degrades the power

23
conversion efficiency.

In [15], the comparator is designed to have non-zero finite DC offset which can

compensate the turn-off delay and thus prevent the reverse leakage current. With a

fixed finite DC offset of the comparator, however, the amount of the compensated

delay varies depending on the amplitude of the received AC input voltage while the

delay of the comparator and buffer is constant regardless of the amplitude of the

AC input voltage. In [14], the delay time of the comparator is reduced with offset

current when the resonant frequency is 13.56-MHz. However, the proposed concept

cannot be applied to mobile devices, because the delay time of the buffer to drive

the large size capacitance of the power transistor is not considered. The power level

is limited by about 6-mW.

4.2. Proposed active rectifier for wireless power receiver for mobile

devices

Fig. 4.4 shows the proposed block active rectifier for wireless power receiver for

mobile devices. The turn-off delay of the comparator and buffer is compensated by

the DLL with the timing shown in Fig. 4.4. By controlling the delay of the voltage

controlled delay line (VCDL), the DLL aligns the falling edge of the signal VND

with that of the comparator output VC1. Then, the gate voltage VN of the nMOS

transistors is aligned to the falling zero crossing instant of the AC input voltage

VIN_A because the delays from VIN_A to VC1 and from VN to VND are all equal to the

delay tD_COMP of the comparator. If the turn-off instant of the nMOS power

transistor is generated after the falling zero crossing instant of the AC input voltage,
24
 VO_REC

IO_REC
MP1 MP2

VIN_A VIN_B
CO_REC
AC input

Comparator VN Comparator
MN1 MN2
with zero delay with zero delay

VIN_A -
VC1 Rising edge detector
VCR
+ S Buffer
VCF VCQ VN
R Q
tD_COMP
tD_BUFF

VCDL

VND ΦUP
tD_COMP VCTRL
Phase
detector ΦDN

Comparator with zero delay

Fig. 4.4. Active rectifier employing the proposed comparator with zero delay.

the falling edge of the voltage VND is generated after the falling edge of the voltage

VC1 is generated, which decreases the control voltage VCTRL and delay time of the

VCDL.

In this way, the delayed turn-off time of the nMOS transistors can be removed,

which prevents reverse leakage current and improves power conversion efficiency.

25
 VIN_A

GND

tD_COMP tD_COMP
VC1

VCR

tD_VCDL
VCF

VCQ

tD_BUFF tD_BUFF
VN

tD_COMP tD_COMP
VND

IO_REC

Fig. 4.5. Timing diagram of the active rectifier with the proposed comparator with

zero dealy.

Although the delayed turn-on of the nMOS transistor MN1 and MN2 is remained, it

does not cause any reverse leakage current.

To prevent the multiple pulses of the pulse width modulation signal, the SR-latch

is used. The driving buffer is realized as an inverter chain with gradually increasing

size to drive the large gate capacitance of the power transistors. The other sub-

circuit of the proposed active rectifier is explained in following chapter.

26
4.2.1. Sub-circuit design of the proposed active rectifier

In this chapter, sub-circuit design of the proposed active rectifier is described in

detail.

4.2.1.1 Phase detector and charge pump

The schematic diagram of the phase detector and charge pump are shown in Fig.

4.6 and Fig. 4.7, respectively. The phase detection consisting of AND logic gate

and two D-flip flops. The input of the phase detector operates as clock of the D-

flop flops. When the VND signal is LOW and comparator output VC1 is HIGH the

output ΦUP and ΦDN of the phase detector goes to HIGH and LOW, respectively. If

the comparator output VC1 is LOW, ΦDN goes to HIGH and the D-flip flop is

reseted by the output of AND logic gate. In this way, the phase difference between

VND and VC1 is converted to differential pulse widths of ΦUP and ΦDN. The

difference between pulse widths of ΦUP and ΦDN is converted to control voltage

VCTRL by charge pump, which determines the delay time of delay line.

The charge pump consists of voltage-current (V-I) converter and current mirror

transistors and switching transistors. When the signal ΦUP is HIGH (LOW), the

capacitor of charge pump is charged (discharged) by constant current. The output

voltage VCTRL of charge pump is inputted to the voltage controlled delay line

(VCDL) to generate appropriate delay time.

4.2.1.2 Voltage controlled delay line (VCDL)

27
 The VCDL circuit shown in Fig. 4.8 is realized as two V-I converters and

inverters to drive four capacitor. Because the magnitude of the current source is

controlled by the control voltage VCTRL, delay time of the VCDL circuit varies

according to the control voltage VCTRL. The magnitude of the current source IVCDL is

VBGR/R2-VCONT/R1. When the control voltage VCONT is increased, the delay from VC1 to

VCF is increased. And thus the delay from VIN_A to VN is increased to align the falling

VDD
D
Q ΦUP
VND CK
Reset
VDD
D
Q ΦDN
VC1 CK

Fig. 4.6. Phase detector.

M2 M4 M6

M3 M5 M7

ΦUP
VCTRL
VREF
ΦDN
A1 M1
M8 M10

RC VREF/RC M9 M11

Fig. 4.7. Charge pump.

28
 C4
VCF
M23

M24

M25

M26
C3
M19

M20

M21

M22
C2
M15

M16

M17

M18
C1
M11

M12

M13

M14
VC1

M9
M10

IVCDL

VBGR/R2 M8
M7

M1
M6

M5 R2
A2
VBGR

M4
M3

VCONT/R1
M1
M2

R1
A1
VCONT

Fig. 4.8. Voltage controlled delay line.

zero crossing instant of the AC input voltage VIN_A. If the reverse leakage is

generated because of the large delay from VIN_A to VN, the control voltage VCTRL is

decreased to reduce the delay from VIN_A to VN.

29
4.2.1.3 Band-gap reference

Fig. 4.9 shows the schematic of the band-gap reference circuit. The generated

reference voltage by the band-gap reference circuit is used for bias current source

and low drop-out regulator. The dummy voltage VDUM is generated by the three

transistors, one resistor, and one zener diode. The break-down voltage of the zener

diode is about 6.0-V and the threshold voltage of the nMOS transistor M3 is about

1.0-V. Therefore the dummy voltage VDUM has about 5.0-V for band-gap reference

circuit. The corrector voltages of different sized bipolar junction transistor Q1 and

Q2 have same voltage by the error amplifier consisting of nMOS transistor M8, M9,

and M10, pMOS transistor M6 and M7, bias current IB1, and resistors R5 and R4.

VO_REC

M1 M2

M3
VDUM
R1 D1
M10
M4 M5 M6 M7

M8 M9
R5

VBGR
Q1 Q2

R2
IB1
R4
R3

Fig. 4.9. Band-gap reference.

30
4.2.1.4 Low-drop-out (LDO) regulator

The linear low-drop-out (LDO) regulator shown in Fig. 4.10 provides 5.0-V

supply to the circuit of the proposed active rectifier to prevent the gate oxide

breakdown when the input voltage level is higher than the tolerable voltage level.

The capacitor CC1 and the resistor RC1 are used to compensate the loop stability of

the LDO regulator.

VO_REC

VDUM
M9 M10

M1 M12
M8 M11 VLDO
VBGR RC1 CC1
M2 M3
RD1

M5 M7
RD2
M4 M6

Fig. 4.10. Low-drop-out regulator.

4.2.1.5 Start-up operation

At start of the wireless power transmission, the output voltage level of the active

rectifier may be ground level. If the output voltage level of the active rectifier stays

ground level, the control logic cannot be operated normally. However, fortunately

31
output voltage level can rise by the parasitic diode of the power transistor. When

the output voltage level is larger than the proper voltage level, the dummy voltage

VDUM, band-gap reference voltage VBGR, and the supply voltage of the control circuit

VDD are generated sequentially.

4.3. Proposed buck converter with an automatic load-adaptive

switching frequency selection technique

4.3.1. Necessity and background of the proposed buck converter

The key features of the switching DC-DC converters are high power efficiency,

low cost, and small size for mobile application [16]. For the small size of a

switching DC-DC converter, the switching frequency is desired to be as high as

possible, which allows small off-chip inductor and capacitor and eventually on-chip

realization of the passive elements. High switching frequency, however, induces

higher gate-driving power loss and switching power loss. Therefore, it is very

difficult to get high power efficiency with high switching frequency. This becomes

much severer at light-load condition because the gate driving power loss is

independent of the load current [17], [18].

The gate driving power loss of a switching DC-DC converter is given as;

Ploss  C gate  Vsw2  f sw (4.1)

Where Cgate is the gate capacitance of the power transistor, Vsw is the voltage

swing of the gate driving signal and fsw is the switching frequency of the DC-DC

converter. From the equation (4.1), there can be three ways to reduce the gate-
32
driving power loss for better light-load efficiency.

The voltage swing of the gate driving signal of power transistor can be lowered at

light-load condition, which requires complicated control circuitry and can result in

floating power transistor if the swing is lowered too much [19]. With the pulse

frequency modulation (PFM), the switching frequency changes according to the

load condition and thereby high power efficiency can be achieved at light-load

condition [20], [21]. A hybrid of the PFM and pulse width modulation (PWM) can

also improve the power efficiency by operating the DC-DC converter in PFM mode

at light-load condition [22]-[27]. With the PFM, however, the switching frequency

is not predictable and undesired switching noise at the harmonics of the switching

frequency is generated. If the switching frequency is lowered to be in the audio

band, the unwanted switching noise can be coupled into the audio circuits through

the supply lines, resulting in severe degradation of audio signal quality [28].

Moreover, a hybrid of the PFM and PWM can provoke relatively large output

voltage transients during the transition between PWM and PFM. In [24], [29], and

[30], the number of the fingers of the power transistor is changed to control the

effective width of the transistor and the gate capacitance Cgate according to the load

current. An off-chip inductor can be placed between the driving buffer and power

transistor so it can resonate with the parasitic capacitance, which allows low power

driving of the power transistor [31]. The charge on the gate capacitor of the power

transistor can be recycled to save power [32]. A non-linear inductor can be used to

lower the switching frequency at light-load condition [33], [34]. However, the

switching frequency is unpredictable and a non-linear inductor is required which

33
can be implemented by a complicated fabrication process and/or materials. In [35],

the switching frequency is fixed to fS at heavy-load condition and changed to fS/N

where N=2i and i = 0, 1, 2, 3 according to the load current for higher efficiency at

light-load condition. The spectral components of the output of switching DC-DC

converter are predictable and can be filtered out regardless of the load condition. To

implement this, a current sensing circuit is required to sense the peak current,

which may consume large power and is sensitive to noise because usually it is

consist of high-gain low-offset error amplifier, switches, and current mirrors [36].

Moreover, if this scheme is to be applied to a voltage mode or hysteretic switching

DC-DC converter, the current sensing itself is a big burden because usually the

current sensing is not required for them.

This chapter presents a switching buck converter with improved efficiency at

light-load condition. At heavy-load condition, the converter operates in continuous

conduction mode (CCM) and the switching frequency is fixed. At light-load

condition, the converter operates in discontinuous conduction mode (DCM) and the

switching frequency is automatically selected among a pre-determined set of

frequencies according to the load current without any costly current sensing circuit.

The load current can be sensed by monitoring the on-time of the power transistor

because it is a function of the load current.

4.3.2. Proposed load-adaptive frequency selection technique

34
 L
VIND VOUT
+
- MP IL
VIN MN CO ILOAD
RC2
CC2 R1

RC1 CC1 CC3

VN
VP
COMP1 VEA EA1 -
-
VFB

Dead time Q R + +
+ R2
& Driving
-
VRAMP VBGR
buffer S
ΦCLK

VUP VF1 ΦCLK

On-time Finite-state Clock & Ramp
detection VDN machine VF0 generator VRAMP

DCM VENA
detection

Frequency selection circuit

Fig. 4.11. Block diagram of the buck converter with the proposed automatic

frequency selection technique for improved power efficiency.

Fig. 4.11 shows the block diagram of a switching buck converter with the

proposed load-adaptive automatic frequency selection technique. The buck

converter employs the conventional voltage-mode control scheme for better noise

immunity [37] with type-III compensation and therefore there is no current sensing

circuit at all.

When the load current is high, the converter is controlled by PWM and operates in

35
the CCM with its switching frequency fixed at its norminal value fS. With light load,

the converter operates in the DCM and the switching frequency is selected among a

pre-defined set of values. In the DCM, the switching duty cycle, D, heavily

depends on the load current as;

2VOUT L
D  I OUT (4.2)
V IN V IN  VOUT TS

where VIN and VOUT are the input and output voltage levels of the converter,

respectively, L is the magnitude of the switching inductor, TS is the clock cycle

time, and IOUT is the load current. From this, the on-time ton of the power transistor

can be found as;

2VOUT LTS
ton   I OUT . (4.3)
VIN VIN  VOUT 

From the equation (4.3), the on-time of the power transistor is a function of the

load current. Therefore the load current can be indirectly sensed by monitoring the

on-time of the power transistor and the switching frequency can be determined

based on the monitored on-time.

The on-time of the power transistor can be detected by the simple circuit shown in

Fig. 4.12. When the gate voltage VP of the power transistor MP is LOW (HIGH),

the capacitor CC is charged (discharged) by the current source IC (ID). For lighter

load, the on-time of the power transistor MP becomes shorter and the peak voltage

level of VC decreases. Therefore, the magnitude of the load current can be indirectly

monitored from the peak voltage level of VC without any costly current sensing

circuit. After ton, the peak voltage level of VC is tonIC/CC and from the equation (3)

36
 IC VREF_H COMP1
+
VOC1 Falling edge detector
VUP
M1 -
VP VC
COMP2
+
M2 CC VR VQ VDN
VREF_L - R Q
ΦCLK
S
ID

Rising edge detector

VP_E

Fig. 4.12. On-time detection circuit.

the peak voltage level VC can be represented as;

IC 2VOUT LTS
VC , peak    I OUT . (4.4)
CC VIN VIN  VOUT 

From (4.4), if the switching frequency is to be changed at IOUT=100-mA, the peak

voltage level of VC has to be compared with the reference voltage of 1.32-V when

IC=50-μA, CC=20-pF, TS=2-μs, VIN=9-V, VOUT=5-V, and L=10-μH. In order to

prevent the oscillation of the switching frequency, a hysteresis is given by setting

VREF_H and VREF_L to be 1.86-V and 0.93-V, respectively because the peak voltage

level of VC can be doubled or halved temporarily during the transition of the

switching frequency. In the steady state, the peak voltage level of VC would be

placed between VREF_H and VREF_L.

37
 ILOAD

VREF_H

VREF_L
VC

VP

VRAMP
VEA

VR

ΦCLK

VQ
VP_E

VDN

(a)

ILOAD
VREF_H

VREF_L
VC

VP

VRAMP
VEA

ΦCLK

VOC1

VUP

(b)

Fig. 4.13. Timing diagram of the on-time detection circuit when the load current (a)

decreases and (b) increases.

38
 The gate driving loss is proportional to the square of the input voltage VIN and

therefore the switching frequency is desired to be lower for higher VIN to get higher

power efficiency. The proposed switching frequency control scheme provides this

feature. From (4.4), the switching frequency changes at larger load current for a

higher input voltage if the output voltage and reference levels are fixed. If the

switching frequency is desired to change at other load current level according to the

variation of the input voltage, the reference level has to be adaptively changed

according to the equation (4.4).

Fig. 4.13 shows the timing diagram of the on-time detection circuit when the load

current changes. If the load current decreases, the on-time of the power transistor

MP is reduced, decreasing the peak voltage level of VC. When the peak voltage

level of VC becomes lower than VREF_L, the VDN pulse is generated to decrease the

switching frequency. If the load current increases, the peak voltage level of VC

increases. When the peak voltage level of VC becomes higher than VREF_H, the VUP

pulse is generated to increase the switching frequency. If all the variables except TS

and IOUT are constant, the load current IOUT is inversely proportional to the

VDN VDN VDN

VUP fS fS/2 fS/4 fS/8 VDN

VUP VUP VUP

Fig. 4.14. The state transition diagram of the frequency selection circuit.

39
 TABLE 4.1
COMPARISON WITH OTHER CONTROL SCHEMES FOR IMPROVED LIGHT LOAD
EFFICIENCY

Automatic Predictable Improvement of

Light load Additional
Control method operation according switching light load
detection components
to load current frequency efficiency
Voltage swing
6.3-%
[19] modulation N/A X O* O
(IOUT=10-mA)
of gate driving signal
Hybrid of PFM and Peak level of Costly current
[22] O X N/A
PWM inductor current sensing circuit

Modulation of power 6.3-%

[29] External control X X O
transistor width (IOUT=10-mA)

[31] Resonant gate driving N/A Discrete inductor N/A O N/A

Recycling network
Charge re-cycling of
(On-chip inductor, 4.4-%
[32] gate capacitor, voltage N/A O O
capacitor, two (IOUT=20-mA)
swing modulation
switches)
2-%
[34] Nonlinear inductor External control Nonlinear inductor N/A X (IOUT=500-mA)

Selectable switching Peak level of Costly current 22-%

[35] O O (IOUT=10-mA)
frequency inductor current sensing circuit
This Selectable switching On time of 24-%
X O O (IOUT=10-mA)
work frequency power transistor
* Enabled by complicated control circuitry.

switching cycle time TS as is clear from the equation (4.4). This means the

switching frequency is halved (doubled) when the load current is halved (doubled).

The switching frequency is selected among the pre-defined four values fS, fS/2, fS/4,

and fS/8 based on the state transition diagram shown in Fig. 4.14. Because the

switching frequency is selected among the known values, the unwanted spectral

components on the output of the DC-DC converter are predictable and can be

filtered out using off-chip high-Q harmonic-trap filters regardless of the load

condition [35]. The outputs VF1 and VF0 of the finite-state machine (FSM) can be

represented as;

40
 VF1  VF1VF 0  VF1VF 0VDN  VF1VF 0VUP (4.5)

VF0  VF1VUP VDN  VF 0VUP VDN  VF1VF 0VUPVDN (4.6)

where V+ is the next state value.

Although the current design applies the proposed switching frequency selection

technique to a voltage-mode controlled buck converter, it can be applied to any

type of switch mode DC-DC converter. The proposed technique requires neither

complicated current sensing circuit nor additional off-chip control. Table 4.1

compares the proposed switching frequency selection scheme with the prior works

on the improving the light-load power efficiency of a switching DC-DC converter.

Because the output voltage of the DC-DC converter is supplied to the battery

charger, the output voltage regulation specifications such as line regulation, load

regulation, and voltage ripple are not considered severely in this study. Instead, the

power efficiency is considered strictly, because lower power efficiency induces

temperature heating and malfunction of wireless power transmission system.

The output voltage ripple may be increased at the light load current due to the

reduced switching voltage as in the PFM scheme. If the other methods to increase

the power efficiency at light load condition such as transistor width modulation and

gate swing voltage modulation are employed, the output voltage ripple may not be

increased. But the power efficiency cannot be increased greatly due to increased

On-resistance of power transistors. Therefore, the switching frequency selection

technique according to the load current is employed because the power efficiency is

the most important specification in wireless power transmission system.

41
4.3.3. Sub-circuit design of the proposed buck converter

In this chapter, sub-circuit design of the proposed buck converter with an

automatic load-adaptive switching frequency selection technique for wireless

power receiver is described in detail.

4.3.3.1. Clock and ramp generator

The clock and ramp generator shown in Fig. 4.15 consists of a controllable current

source, two comparators, and a latch. When the ramp signal VRAMP is higher than

the reference VH, the clock signal ΦCLK becomes HIGH, which turns on the nMOS

switches of the charge pump and discharges the capacitor CR. The clock signal

ΦCLK becomes LOW when the ramp signal VRAMP is lower than the reference VL,

which turns on the pMOS switches of the charge pump and charges the capacitor

8 1 4 1 2 1 1 1
COMP1
VH +
ΦCLK
-
ΦCLK 4to1 VRAMP
MUX COMP2
CR +
VL -

VF1VF0
8 2 4 2 2 2 1 2

Fig. 4.15. Clock and ramp generator.

42
 Rising edge detector
VN VQD VRESET
S Q D Q
ΦCLK
R CK

VIND + RESET
VZERO 3 Bit VENA
CLK OUT
- VDD counter
IN

Fig. 4.16. DCM detection circuit.

CR. The frequency control signal VF1 and VF0 from the FSM are the control inputs

of the 4:1 multiplexer which controls the amount of pumping current. Because the

values of charging (discharging) currents have 8I1 (8I2), 4I1 (4I2), 2I1 (2I2), and I1

(I2), the frequencies of ramp signal have four values fS, fS/2, fS/4, and fS/8.

4.3.3.2. DCM detection circuit

Because the switching frequency is fixed in the CCM and changes only in DCM,

we have to detect whether the switching converter operates in the CCM or DCM

with the DCM detection circuit in Fig. 4.16.

The voltage level of the switching node VIND is slightly higher than VSS if the

inductor current becomes zero when the nMOS switch MN is turned-on. This means

the converter operates in the DCM and the VZERO pulse is generated. Fig. 4.17

shows the timing diagram of the DCM detection circuit when the operation mode

of the DC-DC converter changes from the CCM to DCM and from the DCM to

CCM, respectively.
43
 IL

VN
VIND
VGND

VZERO

VQD

ΦCLK

VRESET

VENA

(a)

IL

VN
VIND
VGND

VZERO

VQD

ΦCLK

VRESET

VENA

(b)

Fig. 4.17. Timing diagram of the on-time detection circuit when the load current (a)

decreases and (b) increases.

44
 When the operation mode of the DC-DC converter changes from the CCM to

DCM, the enabling signal of the automatic frequency selection circuit, VENA, is

generated after eight consecutive pulses of VZERO to ignore any temporary DCM

operation. During the load current transient, the converter can temporarily operate

in the DCM. When the operation mode of the switching converter changes from the

DCM to CCM, VZERO is not generated because the voltage level of the switching

node VIN is continuously lower than VSS when the nMOS switch MN is turned-on.

Then, the reset signal VRESET is generated to disable the automatic frequency

selection circuit during the CCM operation.

4.3.3.3. Dead time controller and driving buffer

The dead time controller and driving buffer are shown in Fig. 4.18. After the

pMOS switch MP is turned-off, the nMOS switch MN is turned-on when the voltage

level of the switching node VIND is lower than VSS. This minimizes the conduction

time through the body-drain diode of the nMOS power transistor for higher

efficiency at light-load condition and prevents the simultaneous conduction of the

power transistors, which would cause shoot-through currents. The nMOS switch

MN is turned off when the zero current detection signal VZERO of the DCM detection

circuit or the clock ΦCLK are generated. The driving buffer consists of inverter chain

of gradually increasing size to drive the large gate capacitance of the power

transistors.

45
 DC-DCVconverter
IND + Active
Falling edge rectifier
detector
-

Power transistor
VP S Q Driving buffer
Power transistor VN
VZERO R
ΦCLK
Driving buffer
VD VP
Driving buffer

Protection
LDO
Fig. 4.18. Dead time controllerDriving bufferbuffer.
and driving
Controller
Clock & ramp Comparator with zero delay
generator
BGR Frequency BGR LDO
selection

Fig. 4.19. Chip microphotograph.

4.3.3.4. Protection circuit

In order to protect the proposed buck converter with an automatic switching

frequency selection circuit, over-output voltage protection (OOVP) and over-current

protection (OCP) circuits are employed. The operations of the OOVP and OCP are

the same as the conventional ones [38]-[40].

4.4. Measurement results

The wireless power receiver has been implemented in a 0.35-μm 2P4M BCDMOS

technology in two chips, one for the active rectifier and the other for the DC-DC

46
 VOUT VOUT

VN VN
VIN_A VIN_A

Reverse leakage

fRES=3.23MHz fRES=3.23MHz
without delay compensation with delay compensation

(a)

VOUT VOUT

VN VN
VIN_A VIN_A

Reverse leakage

fRES=6.78MHz fRES=6.78MHz
without delay compensation with delay compensation

(b)

Fig. 4.20. Measured waveforms of the proposed active rectifier when the resonant

frequency is (a) 3.23-MHz and (b) 6.78-MHz.

buck converter each of which occupies 9.7-mm2 and 8.6-mm2, respectively. The

chip micrographs are shown in Fig. 4.19. The output of the active rectifier and DC-

DC converter are filtered by 10-μF capacitors with equivalent series resistance

(ESR) smaller than 50-mΩ and the inductor of the DC-DC converter is 10-μH with

ESR of 100-mΩ. The switching frequency of the converter is 1-MHz/N where N=2i

and i is automatically selected among 0, 1, 2, and 3 according to the load current.

At heavy loading, the converter operates in the CCM and the switching frequency

is 1-MHz.
47
 IL
IL

VOUT VOUT

VIND VIND

VRAMP VRAMP

(a) (b)

IL IL

VOUT VOUT

VIND VIND

VRAMP VRAMP

(c) (d)

Fig. 4.21. Measured waveforms when the load current is (a) 300-mA, (b) 70-mA,

(c) 35-mA, and (d) 15-mA for the input voltage of 9.0-V and output voltage of 5.0-

V.

Fig. 4.20 shows the measured waveforms of the active rectifier when the resonant

frequency is 3.23-MHz and 6.78-MHz, respectively. Without the proposed DLL-

based delay compensation, the reverse leakage current exists because the gate

voltage of the nMOS power transistors is HIGH for some duration even after the

48
 IOUT 500mA
10mA
VOUT
600mV
VRAMP

IL

(a)

IOUT 100mA
10mA
VOUT
VRAMP

IL

(b)

Fig. 4.22. Measured waveforms when the load current changes (a) between 10-mA

and 500-mA (b) 10-mA and 100-mA.

AC input voltage becomes positive. The DLL-based delay compensation scheme

improves the power conversion efficiency of the active rectifier by 3.5-% and 8.0-%

when the resonant frequency is 3.23-MHz and 6.78-MHz, respectively.

49
 1/8fS 1/4fS 1/2fS fS

(a)

1/8fS 1/4fS 1/2fS fS

(b)

1/8fS 1/4fS 1/2fS fS

(c)

Fig. 4.23. Measured power efficiency versus the load current when the input

voltage is (a) 6.0-V, (b) 9.0-V, and (c) 12.0-V.

50
 Fig. 4.21 shows the measured output waveforms when the load current is 300-mA,

70-mA, 35-mA, and 15-mA, respectively for the input voltage of 9.0-V and output

voltage of 5.0-V. Fig. 4.22 shows the output waveforms when the load current

changes between 10-mA and 500-mA and between 10-mA and 100-mA with the

intervals of 250-µs, respectively when the input voltage is 9.0-V and output voltage

is 5.0-V. The output voltage settles within 100-µs.

The Measured power efficiency of the buck converter versus the load current is

shown in Fig. 4.23 when the input voltage is 6.0-V, 9.0-V, and 12.0-V. For the input

voltage of 12.0-V, the power efficiency is improved by 24.0-% for the load current

of 10-mA when the proposed load-adaptive frequency selection technique is

employed. Because the gate driving power loss is dominant at light load condition

[19], [41], the efficiency improvement at the light load condition is very natural by

lowering the switching frequency with the proposed technique. The maximum

power efficiency is 92.4-% for the load current of 500-mA when the input voltage

is 6.0-V.

Fig. 4.24 shows the measurement set-up of the wireless power receiver connected

to the battery charger of a mobile phone. The overall power efficiency of the

magnetic resonator is 3.23-MHz and 6.78-MHz, respectively at the output power of

3.0-W. Fig. 4.25 shows overall power efficiency of the wireless power receiver

versus the output power. The performance of the wireless power receiver is

summarized in Table 4.2.

To increase the power conversion efficiency of the wireless power receiver the

follow-up research is progressed as following subchapter.

51
 Resonator
Active DC-DC Mobile
rectifier converter phone

Fig. 4.24. Measurement set-up of the wireless power receiver charging a mobile

phone.

[%]
80

70

60

50

40

30
fRES3.23MHz
=3.23MHz
20
fRES6.78MHz
=6.78MHz
10

0
00.2 0.5
0.6 1.0
1 1.5
1.4 1.8 2.0 2.2 2.5
2.6 3.0
3
Output power [W]

Fig. 4.25. Power efficiency of the wireless power receiver versus the output power.

52
 TABLE 4.2.

PERFORMANCE SUMMARY OF THE PROPOSED WIRELESS POWER RECEIVER

Active rectifier DC-DC converter

Technology 0.35-µm BCDMOS 2P4M
Resonant frequency
fRES = 3.23-MHz or 6.78-MHz
of magnetic resonator
Silicon area 9.7-mm2 8.6-mm2
Input voltage 4.0 ~ 8.0-VAC,rms 5.5 ~ 12.0-V
Inductor / ESR - 10-µH / 100-mΩ
Filtering capacitor 10-µF with ESR < 50-mΩ
1-MHz/2N
Switching frequency -
(n= 0~3)
Output voltage - 5.0-V
Load regulation 0.05-mV/mA @ VIN=9.0-V
Line regulation 0.5-mV/V @ IOUT=300-mA
Power conversion 81-% @ fRES=3.23-MHz
92.5-% @ POUT=3-W
efficiency 74-% @ fRES=6.78-MHz

Overall power conversion 75-% @ fRES=3.23-MHz, POUT=3-W

efficiency 68-% @ fRES=6.78-MHz, POUT=3-W

4.5. Follow-up research of the wireless power receiver

Although the power conversion efficiency of the proposed active rectifier can be

increased with the delay compensation scheme, the higher power conversion

efficiency of the wireless power receiver for mobile devices is desired. If the

resonant frequency of the resonator is increased to reduce the resonator size, the

power efficiency of the proposed active rectifier is decreased due to the increased

driving power loss.

53
 CRECT
VO_REC

DC-DC
Rectifier Converter MP
Buff.
VDD
Matching DS1 DS2
VIND
Network Gate
VIN_A Driver Buff.
CM1 MN
AC VSD L
LM
Input CM2 VIN_B
Q CC2
VOUT
CP1 R S RC1 CC1 RC2
CP2 CO
MNR1 MNR2 VDD CC3 RF1 IO
ΦCLK
VDD -
-
CM1 VREF
+ RF2 ROPT
CM2 + EA
COMP1
VRAMP

Load VDD GND

+ VOD RD1 Controller
Modulator - VREF RD2
BGR &
COMP2 LDO
VDD
VCOMM ΦCLK
VREF Clock VENA
VRAMP Protection
Soft-start & Ramp
MM1 MM2 Circuit
Generator

Fig. 4.26. Schematic of the wireless power receiver for mobile devices of follow-

up research.

Fig. 4.26 shows the developed wireless power receiver of follow-up research for

mobile devices. With the various simulation, the power efficiency of the passive

rectifier consisting of combination of the Schottky diodes and cross-coupled

transistors as shown in Fig. 3.11-(c) is higher than that of the proposed active

rectifier at the resonant frequency of 13.56-MHz. Therefore, the active rectifier is

replaced by the rectifier consisting of combination of the Schottky diodes and

cross-coupled transistors. Also, an over-power protection block is added to prevent

54
 DC-DC converter
Rectifier

Power
Transistor

Controller

Load modulator

Fig. 4.27. Chip microphotograph of the wireless power receiver of follow-up

research.

the malfunction of the wireless power receiver.

At the very start of the wireless power receiving and transition from the charging

of multiple devices to the charging of single device, the received AC power level

and therefore the rectified voltage level VO_REC may be higher than the gate oxide

breakdown voltage of the transistors. If the resistor divided voltage level VOD is

higher than the pre-defined reference voltage, the transistors connected to the

output of the comparator COMP2 and therefore the capacitors CP1 and CP2 are

connected between the AC inputs and GND. Thus the matching characteristic

55
Fig. 4.28. Test printed circuit board of wireless power receiver of follow-up

research.

[%]
100

90

80

70
Efficiency

60

50

40

30
6.78MHz
20
13.56MHz
10

0
0.6 1.2 1.8 2.4 3 3.6 4.2 4.8 5.4 6 POUT[W]

Fig. 4.29. Power efficiency of the wireless power receiver of follow-up research

versus the output power.

between wireless power transmitter and receiver can be poor and therefore the

received AC power is decreased. In order to prevent any oscillatory operation of the

over-power protection circuit, the comparator has a non-zero hysteretic window.

56
 Charging Charging
Impedance Wireless
voltage current
Resonator matching power
network receiver

Mobile phone

Fig. 4.30. Measurement set-up of charging a mobile phone.

Also, load modulation transistors are integrated in chip to transmit the information

of device identification and charging status.

The wireless power receiver of follow-up research has been integrated in a 0.35-

µm BCDMOS technology in one chip whose area is 25.0-mm2. Fig. 4.27 shows the

chip microphotograph. The resonant frequency of this work is 6.78-MHz and

13.56-MHz of ISM band frequencies. The inductor and capacitor of the DC-DC

converter are 4.7-µH with ESR of 100-mΩ and 10-µH with ESR of 50-mΩ,

respectively. The filtering capacitor of the rectifier is 10-µF.

57
 Impedance Wireless Charging Charging
Resonator matching power voltage current
network receiver

Tablet PC

Fig. 4.31. Measurement set-up of charging a tablet PC.

F i g . 4.32 . Measurement set-up of charging a mobile phone with in-band

communication.

58
 Fig. 4.33. Measured waveforms of in-band communication.

The test printed circuit board of this work is shown in Fig. 4.28. The wireless

power receiver IC is connected to printed circuit board by chip on board technique.

Fig 4.29 shows overall power conversion efficiency of the wireless power receiver

versus the output power. The maximum efficiency is 81.7-% when the output

power is 2.5-W and resonant frequency is 6.78-MHz.

Fig. 4.30 shows the measurement set-up of charging a mobile phone. The

charging voltage and current is 5.07-V and 0.6-A, respectively. And the

measurement set-up of charging a tablet PC is shown in Fig. 4.31. The charging

current is increased as 1.0-A. Fig. 4.32 shows the measurement set-up of charging a

mobile phone with in-band communication. Fig. 4.33 shows measured waveforms

of in-band communication [42]. The modulated data (yellow) packet by subcarrier

of 150kHz is generated from an external MCU. The data packet modulates the gate

59
 TABLE 4.3.

PERFORMANCE SUMMARY OF THE PROPOSED WIRELESS POWER RECEIVER OF

FOLLOW-UP RESEARCH

Technology 0.35-µm BCDMOS 2P4M

Resonant frequency
of magnetic resonator
Silicon area
Input voltage
Inductor / ESR
Filtering capacitors
Switching frequency
Output voltage
Overall power conversion
efficiency
fRES = 6.78-MHz or 13.56-MHz
25-mm2
4.0 ~ 8.0-VAC,rms
10-µH / 100-mΩ
10-µF with ESR < 50-mΩ
1-MHz
5.0-V
81-% @ fRES=6.78-MHz, POUT=3-W
80-% @ fRES=13.56-MHz, POUT=3-W

of the MOS transistor and generates the modulated RX waveform (pink) by

changing the impedance in front of the rectifier. By doing this, the transmitting

power signal (blue) can also be modulated in front of the power amplifier in the TX.

This signal is coupled by a resistor divider and then is fed into the input of a

demodulator. The output of a demodulator is compared to a reference level by a

comparator and the output of a comparator is the recovered data (green). This is the

same as the original data (01011010110). The performance of the wireless power

receiver is summarized in Table 4.3.

In measurement of over-input voltage protection circuit, the schottky diodes and

cross-coupled nMOS transistors are damaged due to higher voltage stress. Because

the output voltage VO_REC of the rectifier cannot be generated correctly when the

schottky diodes or cross-coupled nMOS transistors are damaged, the over-input

60
voltage protection circuit cannot be operated. If the reference voltage VREF in over-

input voltage protection circuit is compared to the resistor divided input AC voltage,

the over-input voltage protection circuit may be operated. To prevent the over-input

voltage, thyristors are connected to the input AC voltage of the wireless power

receiver.

61
 5. Proposed Wireless Power Transceiver for Device to

Device Wireless Power Transmission

In this chapter, the proposed wireless power transceiver for device to device

wireless power transmission is explained. The wireless power transceiver enables a

mobile device to receive and transmit power wirelessly. When transmitting power,

a mobile device can function as a wireless power station for another mobile device.

To decrease the form-factor of the wireless power transceiver, the proposed bi-

directional DC-DC converter has been developed which can function as either a

buck converter or a boost converter. Because the DC-DC converter can perform a

both the buck and boost operation, only one inductor is required and the form-

factor can be greatly decreased. During the receiver mode of the wireless power

transceiver, the bi-directional DC-DC converter performs the buck operation to

supply regulated voltage for battery charger. During the transmitter mode, the DC-

DC converter operates as the boost converter to make a proper voltage which

determines the output power of the power amplifier.

5.1. Necessity of the wireless power transceiver

If a mobile device is capable of not only receiving but also transmitting power

wirelessly, it can be utilized as a mobile wireless power charging station for another

mobile device which is power-hungry. For example, a mobile phone can charge a

Bluetooth handset, hearing aid, or another mobile phone wirelessly with its battery

62
 Transmitter mode
Analog Receiver mode
switch
DC-DC
DC-AC converter Switch
converter

Resonator DC-DC Battery Battery

Rectifier
converter charger

Impedance
matching

Fig. 5.1. Simplified architecture of a wireless power transceiver.

as the power source. For a mobile device to be capable of both receiving and

transmitting power wirelessly, a wireless power transceiver is required. In the

following chapter, the benefits and control methods of the proposed wireless power

transceiver are presented in detail.

5.2. Block diagram of the proposed wireless power receiver

Fig. 5.1 shows the simplified architecture of a wireless power transceiver. The

analog switch connects the magnetic resonator to the impedance matching network

and the DC-AC converter in the receiver mode and the transmitter mode,

respectively. The direction of the power flow in the transmitter mode is the opposite

of that in the receiver mode and therefore there have to be two DC-DC converters

and thus two inductors, meaning large form factor because of the size of the power

inductor. If the direction of the power flow of a DC-DC converter can be made bi-

directional as in Fig. 5.2, a wireless power transceiver can be implemented with only

63
 Transmitter mode
Receiver mode
Analog
switch
DC-AC converter Analog
switch
Bi-directional
switching
DC-DC
converter

AC-DC Battery
Resonator Battery
converter charger

Impedance
matching

F i g. 5.2 . Proposed wireless power transceiver with a bi-directional DC-DC

converter.

one inductor, allowing small form factor. Generally, the size of the inductor and DC-

DC converter is big because the DC resistance of inductor and On-resistance of the

power transistor in DC-DC converter are inversely proportional to size of the

inductor and DC-DC converter. The proposed bi-directional DC-DC converter can

reduce the number of inductor and DC-DC converter of the wireless power

transceiver, which reduces the form-factor and cost. When AC power is received

from the magnetic resonator, the DC-DC converter is powered by the AC-DC

converter and provides DC power to the battery charger. When power is transmitted,

the DC-DC converter is powered directly by the battery to generate appropriate DC

power for the DC-to-AC converter. The impedance matching network ensures

matching between the resonator and wire power receiver. The detailed design of the

wireless power receiver is explained in the following chapters.

64
 VIN_OUT1 VIND VIN_OUT2
MP
LD
VIN_HIGHER
CIN CD
Buff.
VIN_HIGHER CC2
VOUT
MN RC1 CC1 RC2
Buff.
Driver VDD CC3 RF1
control VDD
- - Battery VBATT
VREF charger
Q R + RF2 RF_OPT Battery
Tx
+ EA
Q S VRAMP
ΦCLK
COMP
Rx
VIN_HIGHER VDD Switch
VIN_HIGHER BGR &
& VOUT LDO
Selection VOUT Regulator

GND
Clock & Ramp Protection
Soft-start
Generator Circuit

Fig. 5.3. Bi-directional DC-DC converter.

5.3. Proposed bi-directional DC-DC converter

Fig. 5.3 shows the bi-directional DC-DC converter. The node VIN_OUT1 is

connected to the rectifier output and the power supply of the class-E amplifier. In the

receiver mode, the class-E amplifier is disabled and the rectifier output VIN_OUT1

becomes the input of the DC-DC converter which operates as a buck converter. In

the transmitter mode, the battery charger is bypassed by the switch and the battery

output VBATT becomes the input of the DC-DC converter which operates as a boost

converter to generate a sufficiently high voltage level to supply power to the class-E

power amplifier.

The DC-DC converter can operate in either the continuous-conduction mode

65
(CCM) or discontinuous-conduction mode (DCM) depending on the load current

level [43]. The DC-DC converter employs the voltage-mode control scheme with the

type-III compensation for good noise immunity and fast transient response [37]. The

passive components including capacitors and resistors are integrated in chip to

reduce the form-factor of the wireless power transceiver. The external resistor RF_OPT

is used to control the regulated output voltage for various applications such as digital

camera or smart watch devices.

In order to determine the size of the power transistors ensuring the maximum

power efficiency, the power efficiency has been simulated for various input voltage

VIN and output current IO. If the size of the power transistors is increased (decreased),

the increased driving (conduction) power loss is larger than the decreased

conduction (driving) power loss. And also, the high side power transistor is selected

to the pMOS power transistor, because the high side transistor of the nMOS power

transistor requires bootstrap diode and external capacitor, which may increases the

form-factor of the wireless power transceiver.

To prevent the in-rush current of the inductor, the reference voltage is slowly

generated by the soft-start circuit and thus the inductor and power transistors can be

protected. The detailed circuit design of the proposed bi-directional DC-DC

converter is described in the following chapter.

5.3.1. Circuit design of the proposed bi-directional DC-DC

converter

In this chapter, sub-circuit design of the proposed bi-directional DC-DC converter

66
for wireless power transceiver is described in detail.

5.3.1.1 VIN_HIGHER and VOUT selection circuit

In both the receiver and transmitter modes, VIN_OUT1 is higher than VIN_OUT2 and

therefore it has to be the input of the LDO regulator. In the transmitter mode,

however, VIN_OUT1 can be lower than VIN_OUT2 before VIN_OUT1 reaches its steady state

value during which VIN_OUT2 has to be the input of the LDO regulator. The

VIN_HIGHER and VOUT selection circuit in Fig. 5.4 determines which one has higher

voltage level between VIN_OUT1 and VIN_OUT2 and the higher one is selected as

VIN_HIGHER to be used as the power supply of the LDO regulator and the buffers

driving the power transistors MP and MN. The gate voltages of the transistors MPS1

and MPS2 are VIN_OUT2-|VTHP| and VIN_OUT1-|VTHP|, respectively and thus only one

transistor is turned on whose source node has higher level. The body of the

VIN_HIGHER selection VOUT selection

VIN_HIGHER
VIN_OUT1 VIN_OUT2
TGATE1
MPS5 MPS6 VIN_OUT1
MPS1 MPS2
VDA VOUT
MPS3 VDB VIN_OUT2
MPS4 Tx
MNS1 MNS2
Rx TGATE2
RS1 RS2

Fig. 5.4. VIN_HIGHER and VOUT selection circuit.

67
 MEP3 MEP6 MEP7
VB1

ΦCLK

MEP4 MEP5
VINP MEP1 MEP2 VB4
VO

VB3
VINN MEN3 MEN4
ΦCLK ΦCLK

VB2
MEN1 MEN2

Fig. 5.5. Error amplifier.

transistors MPS1 and MPS2 are tied to VIN_HIGHER to prevent the forward bias of the

parasitic diodes. Depending on the mode of operation, the VOUT selection circuit

connects VIN_OUT1 or VIN_OUT2 to the feedback network.

5.3.1.2 Error amplifier for output voltage

If the error amplifier EA shown in Fig. 5.3 has input offset voltage, the regulated

output voltage is different from the reference voltage. Also, the input offset voltage

is amplified according to the resistor divided ratio when the output voltage is

compared to the reference voltage. For example, the difference voltage between

output voltage and target output voltage is 120-mV when the input offset voltage of

the error amplifier is 30-mV and the resistor divided ratio between the resistor RF1
68
 M PR3
M PR1 M PR5
IC
M PR4
MPR2 MPR6 VH
Φ CLK
EA 3
VR ΦCLK
M PR7
M NR1 VRA MP

MNR6 C
R

RR1 MNR3 M NR5 VL

IDIS
MNR2 M NR4

Fig. 5.6. Clock and ramp generator.

and RF2 is 4:1. For accurate control of the output voltage, the chopping technique as

shown in Fig. 5.5 is applied to the error amplifier EA to compensate the input offset

voltage.

5.3.1.3 Clock and ramp generator

The clock generator shown in Fig. 5.6 has a similar structure to the one described

in [44]. The voltage-to-current converter consisting of the operational amplifier EA3,

the transistor MNR1, and the resistor RR1 generates the reference current VR/RR1. Then

the charging current IC is given as;

VR W / L MPR 5
IC   . (5.1)
RR1 W / L MPR1

When the clock signal ΦCLK is LOW, the capacitor CR is charged up by IC and the

ramp signal VRAMP rises with the slope IC/CR. When the ramp signal VRAMP becomes

69
higher than the reference level VH of the upper comparator, the clock signal ΦCLK

becomes HIGH and the transistor MNR6 is turned on to discharge the capacitor CR.

Now, the ramp signal VRAMP falls and when it becomes lower than the reference level

VL of the low comparator, the clock signal ΦCLK becomes LOW again. In this way,

the ramp signal VRAMP and the clock signal ΦCLK are generated.

5.3.1.4. Protection circuit

In order to protect the proposed bi-directional DC-DC converter with over-output

voltage protection (OOVP) and over-current protection (OCP) circuits are employed.

The operations of the OOVP and OCP are the same as the conventional ones [38]-

[40].

5.3.2. Stability of the proposed bi-directional DC-DC converter

Because the proposed DC-DC converter operates bi-directionally, stability of the

proposed bi-directional DC-DC converter must be considered. The DC-DC

converter employs the voltage-mode control scheme with the type-III compensation

for good noise immunity and fast transient response. Two left half plane zeros

generated by the resistor RC1 and the capacitor CC1, and the resistor RF1 and the

capacitor CC3 compensates the complex pole generated by the power inductor LD and

the output capacitor CD or CIN according to the operation mode. Also, two poles

generated by the compensation network is generated at the higher frequency than the

switching frequency to reduce the output voltage ripple. Fig. 5.7-(a) and -(b) show

the open loop gain and phase plot of the proposed bi-directional DC-DC converter
70
 100

Magnitude (dB)
50

-50
45

0
Phase (deg)

-45

-90

-135 77º
-180 0 1 2 3 4 5
10 10 10 10 10 10 106 107
Frequency (Hz)

(a)
100
Magnitude (dB)

50

-50
45

0
Phase (deg)

-45

-90

-135
60º
-180
100 101 102 103 104 105 106 107
Frequency (Hz)

(b)

Fig. 5.7. The open loop gain and phase of the proposed DC-DC converter operates

in (a) receiver (b) transmitter mode.

operates in receiver mode and transmitter mode, respectively. In the receiver mode,

the cutoff frequency is 300-kHz and the phase margin is 77˚ when the input voltage

is 6.0-V and the output voltage is 5.0-V as shown in Fig. 5.7-(a). In the transmitter

mode, the cutoff frequency is 200-kHz and the phase margin is 60˚ when the input

voltage is 3.7-V and the output voltage is 5.0-V as shown in Fig. 5.7-(b).

71
5.4. Circuit design of the proposed wireless power transceiver

Fig. 5.8 shows the detailed architecture of a wireless power transceiver. The

design consideration and technique for high power efficiency is described in the

following subchapters.

5.4.1. Impedance matching circuit

To ensure the proper matching between the resonator and wireless power receiver,

impedance matching circuit has been designed. The impedance matching network is

consisting of one inductor and two capacitors as shown in Fig. 5.8. The magnetic

resonator has impedance of 50-Ω at the resonant frequency of 6.78-MHz. In normal

operation, the output load current and output voltage of the bi-directional DC-DC

converter is 1.0-A and 5.0-V, respectively. Therefore, the impedance of the load is

assumed to 5-Ω because the power transistors or Schottky diode of the AC-DC

converter and DC-DC converter has low ON-resistance. Thus the impedance

network has a impedance of 50-Ω to 5-Ω from the resonator to AC-DC converter.

For higher quality factor of the impedance matching network, air core inductor is

used.

72
 Analog Class-E amplifier
switch (DC-AC conversion) Switch
LRFchoke
LPA

Oscillator Battery Battery

CPA2 CPA1 & driver charger

Bi-directional

73
DC-DC converter

Resonator
DS1 DS2
Transmitter mode
Receiver mode

MN1 MN2
Impedance
matching
Passive rectifier

Fig. 5.8. Detailed architecture of a proposed wireless power transceiver.

5.4.2. AC-DC converter

The AC-DC converter employs the passive rectifier consisting of two Schottky

diodes and cross-coupled nMOS power transistors for higher power conversion

efficiency. While an active rectifier is more power efficient at low to medium

resonant frequency, a passive rectifier is preferred at higher resonant frequency

because the driving power loss of an active rectifier becomes dominant. If the

passive rectifier is implemented with the P-N junction diodes, the passive rectifier

has poor power conversion efficiency because P-N junction diodes have large drop

voltage and slow reverse recovery time. Therefore, the Schottky diodes which have

lower drop voltage and fast reverse recovery time is used to higher power

conversion efficiency. Low-side cross-coupled nMOS power transistor is used to

reduce the drop voltage of the Schottky diode, thus the passive rectifier consisting of

Schottky diode and nMOS power transistor has higher power conversion efficiency

than that consisting of four Schottky diodes. If the high side Schottky diode is

replaced by the cross-coupled pMOS power transistor, the output of the passive

rectifier can be shorted to the ground when the voltage swing of the AC input is

larger than twice the threshold voltage of the transistors. Thus the reverse current

can be generated and the power conversion efficiency is very poor.

In this proposed wireless power transceiver, the discrete Schottky diodes and

cross-coupled nMOS power transistor is used because the discrete Schottky diode

has lower drop voltage and the discrete nMOS power transistors has lower On-

resistance than the component that is implemented by integrated circuit due to the

fabrication limitation.
74
 TABLE 5.1. COMPARISON OF THE CLASS-D AND CLASS-E POWER AMPLIFIER

` Class-D Class-E

Switching two transistors with

Complexity Switching one transistor
non-overlapping control
Lower efficiency due to drain- High efficiency due to reduced
Efficiency
source capacitor switching loss

Voltage stress VCC 3.562  VCC

Output power capability POUT 2.847  POUT

Output component - RF Choke or Feed inductor

Proper frequency* fOSC < 3-MHz fOSC > 3-MHz

* Reference [45]

5.4.3. Class-E power amplifier

The power amplifier of the proposed wireless power transceiver employs the

class-E power amplifier for higher power conversion efficiency. Because the linear

power amplifier such as class-A, class-B, and class-AB has poor power conversion

efficiency due to the power dissipation of the power transistors, the switching power

amplifier such as class-D, class-E, and class-F is considered to wireless power

transceiver. With the design consideration of complexity, form-factor, efficiency,

voltage stress, proper frequency, the class-D and class-D is selected to candidate of

the wireless power transceiver.

Although the class-E power amplifier has higher drain-source voltage, the class-E

power amplifier has higher power conversion efficiency due to its soft-switching

75
nature [46]. Also, the class-D power amplifier requires two power transistor and

non-overlapping signal generation circuit. Therefore, the class-E power amplifier is

adapted to this proposed wireless power transceiver. Because the discrete nMOS

power transistor has lower On-resistance, the class-E power amplifier is

implemented with the discrete nMOS power transistor. The choke inductor of the

wireless power transceiver is air core inductor due the lower resistance.

5.4.4. Analog switches

To implement the proposed wireless power transceiver, two analog switches are

required. One switch is the connection between magnetic resonator and impedance

matching network of wireless power receiver in wireless power receiver mode or

class-E power amplifier in wireless power transmitter mode. The other one switch is

the connection between battery and bi-directional DC-DC converter when the

proposed wireless power transceiver operates wireless power transmitter. In receiver

mode, the switch is turned-off to proper connection from the bi-directional DC-DC

converter to the battery. On the contrary, the switch is turned-on to disable the

battery charger operation and supply the power from the battery to bi-directional

DC-DC converter when the wireless power receiver operates transmitter mode.

5.4.5. Battery charger

Generally, the battery charger is used to regulate the charging current of the

battery. If the battery charger is switch charger type, the DC-DC converter may not

be required. Also, the overall power conversion efficiency can be improved due to
76
 Power Transistor

PMOS VIN_HIGHER &

NMOS
Driver VOUT Selection
Driver

Controller

LDO BGR Protection

Fig. 5.9. Chip microphotograph.

the absence of the DC-DC converter. However, recently portable device has already

battery charger inside the smart phone or tablet PC. Therefore, the battery charger is

not considered and DC-DC converter provides the regulated voltage to the battery

charger in this thesis.

77
 [%] Efficiency curve
100

95

90

85

80

75

70
1.0 2.0 3.0 4.0 5.0 6.0
POUT [W]

(a)

[%] Efficiency curve

100

95

90

85

80

75

70
1.0 2.0 3.0 4.0 5.0 6.0
POUT [W]

(b)

Fig. 5.10. Power conversion efficiency when the bi-directional DC-DC converter

operates in (a) buck and (b) boost converter.

78
 (a)

(b)

Fig. 5.11. Wireless power transceiver in (a) the receiver mode and (b) the tr

ansmitter mode.

79
 Fig. 5.12. Printed circuit board of the proposed wireless power transceiver.

5.5. Measurement results

The proposed wireless power transceiver has been implemented in a 0.35-μm

2P4M BCDMOS technology. Fig. 5.9 shows the microphotograph of the bi-

directional DC-DC converter whose area is 9.4-mm2. The other building blocks of

the proposed wireless power transceiver have been implemented separately. The

inductor and capacitor of the DC-DC converter are 4.7-µH with equivalent series

resistance (ESR) of 100-mΩ and 10-µF with ESR of 50-mΩ, respectively. The

resonant frequency of the magnetic resonator is 6.78-MHz. The input range of the

proposed bi-directional DC-DC converter is from 5.5-V to 12.0-V in the receiver

mode and from 2.6-V to 4.0-V in the transmitter mode. The switching frequency of

the DC-DC converter is 0.5-MHz. And the output voltage is 5.0-V in both receiver

and transmitter mode. The output voltage can varies by the controlling the external

resistor RF_OPT for various applications such as digital camera or smart watch devices.

80
 TABLE 5.2.

PERFORMANCE SUMMARY OF THE PROPOSED WIRELESS POWER TRANSCEIVER

Technology 0.35-µm BCDMOS 2P4M

Resonant frequency 6.78-MHz
Silicon area 5-mm  2.5-mm
5.5 ~ 12.0-V @ receiver mode
Input voltage
2.6 ~ 4.0-V @ transmitter mode
Filtering capacitor 10-µF with ESR of 50-mΩ
Inductor / ESR 4.7-µH / 100-mΩ
Switching frequency 0.5-MHz
Output voltage 5.0-V @ both mode
91-% @ receiver mode, POUT=3.0-W
Power efficiency
90-% @ transmitter mode, POUT=3.0-W
81.7-% @ receiver mode, POUT=2.5-W
Overall transceiver efficiency
76.5-% @ transmitter mode, POUT=3.0-W

Fig. 5.10 shows the power conversion efficiency when the bi-directional DC-DC

converter operates in (a) buck and (b) boost converter. The peak efficiencies in the

receiver mode and the transmitter mode are 91-% and 90-%, respectively. With the

set-up in Fig. 5.11, the peak overall efficiency of the wireless power transceiver is

measured to be 81.7-% in the receiver mode when 2.5-W is delivered to the battery

while it is 76.5-% in the transmitter mode when 3.0-W is delivered to the magnetic

resonator. After the measurement, the implemented IC is packaged with the QFN

package. Due to the limitation of the sample package, the size of the package is 10-

mm  10-mm with 44-PIN. Fig. 5.12 shows the printed circuit board of the

proposed wireless power transceiver with the packaging of the proposed bi-

directional DC-DC converter. The performance of the wireless power transceiver is

summarized in Table 5.2.

81
 6. Proposed Wireless Power Charger for Wearable

Medical Devices with In-Band Communication

6.1. Motivation of the wireless power charger

The power consumption of wearable medical devices such as hearing aid,

artificial pacemaker, and glucose monitor has to be minimized to allow their

operation without charging or changing battery as long as possible [3]-[11]. If the

battery of a wearable medical device can be charged wirelessly, the user

convenience can be further improved. In [4] and [5], a wirelessly powered smart

contact lens was presented which can continuously monitor and transmit the glucose

level. The power efficiency of the AC-to-DC converter, however, is not high because

of the voltage drop of the two diode-connected transistors. For better power

efficiency of the AC-to-DC conversion in a wearable medical device, a self-driven

rectifier was proposed [9], [10]. When the voltage swing of the AC input is larger

than twice the threshold voltage of the transistors of the self-driven rectifier, reverse

current can degrade the power efficiency. To avoid this, multiple self-driven

rectifiers has to be cascaded, which can degrade the power efficiency as well.

Another requirement for a wearable medical device is the capability of

exchanging information with an external host [12]. If the medical device monitors

any bio-signal, the monitored bio-signal has to be transmitted to the external host for

a patient or doctor to be informed of it. The status of the battery of a wearable

medical device has to be shared with the power transmitter to maximize the battery

82
life as well [13]. Because the size of a wearable medical device is very critical, it is

desired to transmit any information via the same channel as the one used for the

wireless power transmission, which is known as the in-band communication.

This paper presents a wireless power charger integrated circuit (IC) for a wearable

medical device. The battery of a wearable medical device is charged wirelessly by

placing it on or near a charging pad. In order to notify the charging pad of a proper

connection with a wearable medical device and the battery status, an in-band

communication circuit has been integrated on the wireless power charger IC as well.

In following chapter, the operation of the wireless charger IC for a wearable medical

device is explained in detail and the experimental results are provided.

6.2. Proposed wireless power charger IC for a wearable medical

devices

For a wearable medical device, a lithium-ion (Li-ion) battery is widely used

because of its high energy capacity and low self-discharge rate [47]. However, there

is a possibility of explosion for a Li-ion battery when it is over-discharged [48].

Because the safety is the most important factor for a wearable medical device, the

much safer nickel-metal-hydride (NiMH) battery has been investigated by many

researchers [49]-[51]. The wireless power charger IC of this work is assuming the

wearable medical device is employing a NiMH battery as well.

83
 Fig. 6.1. Wireless power charger IC for a wearable medical device.
This work
Rectifier Linear Charger
VBH
MPB1 MPB2 ICHG
VOREC VOC VBAT VMODE
ADC MCU
ICOPY RC VEND
MP1
RS VGATE
DS1 DS2
VOS NiMH
VINA
battery
EA1

84
Power Amplifier OIVP MP2
VINB CR MP3 RB
VSEN
VEND
VREF MN1
MNR1 MNR2 RSET
In-Band EA2
VMODE
Communication
In-Band Protection
BGR & LDO
Communication (OOVP, OCP, TSD)
 Fig. 6.1 shows the architecture of the system where a wearable medical device

can be charged wirelessly and exchange information by the in-band communication.

The power amplifier (PA) on the charging pad delivers AC power to the magnetic

resonator whose resonant frequency is 6.78-MHz which is the industrial, scientific,

and medical (ISM) band. The wireless power charger IC consists of a passive

rectifier, a linear battery charger, and an in-band communication circuit. The

operation of each building block ix explained below.

6.3. Circuit design of the proposed wireless power charger IC

In this chapter, sub-circuit design of the proposed wireless power charger IC for a

wearable medical device is described in detail.

6.3.1. Rectifier

For the AC-to-DC conversion, a passive full-wave rectifier consisting of Schottky

diodes and cross-coupled nMOS transistors is used which can prevent reverse

leakage current in any environment. If an active full-wave rectifier is used, the

resistive power loss due to the voltage-drop of Schottky diodes can be decreased an

high power efficiency may be expected [52]. For the resonant frequency of 6.78-

MHz, however, the driving power loss of an active rectifier is dominant and

therefore the passive rectifier used in this work can offer high power efficiency. The

output VOREC of the rectifier is applied to the linear battery charger.

6.3.2. Battery charger

85
 Although higher power efficiency can be achieved with a switching-type battery

charger, this work employs a linear-type battery charger in order to minimize the

form factor of the wearable device and avoid any undesired switching noise at the

harmonics of the switching frequency [53].

The charging profile of a NiMH battery is different from that of a Li-ion battery

and consists of the pre-charge mode, the fast charge mode, and the charge

termination mode [54], [55]. When a NiMH battery is completely discharged and the

output voltage of the NiMH battery is lower than a pre-defined voltage level, a small

charging current flows to the battery, which is the pre-charge mode. If the voltage

level of the NiMH battery exceeds the pre-defined level, the fast charge mode begins

during which a constant current ICHG charges the battery and the voltage level of a

NiMH battery increases. When a NiMH battery is fully charged, its voltage level

decreases slightly [54].

The charging profile is controlled by an off-chip analog-to-digital converter (ADC)

and micro-controller unit (MCU). The voltage level of the NiMH battery is digitized

by the ADC and the digitized voltage level is monitored by the MCU to determine

the operation mode of the linear battery charger. If the voltage level of the NiMH

battery is smaller than 0.9-V, the MCU lets the linear battery charger to operate in

the pre-charge mode by setting the charging current ICHG to be small. When the

voltage level of the NiMH battery becomes larger than 0.9-V, the linear charger

enters the fast charge mode by increasing the charging current ICHG. The magnitude

of the charging current ICHG is determined by the resistance of the resistor RSET as

explained below.

86
 MEP3 MEP4

ΦCLK

VINN MEP1 MEP2

VB4
VO

VINP MEN2 MEN3 VB3

MEN6 MEN7
ΦCLK
ΦCLK
MEN1
VB2
MEN4 MEN5

Fig. 6.2. Operational amplifier (EA1) of the linear battery charger.

The voltage level of the node VOS tracks that of the node VOC by the error

amplifier EA1 and the pMOS transistor MP2. Because the voltages across the resistors

RS and RC are same, the charging current ICHG is copied as ICOPY with the ratio

ICHG/ICOPY=N where N=RS/RC. The copied current ICOPY then flows through the

resistor RSET and the current sensing voltage VSEN is generated. The sensing voltage

VSEN is compared with the reference voltage VREF by the error amplifier EA2 to

generate the gate voltage VGATE for the transistor MP1. Then, the charging current

ICHG is regulated as;

VREF RS
I CHG   . (6.1)
RSET RC

For the accurate control of the charging current, the input offset voltage of the

87
operational amplifier EA1 is compensated with the chopping technique as shown in

Fig. 6.2 [56].

When the NiMH battery is fully charged, the MCU sets the voltage VEND to be

HIGH and the pMOS power transistor MP1 is turned off to prevent the over-charging

of the battery.

To avoid the reverse leakage current, the body of the pMOS power transistor MP1

is tied to VBH which automatically tracks the higher voltage level between VOC and

VBAT by the transistors MPB1 and MPB2 [57].

VINA

Power Amplifier
VINB
ΦCLK1 Clock
generator A
VEND (0.83-Hz)
3bit
In-Band VDRV Counter
Driver
Communication Clock
ΦCLK2
generator B
(100-kHz)

Fig. 6.3. In-band communication circuit.

Proper connection Fully charged

200kbps

1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
VDRV

1.2s

LOW HIGH
VEND

Fig. 6.4. Timing diagram of the in-band communication.

88
 M PR3
M PR1 M PR5
IC
M PR4
MPR2 MPR6 VH
Φ CLK
EA 3
VR ΦCLK
M PR7
M NR1 VRA MP

MNR6 C
R

RR1 MNR3 M NR5 VL

IDIS
MNR2 M NR4

Fig. 6.5. Clock and ramp generator.

6.3.3. In-band communication circuit

Fig. 6.3 shows the in-band communication circuit. The proper connection of the

wireless battery charger IC with the charging pad is notified by sending the burst

pattern of “101010100….” at 200-kbps in very 1.2-sec period as shown in Fig. 6.4.

If the battery is fully charged, the continuous pulses “101010101….” at 200-kbps

are sent to the charging pad to stop the power transmission. For this, the clock

generators A and B provides 0.83-Hz and 100-kHz clocks, respectively.

The clock generator shown in Fig. 6.5 has a similar structure to the one described

in [44]. The voltage-to-current converter consisting of the operational amplifier EA3,

the transistor MNR1, and the resistor RR1 generates the reference current VR/RR1. Then

the charging current IC is given as;

VR W / L MPR 5
IC   . (6.2)
RR1 W / L MPR1

89
When the clock signal ΦCLK is LOW, the capacitor CR is charged up by IC and the

ramp signal VRAMP rises with the slope IC/CR. When the ramp signal VRAMP becomes

higher than the reference level VH of the upper comparator, the clock signal ΦCLK

becomes HIGH and the transistor MNR6 is turned on to discharge the capacitor CR.

Now, the ramp signal VRAMP falls and when it becomes lower than the reference level

VL of the low comparator, the clock signal ΦCLK becomes LOW again. In this way,

the ramp signal VRAMP and the clock signal ΦCLK are generated.

The driver of the in-band communication circuit drives the nMOS transistors

MND1 and MND2 which are connected to the input of the wireless power charger and

have the ON-resistance of 2-Ω.

6.3.4. Band-gap reference and low-drop-out regulator

The band-gap reference (BGR) shown in Fig. 6.6 generates the bias voltage

MPB5
MPB4
MPB6 MPB3
MPB7 MPB8
RB5 VBGR

MNB1 MNB2

MNB6
RB1
VBGR
MNB5 MNB4 MNB3 RB2 RB3 RB4
Q1 Q2

Fig. 6.6. Band-gap reference circuit.

90
 MPL3 MPL4

MPL5
VDD
RL1 CL1

VBGR VFB
MPL1 MPL2
RL2

MNL3 MNL1 MNL2 MNL4 RL3

Fig. 6.7. Low-drop-out regulator.

required for the operation of the wireless power charger [58]. The linear low-drop-

out (LDO) regulator shown in Fig. 6.7 provides 1.8-V supply to the circuits of the

wireless power charger IC to prevent the gate oxide breakdown when the input

voltage level is higher than the tolerable voltage level. The capacitor CL1 and the

resistor RL1 are used to compensate the loop stability of the LDO regulator.

6.3.5. Protection circuit

In order to protect the wireless power charger IC, over-input voltage protection

(OIVP), over-output voltage protection (OOVP), over-current protection (OCP), and

temperature shut-down (TSD) circuits are employed. The operations of the OOVP,

OCP, and TSD circuits are the same as the conventional ones [38]-[40] while the

operation of the OIVP is explained below.

At the very start of the wireless power transmission and/or the transition from the

charging of multiple devices to the charging of single device, the received AC

91
 VOREC

RD1

Linear Charger
VREF

Rectifier
MP4
VVP
VDUM

RD2 RDUM

Fig. 6.8. Over-input voltage protection (OIVP) circuit.

voltage level and therefore the rectified voltage level VOREC may be higher than the

gate oxide breakdown voltage of the transistors. To protect the transistors from the

gate oxide breakdown, the dummy resistor RDUM of the OIVP shown in Fig. 6.8

dissipates the received power until the rectified voltage VOREC becomes lower than

the predefined voltage level. If the resistor divided voltage VVP of the rectified

voltage VOREC is higher than the reference voltage VREF, the comparator CP1 turns on

the pMOS transistor MP4, which decreases the rectified voltage VOREC and prevents

the gate oxide breakdown. In order to prevent any oscillatory operation of the OIVP,

the comparator has a non-zero hysteretic window.

6.4. Measurement results

The wireless power charger IC has been implemented in 0.18-µm BCDMOS

process and occupies 1.44-mm2. Fig. 6.9 shows the microphotograph of the

implemented wireless power charger IC. The filtering capacitor CR of the full-wave
92
 Rectifier

Battery charger

UVLO & BGR Inband

LDO Protection Comm.

Fig. 6.9. Chip microphotograph.

rectifier is 10-µF with equivalent series resistance (ESR) of 50-mΩ. The

rechargeable NiMH battery has the capacity of 74-mAh. With the set-up in Fig. 6.10,

the power efficiency of the wireless power charger IC is measured to be 31.7-%

when the charging current ICHG during the fast charge mode is 26.6-mA. The overall

power efficiency from the charging pad to the battery including the magnetic

resonant channel is 13.1-%.

Fig. 6.11 shows the measured waveforms of the in-band communication. For an

appropriate connection of the charging pad with the wireless power charger IC, the

burst pattern of “101010100….” is sent as shown in the figure. The modulated data

can be recovered by detecting the envelop of the signal.

The performance of the wireless power charger IC is summarized in Table 6.1.

93
 Charging current Charging pad
Wearable
Wireless
medical
power
device
charger IC
Battery
voltage

Fig. 6.10. Measurement set-up of the wireless power charger IC.

At wireless power charger side

At charging pad side

Fig. 6.11. Measured waveforms of the in-band communication for the proper

connection of wireless power charger and charging pad.

94
 TABLE 6.1.

PERFORMANCE SUMMARY OF THE PROPOSED WIRELESS POWER CHARGER

Technology 0.18-µm BCDMOS 2P4M

Silicon area 1.44-mm2
Resonant frequency 6.78-MHz
Input voltage 1.2 ~ 3.5-VAC,rms
Output voltage 0 ~ 1.8-V
Charging current 0 ~ 50-mA
Filtering capacitor 10-μF with ESR of 50-mΩ
Communication Four pulse (200-kbps) bursts in 1.2-sec period @ proper connection
strategy Consecutive pulses (200-kbps) @ fully charged
Power efficiency 31.7-% @ ICHG=26.6-mA
Overall power
13.1-% @ ICHG=26.6-mA
conversion efficiency

95
 7. CONCLUSIONS

In first research for the wireless power receiver for mobile devices, resonant

magnetic coupling is utilized to transfer 3.0-W power wirelessly. The received AC

power is rectified by a proposed active rectifier and then converted to the desired

DC level by a proposed switching DC-DC converter. The reverse leakage current of

the active rectifier is prevented by a DLL based delay compensation circuit. Also, a

simple technique improving the power efficiency of the switching DC-DC converter

at light-load condition is proposed. The switching frequency is automatically

selected among a pre-defined set of frequencies according to the load current

without any costly current sensing circuit. The wireless power receiver consisting of

the active rectifier and switching DC-DC converter has been implemented in a 0.35-

μm 2P4M BCDMOS technology in two chips, one for the active rectifier and the

other for the DC-DC buck converter each of which occupies 9.7-mm2 and 8.6-mm2,

respectively. The DLL-based delay compensation scheme of the active rectifier

improves the power conversion efficiency of the active rectifier by 3.5-% and 8.0-%

when the resonant frequency is 3.23-MHz and 6.78-MHz, respectively. The power

efficiency of the proposed switching DC-DC converter with the automatic load-

adaptive switching frequency selection circuit is improved by 24.0-% when the load

current is 10-mA, input voltage is 12.0-V, and output voltage is 5.0-V. The overall

power efficiency of the wireless power receiver is 75-% and 68-% when the resonant

frequency of the magnetic resonator is 3.23-MHz and 6.78-MHz, respectively at the

output power of 3.0-W.

96
 The wireless power transceiver which enables a mobile device to receive and

transmit power wirelessly has been developed in second research. For example, a

mobile phone can charge a Bluetooth handset, hearing aid, or another mobile phone

wirelessly with its battery as the power source. To decrease the form-factor of the

wireless power transceiver, the proposed bi-directional DC-DC converter has been

developed which can function as either a buck converter or a boost converter.

Because the DC-DC converter can perform a both the buck and boost operation,

only one inductor is required and the form-factor can be greatly decreased. During

the receiver mode of the wireless power transceiver, the bi-directional DC-DC

converter performs the buck operation to supply regulated voltage for battery

charger. During the transmitter mode, the DC-DC converter operates as the boost

converter to make a proper voltage which determines the output power of the power

amplifier. In addition, some techniques are applied to increase the power conversion

efficiency of the other building blocks of the wireless power transceiver. The bi-

directional DC-DC converter has been implemented in a 0.35-μm 2P4M BCDMOS

technology and silicon area is 9.4-mm2. The maximum power conversion efficiency

of the bi-directional DC-DC converter is 91-% and 90-% in receiver and transmitter

mode, respectively at the output power of 3.0-W. The overall power efficiency of the

wireless power transceiver is 81.7-% in the receiver mode when the delivered power

is 2.5-W. In the transmitter mode, the overall efficiency is 76.5-% when the

transferred power is 3.0-W.

In third research of this thesis, a wireless power charger has been developed for a

wearable medical device. The AC power received from a charging pad is converted

97
to DC power by a passive rectifier whose output is connected to a nickel-metal-

hydride (NiMH) battery through a linear charger. Because the safety is the most

important factor for a wearable medical device, the much safer NiMH than lithium-

ion battery has been adopted. The linear charger allows the small form factor of a

wearable medical device albeit its lower power efficiency than a switching type one.

The connection of the wireless power charger IC with a charging pad and the fully

charged state of the battery are notified by the in-band communication. The wireless

power charger implemented in a 0.18-μm 2P6M BCDMOS process occupies 1.44-

mm2 silicon area and shows 31.7-% efficiency when the battery charging current is

26.6-mA. The overall power efficiency from the charging pad to the battery is 13.1-

%.

98
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103
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directional DC-DC Converter for Wireless Power Transceiver in 0.35-μm
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frequency selection technique for improving the light-load efficiency of a
buck converter,” Analog Integrated Circuits and Signal Processing, vol. 75,
no. 3, pp. 349-358, Jun. 2013.

105
 Publications

- International Journal

[1] Young-Jin Moon, Yong-Seong Roh, Chan-Young Jeong, and Changsik Yoo, “A
4.39–5.26 GHz LC-Tank CMOS Voltage-Controlled Oscillator With Small
VCO-Gain Variation,” IEEE Microwave and Wireless Components Letters, vol.
19, no. 8, pp. 524-526, Aug. 2009.

[2] Young-Jin Moon, Yong-Seong Roh, Jung-Chul Gong, and Changsik Yoo,
“Load-Independent Current Control Technique of a Single-Inductor Multiple-
Output Switching DC-DC converter,” IEEE Transactions on Circuits and
Systems II: Express Briefs, vol. 59, no. 1, pp. 50-54, Jan. 2012.

[3] Young-Jin Moon, Yong-Seong Roh, and Changsik Yoo, “An automatic load-
adaptive switching frequency selection technique for improving the light-load
efficiency of a buck converter,” Analog Integrated Circuits and Signal
Processing, vol. 75, no. 3, pp. 349-358, Jun. 2013.

[4] Young-Jin Moon and Changsik Yoo, “A Switch-Mode Boost DC-DC

Converter for IR-Drop Compensation of Charging Cable,” International
Journal of Circuit Theory and Applications, Online published.

[5] Young-Jin Moon, Jeongpyo Park, Mingyu Jeong, Sang-Hyun Kim, Jin-Gyu
Kang, Dong-Zo Kim, and Changsik Yoo, “Wireless Power Charger for
Wearable Medical Devices with In-Band Communication,” Submitted to IEEE
Transactions on Circuits and Systems II: Express Briefs.

[6] Yong-Seong Roh, Young-Jin Moon, Jung-Chul Gong, and Changsik Yoo,
“Active Power Factor Correction (PFC) Circuit With Resistor-Free Zero-
Current Detection,” IEEE Transactions on Power Electronics, vol. 26, no. 2, pp.
630-637, Feb. 2011.

[7] Ho-Joon Jang, Yong-Seong Roh, Young-Jin Moon, Jeongpyo Park, and

106
 Changsik Yoo, “Low Drop-Out (LDO) Voltage Regulator with Improved Power
Supply Rejection,” Journal of Semiconductor Technology and Science, vol. 12,
no. 3, pp.313-319, Sep. 2012.

[8] Yong-Seong Roh, Young-Jin Moon, Jeongpyo Park, and Changsik Yoo, “A
Two-Phase Interleaved Power Factor Correction Boost Converter With a
Variation-Tolerant Phase Shifting Technique,” IEEE Transactions on Power
Electronics, vol. 29, no 2, pp. 1032-1040, Feb. 2014.

[9] Jeongpyo Park, Yong-Seong Roh, Young-Jin Moon, and Changsik Yoo, “A
CCM/DCM Dual-Mode Synchronous Rectification Controller for a High-
Efficiency Flyback Converter,” IEEE Transactions on Power Electronics, vol.
29, no 2, pp. 768-774, Feb. 2014.

[10] Yong-Seong Roh, Young-Jin Moon, Jeongpyo Park, Min-Gyu Jeong, and
Changsik Yoo, “A Multi-Phase Synchronous Buck Converter with Fully
Integrated Current Balancing Scheme,” IEEE Transactions on Power
Electronics, Online published.

- Domestic Journal

[1] 문영진, 유창식, “양방향으로 동작하는 DC-DC Converter를 이용하는 무

선 젂력 송수싞기 개발,” 대핚젂자공학회 논문지 제 51 권 SD 편 제

7호, pp. 111-121, 7월, 2014년.

[2] 공정철, 노용성, 문영진, 최우석, 유창식, “부궤환 선택회로를 갖는 단

일 인덕터 다중 출력 직류-직류 변환기,” 대핚젂자공학회 논문지 제

48 권 SD 편 제 12호, pp. 23-30, 12월, 2011년.

107
 - International Conference

[1] Young-Jin Moon, Yong-Seong Roh, Jeongpyo Park, and Changsik Yoo, “EMI
Reduced DC-DC Switching Buck Converter with Sigma-Delta Modulation,” in
Proc. International Technical Conference on Circuits/Systems, Computers and
Communications, Jul. 2012.

[2] Young-Jin Moon, Yong-Seong Roh, Changsik Yoo, and Dong-Zo Kim, “A 3.0-
W wireless power receiver circuit with 75-% overall efficiency,” in Proc. IEEE
Asian Solid State Circuits Conference, pp. 97-100, Nov. 2012.

[3] Young-Jin Moon, Dong-Zo Kim, Sang-Wook Kwon, Yong-Seong Roh, and
Changsik Yoo, “A 6.0-W bi-directional DC-DC converter for wireless power
transceiver in 0.35-µm BCDMOS,” in Proc. IEEE Symposium on VLSI Circuits,
pp. 230-231, Jun. 2013.

[4] Dong-Zo Kim, Ki Young Kim, Jinsung Choi, Young-Ho Ryu, Yun-Kwon Park,
Sangwook Kwon, Young-Jin Moon, and Changsik Yoo, “High Efficient Power
Receiver IC with Load Modulator for Wireless Resonant Power Transfer,” in
Proc. European Microwave Conference, pp. 416-419, Oct. 2012.

- Domestic Conference

[1] Yeongjin Moon and Changsik Yoo, “A 5-GHz CMOS VCO with small VCO-
Gain Variation for WLAN Application,” RF Integrated Circuit Technology
Workshop, Jeju, Sep. 2007.

[2] 공정철, 노용성, 문영진, 유창식, “부궤환 선택 회로를 갖는 단일 인덕

터 다중 출력 직류-직류 변환기,” 2010년도 대핚젂자공학회 하계학술

대회, 제 33 권, 제 1호, pp. 533-536, 12월, 2011년.

[3] 박정표, 문영진, 정민규, 강짂규, 김상현, 유창식, “플라이백 배터리 충

108
젂회로의 정젂류 모드 효율 개선을 위핚 동기 정류 컨트롤러,” 2014년

도 SoC 학술대회, 서울, May. 2014.

109
 Patents

- International (Registration)

[1] US 8289091, “Relaxation oscillator”

[2] US 8791677, “Power factor correction circuit for correcting power factor”

- Domestic (Registration)

[1] 1010104510000, “레플리카 부하를 이용핚 저젂압 강하 레귤레이터”

[2] 1010094580000, “부하 조건에 무관핚 단일 인덕터 다 출력 직류-직류

변환 장치 및 그 스위치 제어 방법을 실행시키기 위핚 프로그램을 기

록핚 기록매체”

[3] 1011535740000, “부궤환회로를 이용핚 이완 발짂기”

[4] 1011793270000, “역률 개선 회로”

[5] 1011715970000, “스위칭 방식 젂압 변환기의 인덕터 영 젂류 측정 장

치”

[6] 1020110120270, “젂원장치에 사용되는 IC 회로”

International (Application)

[1] US 20120051109, “ACTIVE RECTIFIER WITH DELAY LOCKED LOOP,

WIRELESS POWER RECEIVING APPARATUS INCLUDING ACTIVE

110
 RECTIFIER”

[2] US 20120087160, “POWER FACTOR CORRECTION CIRCUIT”

[3] US 20120155133, “DIRECT CURRENT/ DIRECT CURRENT CONVERTER

FOR REDUCING SWITCHING LOSS, WIRELESS POWER RECEIVER
INCLUDING DIRECT CURRENT/ DIRECT CURRENT CONVERTER”

[4] US 20130127525, “IC CIRCUIT”

[5] US 20140176089, “PHASE SHIFT CIRCUIT AND POWER FACTOR

CORRECTION CIRCUIT INCLUDING THE SAME”

[6] US 20140015331, “APPARATUS AND METHOD FOR WIRELESS POWER

RECEPTION”

- Domestic (Application)

[1] 1020100083311, “지연 고정 루프를 이용핚 능동형 정류기, 능동형 정류

기를 포함하는 무선젂력 수싞 장치”

[2] 1020100130861, “스위칭 손실을 줄이는 직류-직류 젂압 변환기, 상기

직류-직류 젂압 변환기를 포함하는 무선젂력 수싞 장치”

[3] 1020120151303, “위상 변환 회로 및 그를 포함하는 역률 보상 회로”

[4] 1020120151304, “위상 변환 회로 및 그를 포함하는 역률 보상 회로”

[5] 1020120157073, “역률 개선 회로”

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 초록

한양대학교 대학원

전자컴퓨터통신공학과

문 영 진

이 논문은 모바일 및 착용 가능핚 의료 기기의 무선 젂력 젂송을 위핚

무선 충젂 수싞기, 무선 충젂 송수싞기, 무선 충젂기를 각각 설명하고

있다. 지연 고정 루프를 기반으로 핚 보상 회로를 이용하여 모바일

기기를 위핚 무선 충젂 수싞기의 능동형 정류기의 역방향 누설 젂류를

방지하였다. 무선 충젂 수싞기의 강압 컨버터는 작은 출력 젂류 상황에서

비연속 도통 모드로 동작하며 효율을 향상시키기 위하여 스위칭 주파수가

출력 젂류에 따라 미리 정해짂 주파수 중의 하나로 선택된다. 또핚,

모바일 기기가 무선으로 젂력을 받을 수 있을 뿐 아니라 젂달 해 줄 수

있는 무선 충젂 송수싞기를 위핚 양방향으로 동작하는 직류-직류 젂압

변환기를 개발하였다. 제안된 양방향으로 동작하는 직류-직류 젂압

변환기를 적용하여 무선 젂력 송수싞기의 form-factor를 줄였다. 그리고

착용 가능핚 의료기기의 배터리를 충젂하기 위핚 무선 젂력 충젂기를

개발하였다. 배터리의 상태는 in-band 통싞 회로에 의해 송싞기로 젂달

된다.

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 To my family,

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