Cascaded Counters

ECE 238L 16 © 2006

Page 1
 A Mod4 Counter
(A 2-bit counter)
CLR INC Q1 Q0 N1 N0 CLR’ • INC’
CLR
0 0 0 0 0 0
0 0 0 1 0 1
0 0 1 0 1 0 00
0 0 1 1 1 1 CLR’ • INC
CLR’ •INC
0 1 0 0 0 1
CLR’ • INC’
0 1 0 1 1 0 CLR’ • INC’
0 1 1 0 1 1
0 1 1 1 0 0 11 01
1 - - - 0 0

CLR’ • INC CLR’ • INC

10

CLR’ • INC’

ECE 238L 16 © 2006

Page 2
 A Mod4 Counter With a Rollover Signal

CLR INC Q1 Q0 N1 N0 Rollover CLR’ • INC’

Mealy output CLR
0 0 0 0 0 0 0
0 0 0 1 0 1 0
0 0 1 0 1 0 0 00
0 0 1 1 1 1 0 CLR’ • INC/Rollover
CLR’ • INC
0 1 0 0 0 1 0
CLR’ • INC’
0 1 0 1 1 0 0 CLR’ • INC’
0 1 1 0 1 1 0
0 1 1 1 0 0 1 11 01
1 - - - 0 0 0

CLR’ • INC CLR’ • INC

Signal Rollover can be used to tell 10

other circuitry that counter is
rolling over to all 0’s
CLR’ • INC’

ECE 238L 16 © 2006

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 Cascading 2 Mod4 Counters
Digit1 Digit0

00 Increment higher
01 Count sequence digit’s counter
02 when lower digit’s
03 counter is rolling
10 over
11
12
13
Digit1 Digit0
20
21 clk clk
2 2
22
23 CLR CLR
30 Mod4 Mod4
Rollover1 Rollover0 INC
31 Counter Counter
32
33
00

ECE 238L 16 © 2006

Page 4
 3 Digits’ Worth
Increment higher
digit’s counter
when lower digit’s Can do this with any
counter is rolling counter that has
Could build a digital watch over a Rollover output
or clock circuit this way with
Mod60 and Mod24 counters
Digit2 Digit1 Digit0

clk clk clk

2 2 2

CLR CLR CLR

Mod4 Mod4 Mod4 INC
Rollover2 Rollover1 Rollover0
Counter Counter Counter

ECE 238L 16 © 2006

Page 5
 Cascading Counters

• A counter will increment only when

– The counter below it is at its terminal count
and it is being incremented
• That is the definition of the Rollover signal

• Some people try to tie Rollover to the clk

input of the next higher counter
– Bad idea… Very bad idea…
– Violates our Globally Synchronous policy
– Doesn’t work as intended

ECE 238L 16 © 2006

Page 6
Sequence should be: Digit1 Digit0
…-12-13-20-21-22-23-30-… clk1 2 clk
2
but we get:
CLR CLR
…-12-23-20-21-22-33-30-…
Mod4 Mod4 INC=‘1’
‘1’
????? Counter Counter
Rollover1 Rollover0
DO NOT TIE CLK
inputs on modules
to anything but the
clock !!!!!! clk
Even if you tinker until
you get the right count Digit1 1 2
sequence, you must
guarantee that signal
Rollover0 has no hazards Digit0 2 3 0 1 2
Digit0 transition from 1-2
makes this difficult if
not impossible Clk1
(Rollover0)

ECE 238L 16 © 2006

Page 7
Sequence should be: Digit1 Digit0
…-12-13-20-21-22-23-30-… clk1 2 clk
2
but we get:
…-12-23-20-21-22-33-30-… CLR CLR
Mod4 Mod4 INC=‘1’
????? Counter ‘1’ Counter
Rollover1 Rollover0
DO NOT TIE CLK
inputs on modules
to anything but the
clock !!!!!! clk
Even if you tinker until
you get the right count Digit1 1 2
sequence, you must
guarantee that signal
Rollover0 has no hazards Digit0 2 3 0 1 2
Digit0 transition from 1-2
makes this difficult if
not impossible Clk1
(Rollover0)

Possible hazard
ECE 238L 16 © 2006
Page 8
 Ripple Counters

• When you tie a rollover-like signal to a clock

on the next higher digit Ù ripple counter
• A ripple counter is an ASYNCHRONOUS
counter
– Transitions are not all synchronized to the clock
– Different flip flops change at different times
– Similar to gated clocks (seen earlier)
• Asynchronous circuits are an advanced topic

ECE 238L 16 © 2006

Page 9
 Another Common Ripple Counter
Sequence is:

0000
Q3 Q2 Q1 Q0
0001
0010
0011
0100 ‘1’ ‘1’ ‘1’ ‘1’
0101 T Q T Q T Q T Q
0110 Q’ Q’ Q’ Q’
0111
1000
CLK
1001
1010
1011
1100
1101
1110
1111
0000

So what is the problem?

ECE 238L 16 © 2006

Page 10
 Timing Diagram

clk Q0 changes in response to clock edge

Only after it changes does Q1’s FF get a clock

Q0
Only after that does Q2’s FF get a clock

Q1
Net effect is that all the FF’s change at
different times
Q2
Logic depending on Q3 has very little time
to react before next clock edge
Q3

ECE 238L 16 © 2006

Page 11
 Do Not Use Asynchronous or Ripple
Counters
Digit1 Digit0

clk1

2
clk
2
CLR CLR

INC=‘1’
Mod4 Mod4
Counter Counter
‘1’

Rollover1 Rollover0

Q3 Q2 Q1 Q0

‘1’ T Q ‘1’ T Q ‘1’ T Q ‘1’ T Q

Q’ Q’ Q’ Q’

CLK

ECE 238L 16 © 2006

Page 12
 Mod4 Counter

(CEin Reset’)/CEout
00 CEin Reset’

Reset

Reset
Reset
11 01

CEin Reset’ CEin Reset’

10

ECE 238L 16 © 2006

Page 13
 The State Flip- Flop

Note: Both CLK and CE are required

to change the flip-flop

ECE 238L 16 © 2006

Page 14
 Mod4 Counter
Q1Q0 N1
CEin Q1 Q0 N1 N0 CEout Ce 00 01 11 10

0 0 0 0 0 0 0 1 1

0 0 1 0 1 0 1 1 1

0 1 0 1 0 0
0 1 1 1 1 0
N1 = Ce’Q1 + Q1Q0’ + CeQ1’Q0
1 0 0 0 1 0
1 0 1 1 0 0
1 1 0 1 1 0
1 1 1 0 0 1 Q1Q0 N0
Ce 00 01 11 10

0 1 1
Note: No change when CEin=0 1 1 1

CEout = CeQ1Q0 N0 = Ce’Q0 + CeQ0’

ECE 238L 16 © 2006

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Mod4 Counter

ECE 238L 16 © 2006

Page 16
 Cascaded Ripple Counter

Stage 2
increments
is too
early

CLKin
Reset
Dout
CEout
Next Counter

ECE 238L 16 © 2006

Page 17
 Cascaded Ripple Counter

Why is Next Stage increment too early?

Stage 1 10 11

master loads
CEout slave loads
CEout from Stage 1 is used as the clock
for Stage 2

Stage 2 00 01

ECE 238L 16 © 2006

Page 18
 Cascaded Ripple Counter

A Ripple Counter is an ASYNCHRONOUS counter

since it’s transitions are NOT synchronized to the

system clock.

In a SYNCHRONOUS counter, all stages transition

with the system clock

ECE 238L 16 © 2006

Page 19
 Cascaded Synchronous Counter

Stage 2 is
incremented
at the correct
time

CLKin
Reset
Dout
CEout
Next Counter

ECE 238L 16 © 2006

Page 20
 Cascaded Synchronous Counter

System
master loads slave loads master loads slave loads
Clock

Stage 1 10 11 00

CEout

Stage 2 master loads

Stage 2 slave loads

Stage 2 00 01

ECE 238L 16 © 2006

Page 21
 Cascaded Counters

The more stages you add to the counter, the bigger

the discrepancy between Synchronous and Asynchronous
counters

Stage 1

S
Stage 2
A
S
Stage 3
A

ECE 238L 16 © 2006

Page 22
 Cascaded Synchronous Counter

CEin controls when the S.M. can change

Clk Clk Clk

‘1’ CEin CEin CEin

Count Count Count

CEin CEin CEin

CEin also controls when the CEout will be generated

ECE 238L 16 © 2006

Page 23
 Cascaded Synchronous Counter
Note that the CEout from each stage is synchronized with the
system clock and with each other. The stage transitions are all
synchronized with the system clock

CEout 1

CEout 2

Color Code: Clock

Stage 1
Stage 2
Stage 3

ECE 238L 16 © 2006

Page 24
Cascaded Synchronous Counter

Lesson : Always use SYNCHRONOUS

counters and timers.

ECE 238L 16 © 2006

Page 25
 A Mod4 Counter
CLR INC Q1 Q0 N1 N0 RO
0 0 0 0 0 0 0
Count
0 0 0 1 0 1 0 Value
0 0 1 0 1 0 0
D Q
0 0 1 1 1 1 0 Clr Terminal
0 1 0 0 0 1 0 Count
0 1 0 1 1 0 0
0 1 1 0 1 1 0 IFL
0 1 1 1 0 0 1
1 - - - 0 0 0
D Q

Inc

ECE 238L 16 © 2006

Page 26
 A Mod4 Counter
CLR INC Q1 Q0 N1 N0 RO
0 0 0 0 0 0 0
Count
0 0 0 1 0 1 0 Value
0 0 1 0 1 0 0
D Q
0 0 1 1 1 1 0 Clr Terminal
0 1 0 0 0 1 0 Count
0 1 0 1 1 0 0
0 1 1 0 1 1 0 IFL
0 1 1 1 0 0 1
1 - - - 0 0 0
D Q

Inc
Roll
Over
You wouldn’t really build it like this!

ECE 238L 16 © 2006

Page 27
 Cascaded Counters
Clk
Clr

Clk Clk Clk

Clr CV Clr CV Clr CV

MOD4 TC MOD4 TC MOD4 TC

Inc Inc Inc

Inc

ECE 238L 16 © 2006

Page 28
 Cascaded Counters
Clk
Clr

Clk Clk Clk

Clr CV Clr CV Clr CV

MOD4 TC MOD4 TC MOD4 TC

Inc Inc Inc

Inc

Assume that the second timer is already at the terminal count

ECE 238L 16 © 2006

Page 29
 Cascaded Counters
Clk
Clr

Clk Clk Clk

Clr CV Clr CV Clr CV

MOD4 TC MOD4 TC MOD4 TC

Inc Inc Inc

Inc

ECE 238L 16 © 2006

Page 30
 Cascaded Counters
Clk
Clr

Clk Clk Clk

Clr CV Clr CV Clr CV

MOD4 TC MOD4 TC MOD4 TC

Inc Inc Inc

Inc

ECE 238L 16 © 2006

Page 31
 Cascaded Counters
Clk
Clr

Clk Clk Clk

Clr CV Clr CV Clr CV

MOD4 TC MOD4 TC MOD4 TC

Inc Inc Inc

Inc

ECE 238L 16 © 2006

Page 32
 Cascaded Counters
Clk
Clr

Clk Clk Clk

Clr CV Clr CV Clr CV

MOD4 TC MOD4 TC MOD4 TC

Inc Inc Inc

Inc

ECE 238L 16 © 2006

Page 33
 Cascaded Counters
Clk
Clr

Clk Clk Clk

Clr CV Clr CV Clr CV

MOD4 TC MOD4 TC MOD4 TC

Inc Inc Inc

Inc

It looks like the Inc signal will ripple from counter to counter.
Why is this any different from the toggle flip-flop example?

ECE 238L 16 © 2006

Page 34
 A Mod4 Counter
The right way!

Count
Value
Clr D Q
Terminal
Count
IFL

D Q

Inc Roll
Over

ECE 238L 16 © 2006

Page 35
A Mod4 Counter

Clear

Count
Value
Increment

MOD4
Roll
Over
Clock

ECE 238L 16 © 2006

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