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Asynchronous and Synchronous Counter
Asynchronous and Synchronous Counter
Asynchronous and Synchronous Counter
(DIGITAL SYSTEMS)
LABORATORY SESSION 4
Prepared by:
Prepared for:
THEORY :
PROCEDURE :
A. Asynchronous Counter
1) The JK flip-flops of 3-bit asynchronous counter was connected. The
counter has Q0, Q1, and Q2 as the output (Q0 is LSB and Q2 is
MSB).
2) The CLR (Reset) and PR (Set) was connected to +5v.
3) Function Generator output point is connected to the clock for the
first flip-flops.
4) Settings of Function generator will be like the followings:
I. Output Amplitude Adjuster was set to maximum.
II. Fine Tune Output are set to 1Hz.
III. Then, the Output Waveform has been selected to square
wave.
5) Then, 2 digits has been setting like the following:
I. D knew as MSB while A is LSB.
II. Pin A, B and C is connected to Q0, Q1 and Q2 respectively.
III. The other pin that not being used are grounded.
IV. The DIP switch is turned ON for LDL-800 Digital Lab Unit.
6) After completed the circuit, the power supply is turned ON.
7) The seven segment display was observed and reported it in result.
8) Schematic diagram of 3-bit asynchronous using JK flip-flops and
external connection of 7476 chips was draw in Result.
B. Synchronous Counter
1) The JK flip-flops is connected to have 2-bit synchronous counter.
The counter has Q0 and Q1 as the output (Q0 is LSB and Q1 is
MSB).
2) The procedure was repeated from A2-A4.
3) For procedure 5, Q0 and Q1 is connected to pin A and B
respectively and was grounded the others that not in use.
4) The procedure from A6-A8 is repeated.
RESULT :
A. Asynchronous Counter
Synchronous Counter
DISCUSSION :
REFERENCES :
http://verticalhorizons.in/synchronous-and-asynchronous-counters-in-digital-
electronics/
https://www.allaboutcircuits.com/textbook/digital/chpt-11/synchronous-counters/
https://www.quora.com/What-is-an-asynchronous-counter