Vineel Jessy Talluri

Believe in Smart Work

Objective
To create value and recognition on work place by producing best results through
hard work,smart work and people skills.

Areas of Interest
{ RTL Design and Verification { Physical Design
{ Static Timing Analysis { Analog/Digital circuit design
{ Semiconductor Device Modeling { Layout design

Education and Training

2019 ASIC Front-End Training, Maven Silicon, Bangalore.
Course: RTL Design and Verification.
Training Period: 2019 (March-July).

2016-18 M.TECH, NIT GOA, Goa.

Branch: VLSI (Electronics and Communication)
Marks: 7.25 CGPA

2011-15 B.TECH, Koneru Lakshmaiah University, Guntur (A.P.).

Department: Electronics and Communication
Marks: 6.38 CGPA

2009-2011 INTERMEDIATE, Sri Chaitanya Junior College, Vijayawada (A.P.).

Board of Intermediate Education
Percentage: 86.6%

2009 HIGH SCHOOL, Royal High School, Martur (A.P.).

Board of Secondary Education
Percentage: 85.5%

Maven Silicon – Gottigere, Bangalore (560076) – India

H +91 8897209797 • B vineeltalluri@gmail.com
Linkedin:linkedin.com/in/vineel-talluri-4a600181
Industry Exposure and Work Experience
{ Teaching assistant under Dr.Prashanth.G.R for Micro-processors and Micro-
Controllers subject and conducted labs for B.Tech 3rd year students and taught
Microprocessor Programming.Teaching assistant under Dr.Trilochan Panigrahi for
Digital Communications subject. The whole teaching experience helped me to
grow in many aspects and improve my management skills.
{ Undergone IMPLANT TRAINING in Labyrinth solutions, Vishakhapatnam on
“Wireless Communications” and Functioning of the equipment’s at Training Centre
from 8th May to 20th June 2013.

Programming Languages
{ Verilog/VHDL
{ System Verilog(SV)
{ Universal Verification Methodology(UVM)
{ UNIX
{ Basics of Perl
{ Basics of C

Technical Tools
{ Xilinx - Gvim,Rivera pro
{ Cadence - ADEL,ADEXL
{ Xilinx ISE - Verilog/VHDL
{ Vivado - Verilog/VHDL
{ Xilinx - Gvim,Rivera pro
{ Matlab - Simulink

Projects
Curriculum Projects
{ Router 1*3 Design.
Language Used: Verilog/VHDL.
EDA Tools: Xilinx ISE 14.7, Aldec Riviera-PRO 2015.
Duration:19th April 2019 to 29th April 2019 (Latest Project)
Summary: Router is a device used for broadcasting and it is a device that forwards
data packets between computer networks.It is an OSI layer3 routing device.It drives
an incoming packet to an output channel based on the address field contained in
the packet header.

Maven Silicon – Gottigere, Bangalore (560076) – India

H +91 8897209797 • B vineeltalluri@gmail.com
Linkedin:linkedin.com/in/vineel-talluri-4a600181
Academic Projects
{ Low Voltage Operational Transconductance Amplifier with Gain and Gain
Bandwidth Enhancement
Technology Used: Cadance, virtuoso.
Duration:27th July 2017 to 8th July 2018 (M.tech Project)
Summary: Low Voltage OTA works at low voltage and low power with full swing
output voltage, and provide high common mode rejection ratio,with supply voltage
of 1-V , power consumption of 0.32mW with DC gain of 52dB,phase margin
around 52◦ and GBW of 140Mhz.

{ Design and Implementation of Pilot OFDM

Technology Used: The Verilog code is written and simulated in XILINX 14.2
and tested using FPGA Spartan-3E board.
Duration:21th Jan to 15th May 2015 (B.tech Final Project)
Summary:The basic principle of OFDM is studied in this PROJECT and modeling
was carried out in MATLAB followed by Verilog HDL implementation. The project
is published in JATIT 2015 vol. 78.

Miniprojects
{ Designed the Layout of Gates such as AND, OR, NAND, NOR, EX-OR, EX-NOR
(Layout Design using Cadence ).
{ Implemented "Traffic Light Controller" using Verilog (Verilog based project using
Cadence software).
{ Design of parallel and pipeline processing using Verilog.(Verilog based project
using Cadence).
{ Designed an "Operational Amplifier"(Analog Circuit Design using Cadence).
{ Participated in a workshop conducted by "SCL Technologies" and implemented
"OP-AMP Layout"(Layout Design using Cadence).
{ Designed and analysed the NMOS and PMOS using Silvaco’s Atlas Soft-
ware.(Device Modeling using Silvaco’s ATLAS).
{ Implemented "Sense Amplifier" Layout in workshop conducted by "Global
Foundries"(Layout Design Using Cadence).
{ Designed 10-bit Pipeline ADC (Mixed-Signal-design using virtuoso cadence).
{ Designed 5-Bit Flash ADC(Mixed-Signal-design using virtuoso cadence).
{ Worked with the project titled "Water Level Alarm Circuit"(Hardware Using Bread
Board).
{ Worked with the project titled "Speech recognition Controller" (Matlab).

Maven Silicon – Gottigere, Bangalore (560076) – India

H +91 8897209797 • B vineeltalluri@gmail.com
Linkedin:linkedin.com/in/vineel-talluri-4a600181
 Achievements
{ Cracked the Gate in first attempt (2016) .
{ Published a Journal paper in JATIT 2015 vol.78 .
{ Participated in Inter NIT Cricket Tournament, 2017.
{ Participated in Paper Presentation Titled Speech Recognition Controller in The
National Level Techno Management festival, SAMYAK’14, K L University.

Linguistic Proficiency
{ English
{ Telugu
{ Hindi

Personal Details
Date of Birth 9th Aug 1994
Fathers’ Mr. T.Pakeeraiah
Name
Mothers’ Mrs. Vijaya Kumari
Name
Permanent 5-53, konanki(post),Martur(Mandal), Prakasam(Dist), A.P. -523260
Address
Present Bellandur,Bengaluru,Karnataka
Address
Nationality India

Declaration
I here by declare that the above information given by me is true to the best of my
knowledge and belief.

Place: Bengaluru,Karnataka
Date: August 2, 2019 Vineel Jessy Talluri

Maven Silicon – Gottigere, Bangalore (560076) – India

H +91 8897209797 • B vineeltalluri@gmail.com
Linkedin:linkedin.com/in/vineel-talluri-4a600181