International Journal of Electrical, Electronics and Computer Systems (IJEECS)

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A Comparative Study Between Different Types of Adders and

Multipliers
1
Nupur Jain, 2Pooja Ganesh
1,2
Department of Electronics and Communication Engineering, R.V. College of Engineering, Bangalore- 560059,
Vishweshwaraya Technological University, Belgaum

comparators, ALU’s, DSP architectures, parity checkers

Abstract: In this paper we have compared the working of
different types of adders and multipliers based on few of
the very crucial parameters which include speed and
power dissipation. Comparison is also made on the basis of
number of transistors and the (PDP) power delay product
values. The circuits are designed at a transistor level using
CMOS 180nm technology
Keywords: CPL logic, DCVSL logic, NORA logic, Pseudo
nMOS, Static CMOS, Wallace tree multipliers, Array
multipliers.
I. INTRODUCTION
The most important feature of modern day electronics is
to build low power high speed devices both due to
increase in integration of components and reduction in
size. Over the decades the battery life has only improved
by a factor of 2 or 4 whereas the power of digital IC’s
has increased with over four orders of magnitude.A low
power design needs to be adopted for future
advancements or else the devices will suffer from a short
battery life or very heavy battery packs. It is also
important to avoid local areas of high power dissipation
which may cause hotspots, and also to reduce the need
for a low power impedance and ground distribution
network which may interfere with signal
interconnections.
The size of transistors, parasitic capacitances and delay
in the critical path are some of the factors that limit the
speed of the design .Speed and power are two
conflicting but very important factors while designing
circuits. Hence we measure performance based on the
values of the Power delay product (PDP).Power
dissipated in circuits depends on three major factors
which include static power due to leakage currents,
switching power due to charging and discharging of
capacitances, short circuit power due to current flow
from power supply to ground with simultaneous
functioning of n and p networks.Power dissipated also
depends on number and size of transistors, wiring
complexity, routing methods, node capacitances.
Addition is a basic core operation used for all other
operations such as multiplication, subtraction, division,
address generation etc. Adders form the basis of many
VLSI systems such as processors, code converters,
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etc. For performance analysis of adders various
parameters are measured such as PDP, number of
transistors, power dissipation etc. The use of full adders
in cascading configuration gives it a poor driving
capability and hence it requires additional buffer which
further increases power consumed. The designs of full
adders have gone through various modifications to
improve speed and reduce the power consumed but at
the cost of poor driving capability and reduced voltage
swing.
II. LOGIC STYLES
CMOS logic styles are categorized into two major parts
namely Static CMOS and Dynamic CMOS. It is well
known for theoretical reasons that static logic retains the
value by using the circuit states whereas in dynamic
logic the value is stored in the form of charge. The
dynamic logic is supposed to be more advantageous
because of a total absence of output glitching and a
reduced parasitic capacitance. However, static logic
eliminates the need to pre charge and thus reduces extra
power dissipation making it preferred over dynamic
logic.
Static logic is further of two types:
 Single rail: In this logic the output of the logic
gate is a function of any one variable which may be
represented as 0 or 1.If a represents the input the output
is given as f(a).
 Dual rail: These circuits use both the variable
and its complement as an input pair. The output is also
of the form (f, f’) which drives the next gates in logic
cascade.
In this paper we are going to be discussing a few of the
most commonly used static and dynamic logic based
adders and multipliers namely Complementary Pass
Transistor logic (CPL), Static CMOS, Pseudo nMOS,
Nora CMOs, Complementary voltage switch logic
(CVSL),Array multiplier, Wallace tree multiplier,
Dadda multiplier.
 International Journal of Electrical, Electronics and Computer Systems (IJEECS)
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III. ADDERS
The addition of any two variables A and B is given as
the X-OR of A and B. The carry of this addition is given
as the AND of A and B. Design of half adders for
addition of two bits is based on this logic. Full adders
take three variables( A, B, Cin) as the input and the
output is the SUM and the Cout.
The equations are given as follows:
SUM = A XOR B XOR C
Cout = Aʘ B + Bʘ Cin + Cinʘ A
These can be modified and can be written in various
other forms for other implementations.
A. STATIC CMOS
A full adder design is created by using 28 Transistors.
The transistors need to be scaled appropriately to ensure
that the charging time of the load capacitor is same as
that of the discharging time otherwise the pMOS device
becomes slower and the output is distorted and slow.
The advantages of the design include that there is no
power dissipation as there is no direct contact between
the ground and Vcc but the number of transistors are
more. Since there is no direct connection between Vcc
and ground, the short circuit power can be avoided
which decreases the Power dissipation of the circuit. For
n input transistors we need 2n transistors in the whole
circuit as we need 2 transistors for every input.
Fig1.Static CMOS adder schematic
Fig 2.Simulation results of static CMOS adder using
practical nMOS
B. Pseudo nMOS
This logic makes use of 18 transistors to make a full
adder cell. The pMOS is not driven by any signals and
the gate input always remains grounded and therefore
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the pMOS is always on and it is operating in the
saturation region. The pMOS devices pull the output to
Vdd and the nMOS to the ground. However the output
never goes to zero completely as the pMOS is always
ON. This leads to contention. By adjusting the sizes of
the two transistors, optimal values of output can be
achieved. While sizing is should be noted that to get
minimum dc values at the output the wpvalue should be
approximately 1/4th of wn. With increase in the ratio the
dc value at the output also increases but reduces the
output swing obtained. When the nMOS is turned on
there is a direct path between Vdd and ground and hence
short circuit current is present which leads to short
circuit power dissipation.
The features of pseudo nMOS include high speed and
reduced number of transistors at the cost of reduced
output swing, more susceptibility to noise and increase
in power consumption due to the pMOS pull up device.
Fig3.Pseudo NMOS waveforms using practical CMOS
Fig4.Pseudo NMOS schematic
C. Cascode Voltage Switch Logic
CVSL is a dynamic logic family. Unlike the NORA
circuits the complement of the clock is not required.
Replacing the p type transistors in CVSL with a cross
coupled pair of P transistor yields a static version of the
family known as Differential Cascode Voltage Switch
Logic (DCVSL) .The pMOS devices act as a differential
pair and outputs are generated on either sides both in
complementary as well as in its true form.
These devices are comparatively slower as compared to
the others .The size of the pMOS plays a very important
role and needs to be scaled precisely. If the value of wpis
less the charging time increases and the device is slower.
Static power dissipated is comparatively lesser as there
is no direct path between Vdd and ground.
 International Journal of Electrical, Electronics and Computer Systems (IJEECS)
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Fig5.CVSL schematic
Fig6.CVSL waveforms
D. Complementary Pass transistor logic
Full adders implemented using CPL uses 32 transistors.
It is based on multiplexer logic so it needs all inputs
both in true and complementary form and also the
outputs for it to further drive the next stage inputs .Using
only the pass transistor logic would not allow the use of
nMOS in cascade form as it is a weak ‘1’ passing logic
device. Similarly pMOS is a weak ‘0’ passing device
and it gives erroneous outputs if there is no sufficient
noise margin .The use of CPL eliminates these problems
by using the multiplexing logic however it is not suitable
for low power applications as it has routing problems
and large values of time delay.
Fig7.CPL based Full adder
Fig8.CPL waveforms
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E. NORA Logic
NORA logic devices are based on the dynamic CMOS
family. Dynamic CMOS circuits determine the output
based on the state of the clock and the current input.
Some dynamic logic devices face the problem of
monotonicity where the output does not make a
transition from low to high when the input changes from
high to low as it is present in the evaluation phase and
there is no charge left on the load capacitance and the
pMOS cannot pull it to Vdd. A solution to the above
mentioned problem is given by the domino and the
NORA logic. NORA logic uses both the true and
complementary form of the clock. The NORA adder
uses 22 transistors. The p type stage is dynamically
charged high when the clock is low
Fig9.NORA Logic
IV. MULTIPLIERS
Array multipliers are one of the most crucial elements of
the ALU. Most processors employ fast multipliers to
increase the speed of operations both on integer and
floating point values. Digital multiplication is used very
extensively especially in signal processing applications.
These are the following two types of multiplication
schemes:
 Serial Multiplication – This method computes a
set of partial products separately and then finds their
sum to get the final answer. The implementation is
primitive and employs simple architecture.
 Parallel Multiplication – This method generates
the partial products simultaneously. The speed increases
and this is used for high performance machines where
latency needs to be minimized.
Fig10.Array Multiplier
 International Journal of Electrical, Electronics and Computer Systems (IJEECS)
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The above figure shows the serial implementation of a

4*4 multiplier. It is a slow process and uses a lot of
hardware therefore the power dissipated increases. It
used 16 AND gates, 4 Half adders and 8 Full adders
which gives us a total of 12 Full adders. Although it uses
a large number of gates the speed can be increased using
pipelining however large delays are introduced due to
latching.
A. Wallace Multipliers
To decrease the delay at the final output we replace the
ripple carry adder at the bottom with a carry look ahead
adder, such a adder is referred to as the modified array
Fig13.Wallace waveforms
multiplier. Wallace tree multiplier is an example of the
same where the partial products are arranged in a tree B. Dadda multiplier
like fashion. This design helps in reduction of
It is similar in working to the Wallace tree multiplier but
propagation delay and critical path. The tree multiplier
it is comparatively faster and requires less number of
also substantially reduces hardware and power
full and half adders. The worst case delay is of the same
dissipated. It is substantially faster than other designs
order for both designs. Disadvantages of dadda
but it has the disadvantage of being very irregular which
multiplier are that it does not have a very regular
makes it hard to implement in VLSI design and requires
structure which makes it more difficult to implement in
a much larger area. It has the least values for power
VLSI.
dissipated and delay.
The delay values can be reduced to a logarithmic scale,
in fact it can be shown that the propagation delay
through a Wallace tree can be reduced toO( log 3/2 (N))
making it faster than array multiplier.

Fig14.Dadda multiplier
V. CONCLUSION
We have done a comparative study of the different types
of adders and multipliers. One measure of the power
dissipated from a circuit is the number of transistors
which in turn describe the total current. The table below
gives the number of transistors for different types of
Fig11.Wallace tree multiplier adders:
I.Bill of materials for different logic adders
Name of logic Number of transistors
Static CMOS adder 28
Pseudo nmos adder 18
CVSL(carry) 18
CPL 32
NORA 22
II. Worst case delay values
MULTIPLIER MULTIPLIER SIZE IN BITS
Fig12.Wallace tree multiplier schematic TYPE 8 16 32
Modified Array 50 98 198
Wallace/Dadda 35 51 63

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 International Journal of Electrical, Electronics and Computer Systems (IJEECS)
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III. Average number of Logic transitions per REFERENCES

multiplication
[1] Power and Delay Comparison in between
MULTIPLIER MULTIPLIER SIZE IN BITS Different types of Full Adder Circuits-Saradindu
TYPE 8 16 32 Panda1 , A.Banerjee, B.Maji ,
Modified Array 588 7347 99,102 Dr.A.K.Mukhopadhyay Dept. of Electronics and
Wallace/Dadda 573 3875 19,547 Communication Engineering, Narula Institute of
Technology, WBUT, Kolkatta, India Dept. of
Based on the above values we can say that the array Electronics and Communication Engineering,
multiplier become highly inefficient for large number of NIT, Durgapur, India Director, BITM,
bits. They are slower and the average number of logic Santiniketan, Birbhum, West Bengal, India.
transitions become very high as compared to other two.
An advantage of the array multiplier is that the design is [2] Practical Low power digital VLSI design by Gary
regular and easy to implement. The number of Yeap
transistors being used for Wallace and Dadda are more [3] Low power design by Jan.M.Rabaey and
than what the values indicate due to irregularity in MassoudPedram
design.
[4] An Survey on Adders & Multiplier For High
The power dissipation depends on a number of factors Speed & Low Power Application. 1M.Rohini,
which include wiring, number of transistors number of M.Madhumetha, S.RanjithJeppiaar Engineering
transitions, capacitances, area etc. The appropriate adder College, Chennai.
design should be chosen according to the requirement.

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