This one-week faculty development program on FPGA and ASIC design will be held from February 25th to March 1st 2019 at Bharati Vidyapeeth's College of Engineering in New Delhi. The program will cover FPGA design flow using Vivado, ASIC design basics and full custom design flow, and EDA solutions for IC/ASIC design. The registration fee is Rs. 500 per participant and the deadline to register is February 24th 2019.
This one-week faculty development program on FPGA and ASIC design will be held from February 25th to March 1st 2019 at Bharati Vidyapeeth's College of Engineering in New Delhi. The program will cover FPGA design flow using Vivado, ASIC design basics and full custom design flow, and EDA solutions for IC/ASIC design. The registration fee is Rs. 500 per participant and the deadline to register is February 24th 2019.
This one-week faculty development program on FPGA and ASIC design will be held from February 25th to March 1st 2019 at Bharati Vidyapeeth's College of Engineering in New Delhi. The program will cover FPGA design flow using Vivado, ASIC design basics and full custom design flow, and EDA solutions for IC/ASIC design. The registration fee is Rs. 500 per participant and the deadline to register is February 24th 2019.
solutions, Low Volume Manufacturing, System Mr. Ankur Sangal ( Sr. Application Engineer ) BHARTI VIDYAPEETH’S Upgrades and Obsolescence management, EDA tools, COTS products, Semiconductor solutions and University Program, CoreEL Technologies, Ph: 8826892619/9891884347. COLLEGE OF ENGINEERING, NEW DELHI Technology Training. CoreEL is a leading developer of advanced electronic system level products and PRESENTS solutions to three primary markets– Aerospace & Defense, Digital Media Broadcast and Universities & Registration Fees One week FDP Institutions of higher learning. Registration fees is Rs.500/- per participant. This Topics to be covered includes Tea and certificate cost. Lunch facility is on on payment basis in our canteen. The Demand Draft FPGA design flow using Vivado:7-Series Architecture FPGA and ASIC design Overview, Vivado Design Flow-Use Vivado IDE to create a should be drawn in favor of “Principal BVCOE” th simple HDL design, Combinational design, Sequential payable at Delhi before 25 February 2019. th st design. Simulate the design using the XSIM HDL simulator February 25 2019 to 1 march 2019 available in Vivado design suite. Generate the bitstream and Registration verify in hardware. Synthesis Technique. ASIC: Basic of ASIC design , full custom design flow, spice Organized by Participants (Faculty, Research Scholars, Students) need net list, spice models & analysis , layer map file, DRC & to register by filling On-Line registration form LVS rule layout design. Designing of digital blocks using Dept. of ECE, BVCOE, New Delhi (https://goo.gl/forms/QdG110GyIWgRdSHv2) and send Pyxsis Tool, schematic design , spice simulation using Eldo the copy of form with payment proof to tool , layout design Layout design using SDL, caliber DRC, manoj.sharma@bharatividyapeeth.edu . Institute: Caliber LVS, Caliber PEX, post layout simulation. EDA Solutions for IC/ASIC Design & Verification – Semi - Custom Bharati Vidyapeeth’s College of Engineering Design Flow demonstration ( RTL to GDSII Flow )-RTL Last Date of Registration: 24th February 2019 (BVCOE), New Delhi, since its establishment in 1999, Code writing, simulation, synthesis, Floor Planning, has strived to provide the best engineering education Placement, routing, DRC, LVS with XRC. A certificate of participation would be provided to to its students through well-qualified and dedicated the participants on conclusion of the programme. faculty and provision of well-equipped modern labs. REGISTRATION FORM The College is affiliated to Guru Gobind Singh Indraprastha University, New Delhi, and approved by All India Council for Technical Education (AICTE), Name : ……………………………………………………………….. Ministry of HRD, Govt. of India. BVCOE is steadily Academic Qualification: …………………………………….. striding forward in its quest of establishing itself among the top engineering colleges in North India. The vision Designation : ………….……………………..……………………. of the college is to continuously excel and thus coming Department : ………….…………….……………………………. together enlivens the research themes, creates awareness about upcoming technologies and provide Organization : ………….…………………………………………. platform to budding research workers for achieving Address (O) : ……………..…….…………………………………. their rightful place in the scientific community. For further information please contact: Phone/Fax : ……………..……..………………………………. Partner Organisation: For Technical aspects: E-mail : ………………………….………………………………. CoreEL Technologies is a Customer Application Dr. Manoj Sharma, Associate Prof. BVCOE, ND Payment Details (DD No./Date/Amount): Specific Product & Solutions (CASPS) company offering innovative solutions, which ranges across For Registration & Logistics aspects: REGISTRATION Online Link: - Intellectual Property (IP) cores, Design & Mr Prakhar Priyadarshi, Assistant Prof. BVCOE, ND Development, Bespoke System Design & Prototype S B Kumar, Assistant Prof. BVCOE, ND https://goo.gl/forms/QdG110GyIWgRdSHv2 Development, Next-Gen Digital products, Integrated