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Spectral Analysis: P Fundamental 3.162 MW P2 10 Uw P3 31 NW PT 3.172 MW
Spectral Analysis: P Fundamental 3.162 MW P2 10 Uw P3 31 NW PT 3.172 MW
1.1.2 Calculate the total harmonic distortion (THD) of the signal generator. (3)
D2 = 0.056
D3 = 0.003
THD = 5.7 %
1.1.3 Sketch the spectrum analyzer display showing all relevant amplitude levels in dBm and
frequencies in kHz. (3)
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RAE4 Typical questions and POSSIBLE answers Exam Preparation
1.2 Figure 1 below is passed through a 150 kHz band pass filter that has a -3 dB bandwidth
of 10 kHz.
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Signal 1 / V
10
8
6
4
2
0
0 5 10 15 20 25 30 35 40
Time/uSecs 5uSecs/div
Figure 1: Square wave output from a CMOS device
1.2.1 Calculate the amplitude levels of the first 5 harmonic frequencies which would be viewed
on a spectrum analyzer. (3)
1st = 9.549V 2nd and 4th = 0V
3rd = 3.183V 5th = 1.91 V
DC = 7.5 V
1.2.2 Calculate the frequencies of the first 5 harmonics which would be viewed on a spectrum
analyzer. (3)
1st = 50 kHz 2nd = 100 kHz
3rd = 150 kHz 4th = 200 kHz
5th = 250 kHz
1.2.3 Sketch the spectrum analyzer display of the square wave frequency up to the 5th
harmonic. (2)
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RAE4 Typical questions and POSSIBLE answers Exam Preparation
1.2.4 Sketch the possible output of the band pass filter in the time domain. (2)
Signal 1 / V
0
-2
-4
-6
0 2 4 6 8 10 12
Time/uSecs 2uSecs/div
1.2.5 Sketch the frequency response of the band pass filter. (1)
Band pass sketch showing 145 kHz – 155 kHz as the cut-off points
2.1 A CD 4046 phase lock loop (PLL) has an output voltage controlled frequency (VCO) of
1.5 MHz at 20 ºC. The manufacturers indicate a 0.03 % / ºC frequency drift with
temperature on their datasheet.
A NE 568 PLL has a VCO frequency drift with temperature of 100 ppm / ºC.
2.1.1 Calculate the new output frequency of the CD 4046, in kHz, if the temperature changes
to 24 ºC. (3)
Percentage change = 0.12 %
Total drift = 1.8 kHz
New frequency = 1 501.8 kHz
2.1.2 Calculate the parts per million (ppm) drift of the CD 4046 PLL. (1)
At 1 MHz drift = 300 Hz
300 ppm
2.1.2 Conclude which one of the two PLL’s has a smaller frequency drift. (2)
The NE 568 has a smaller drift of 100 Hz at 1 MHz compared to the 300 Hz at 1 MHz for
the CD4046
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RAE4 Typical questions and POSSIBLE answers Exam Preparation
2.2 Design a frequency synthesizer that will generate the amplitude frequency range (AM =
540 – 1600 kHz) used for AM radio broadcasts in South Africa. The reference frequency
must be 20 kHz. Utilize the following parts:
5 by Binary coded decimal (BCD) programmable dividers with a maximum input
frequency of 20 MHz;
1 by CD 4046 PLL with a maximum output frequency of 4 MHz;
1 by LM 565 PLL with a maximum output frequency of 0.5 MHz;
1 by 1 MHz crystal oscillator; and
1 by 15 / 16 Dual modulus prescaler
2.2.1 Calculate the maximum and minimum divider values for the feedback circuit (Remember
that NO decimals are allowed). (2)
Fout = 540 – 1600 kHz
Fmax = 80
Fmin = 27
2.2.4 Calculate the output frequency for a BCD value of 0010 0100 in the feedback circuit.
The first digit is the most significant bit. (1)
N = 32 + 4 = 36
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RAE4 Typical questions and POSSIBLE answers Exam Preparation
2.2.5 Calculate the division factor for the crystal oscillator frequency. (1)
Q = 50
2.2.6 Most PLL circuits face the problem of phase noise. What technique could be used to
overcome this problem? (1)
Direct Digital Synthesis
2.2.7 What purpose does the phase detector serve in the PLL? (1)
Compares two signals with each other and provides a DC voltage corresponding to the
phase difference
350nH 470nH
33pF L1 L2 4.7 k
47k C1 R6
R1
10 12
R4 R5
1nF
+ Vin
Q2N2222
C3
- Vin
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RAE4 Typical questions and POSSIBLE answers Exam Preparation
QUESTION 3 Noise
3.1 Differentiate between amplitude noise and phase noise with the aid of sketches. (4)
Amplitude noise = undesired variation in the output amplitude of an oscillator signal
3.3 Generate a list of steps to be followed for measuring the noise figure of a device using a
calibrated noise source. (4)
Noise source connected to input with a true RMS voltmeter connected to output
With the noise source off, the voltmeter displays the internally generated noise of the
device plus the thermal noise from the generators source resistance
Noise source turned on and adjusted so that the output increases by 3 dB
Noise figure is the read of the noise source
3.4 The following circuitry exists in an electronic circuit operating at a 200 kHz bandwidth.
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RAE4 Typical questions and POSSIBLE answers Exam Preparation
A B C D
Load
Figure 3: Circuit
3.4.1 Calculate the noise voltage of the resistor (R) at 303 K. (1)
En = 1.918 uV
3.4.2 Calculate the signal to noise ratio (S/N) at B if a 56 mV signal is applied at A. (1)
SNin = 89 dB
3.4.4 Calculate the equivalent noise temperature of the system in dB. (1)
Temp = 23.168 dB
3.4.5 Calculate the final S/N ratio developed over the load when a 56 mV signal is connected
to pin A. (2)
SNout = 87.041 dB
QUESTION 4 Antennae
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RAE4 Typical questions and POSSIBLE answers Exam Preparation
4.1.1 What is the common wavelength spacing between the elements? (1)
0.2 wavelengths
4.1.4 Calculate the frequency of operation if the driven element was measured to be 236 mm
long. (1)
603.814 MHz
4.2 Figure 5 below presents a radiation pattern of a selected antenna where each circle
represents +2 dB. The centre point has a value of 0 dB.
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RAE4 Typical questions and POSSIBLE answers Exam Preparation
0
340 350 10 20
330 30
320 40
310 50
300 60
290 70
280 80
270 90
260 100
250 110
240 120
230 130
220 140
210 150
200 160
190 170
180
4.2.3 Determine the angles at which the minor lobes exist. (1)
270 and 90º
5.1 Complete the following table by indicating the question number and its relevant answer
in your examination book.
Table 1: GSM specifications
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RAE4 Typical questions and POSSIBLE answers Exam Preparation
Specification Value
(5)
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RAE4 Typical questions and POSSIBLE answers Exam Preparation
6.1 Design a MBC system that will communicate over a distance of 1880 km. Use the
following parameters:
Transmit power = 750 W
Receiver sensitivity = -120 dBm
Operating frequency = 33 MHz
MBC scatter loss = 60 dB
Transmit antenna gain = Receive antenna gain = 12 dBi
6.1.1 Calculate the system margin. (4)
Pt = 58.7 dBm
EIRP = 70.751 dBm
Total Loss = 188.295 dB
Margin = 14.455 dB
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RAE4 Typical questions and POSSIBLE answers Exam Preparation
7.1.2 Calculate the minimum process gain allowable for a 12 dB S/N ratio at the output. (1)
PG = 35.979 dB
7.1.3 Calculate the minimum required RF bandwidth if the information rate is 8 kbps. (1)
BW = 31.7 MHz
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