Session: Jan-May 2011

School of Electronics
Devi Ahilya University, Indore
Course Plan

Title of Course: CMOS VLSI Design

Code: ECN 41(b)/ELE 41

Level at which course if offered: M.Sc. (Electronics) and M.Sc. (Electronics &
Communication) II Year

Faculty: Dr. Manju K. Chattopadhyay

Prerequisites: A basic course in Digital Design

Aim & Objectives of course: To introduce students to

CMOS logic

CMOS Technologies

Various physical parameters such as delay,sizing, power dissipation,
interconnects

Various limitations such as Velocity Saturation and Mobility
Degradation, Channel Length Modulation,

Concepts of MOS small-signal model

Course Scheduling:

Week Topics to be covered

1-3 CMOS Logic: Inverter, NAND Gate, Combinational Logic, NOR
Gate, Compound Gates, Pass Transistors and Transmission Gates,
Tristates, Multiplexers, Latches and Flip-Flops, CMOS Fabrication
and Layout: Inverter Crosssection, Fabrication Process, Layout
Design rules, Gate Layout, Stick Diagrams. VLSI Design Flow.

4-6 MOS Transistor Theory: Ideal I-V Characteristics, C-V

Characteristics: MOS Capacitance Models, MOS Gate Capacitance
Model, MOS Diffusion Capacitance Model.
Non ideal I-V Effects: Velocity Saturation and Mobility
Degradation, Channel Length Modulation, Body Effect,
Subthreshold Conduction, Junction Leakage, Tunneling, Temp. and
Geometry Dependence. DC Transfer characteristics:
Complementary CMOS Inverter DC Characteristics, Beta Ratio
 Effects, Noise Margin, Ratioed Inverter Transfer Function, Pass
Transistor DC Characteristics, Tristate Inverter, Switch- Level RC
Delay Models.
7-8 CMOS Technologies: Background, Wafer Formation,
Photolithography, Well and Channel Formation, Silicon Dioxide
(SiO2), Isolation, Gate Oxide, Gate and Source/Drain Formation,
Contacts and Metallization, Passivation, Metrology.

Layout Design Rules: Design Rules Background, Scribe Line and

Other Structures, MOSIS Scalable CMOS Design Rules, Micron
Design Rules.

CMOS Process Enhancements: Transistors, Interconnect, Circuit

Elements, Beyond Conventional CMOS
9-10 Delay Estimation: RC Delay Models, Linear Delay Model, Logical
Effort, Parasitic Delay. Logical Effort and Transistor

Sizing: Delay in a Logic Gate, Delay in Multistage Logic

Networks, choosing the Best Number of Stages.

Power Dissipation: Static Dissipation, Dynamic Dissipation, Low-

Power Design.

11-13 Interconnect: Resistance, Capacitance, Delay, Crosstalk. Design

Margin: Supply Voltage, Temperature, Process Variation, Design
Corners. Reliability, Scaling.

14-16 MOS Small-signal Model, Common Source Amplifier, The CMOS

Inverter as an Amplifier, Current Mirrors, Differential Pairs,

2. Refererence Books:
1. Neil H.E. Weste, David Harris, Ayan Banerjee: CMOS VLSI Design, Third
Edition, Pearson Education.
2. J. P. Uyemura: Chip Design for Submicron VLSI, Cengage Learning.
3. J. P. Uyemura: Introduction to VLSI Circuits and Systems, Wiley.
4. Plummer: Silicon VLSI Technology, Pearson Education.

Web References:

Attendance: Strudents are strongly recommended to attend the lecture and complete the
assignments on time. In case of late submission of assignment, you will be evaluated
from 80% of the total.

Grading Policy:
Assignment: 5%
 Minor Test: 35% (2 at 15% each)
Final Exam: 60%
Cumulative exam score, including assignments, both exams and the final, must
be at a passing level (>=30%). Your grade will be based on the following schedule:

A+ Total Average>=90

A 90>Total Average>=80

B+ 80>Total Average>=70

B 70>Total Average>=60

C+ 50>Total Average>=60

C 40>Total Average>=50

D 30>=Total Average>=40

F 30>Total Average

Notes:
1. This syllabus may be changed by the instructor as needed for good academic practice.
2. If any student will absent in any test, Improvement test will only be given in the case of a properly
excused absence with the permission of Head and respective Subject Teacher.