Simple arithmetic operations

Addition (subtraction) of numbers in the sign magnitude representation

In the case of addition (subtraction) of binary numbers with signs in the sign magnitude representation we
have to compare the signs and proceed depending on the signs of arguments: add or subtract the magnitudes
with a proper sign generation.

At consecutive binary positions, bits of arguments and a carry (borrow) bit from a previous position are added
(or subtracted) with carry (borrow) bit generation to the next position. The operation result is obtained after
the operation has been performed on all argument positions.

When big magnitude numbers are added the overflow can occur which is the carry over-passing the size of
the argument magnitudes (to the sign position). We have here the arithmetic overflow which results from the
fact that the result value does not fit the scope of number which can be written in a word of a given length.
The result is not correct and an execution error is signaled. The arguments of the operation should be then
decreased (shifted in the binary way to the right) and the operation should be performed again.

When we add numbers 010100010 (+162) and 011010001 (+209), we add magnitudes of the numbers and
we obtain

10100010
+11010001
(1)01110011 (-115 instead of +371)
A carry appeared to the sign position, the result has changed the sign and it is incorrect.

After we shift arguments one position to the right, the result will be correct.

3.2. Addition (subtraction) in the 2's complement representation

Addition of binary number with the sign in the 2's representation is performed in the same way as for the
numbers without the signs i.e. with carry to the sign position treated as a normal thing. During addition of
negative numbers the carry out of the sign position is treated as a normal thing and it is neglected.

Example

When adding positive or negative numbers that have very large magnitudes, the result obtained can be
incorrect due to the appearance of the overflow, as in the example below.

000101101 (+45) 11000110 (-58)

+000010001 (+17) +11010001 (-47)
000111110 (+62) (1)10010111 (-105)
Therefore, the overflow occurrence is always checked with the use of additional testing logical circuits
connected to the adder. The check of the overflow sets the overflow flip-flop(flag) of the processors and this
is signaled as an error to the operating system.

00111101 (+61)
+01010001 (+81)
10001110 (-114 instead of +142, the result has changed its sign)

10100010 (-94)
+11010001 (-47)
 (1)01110011 (+115 instead of -141, the result has changed its sign)
Subtraction in the 2's complement representation is performed by adding to the minuend the 2's complement
of the subtrahend, i.e, by adding the complemented subtrahend with a binary number that has zeros on all
positions except the least significant position on which 1 appears.

01101101 (+109)
- 01010001 (+81)
01101101

+ 00000001
00011100 (+28)

3.3. Adders and subtractors for the 2's complement representation

Addition (subtraction) is executed by adding (subtracting) bits on consecutive positions with carries
(borrows) between neighbouring positions. q

Adders (subtractors) are built as a sequence of circuits, which perform operations on bit positions being
supported in some cases by circuits that speed-up carry generation.

We distinguish:

Binary and binary coded decimal adders (subtractors)

Serial and parallel adders (subtractors).
Serial adders (subtractors) perform addition (subtraction) of all pairs of digits in parallel.

Parallel adders (subtractors) perform addition (subtraction) of consecutive pairs of digits in parallel in
consecutive executive cycles.

Among parallel adders we distinguish:

Ripple carry adders (subtractors)

Carry look-ahead adders (subtractors)
Carry select adders (subtractors).
To perform addition in the 2's complement representation we use adders whose structures are shown below.
To construct adders half-adders and elementary (single -bit) adders are used. A half-adder (HA) performs
addition of two bits on a given position and generates the carry to the next position. An elementary (single-
bit) adder adds 3 elements: two bits on a given position and a carry from the previous position. An elementary
adder can be built using two half-adders. Their structure has been described in the previous lecture as an
example of combinational circuits.

One stage of an adder built of two half-adders

Ripple carry (parallel) adders are constructed as a ripple structure of elementary adders (i.e. a structure in
which a carry output from the preceding position is transferred to the input at the next position). In ripple
carry adders an important execution slowdown is observed due to the propagation of carries through all adder
positions (stages). The addition result can be read only after a period of time (delay), which corresponds to
the propagation of the carry in the worst case i.e. assuming it equal to 1 and propagated through all adder
positions. For long addition arguments the delay is many times bigger than the delay coming from a single
adder stage.
 A ripple carry adder for 2's complement representation

To subtract numbers in 2's complement representation the same circuits are used as for addition (it is a big
advantage of the 2's complement representation) but the arguments are slightly transformed, which is
implemented in a very simple way. On one adder input, the minuend is supplied. On the other input, the
complemented subtrahend is supplied with the value one supplied to the carry input of the lest significant
position. The result appears on the adder output only when the carry propagation process has been
completed.

A ripple carry subtractor for 2's complement representation

To eliminate the delay due to carry propagation in adders different solutions are applied.

the first solution is to built circuits, which generate carries for all positions in the same time, in parallel with
additions executed on all bit positions. It is useful, since the carry generation circuits incure smaller delays
than the carry propagation in ripple carry adder.

The adders of this type are called carry look-ahead adders. The carry generation circuits are 3-level logical
combinational circuits , which work according to the logic equations shown below.

C1 = g0 + C0p0

C2 = g1 + p1g0 + p1p0C0

C3 = g2 + p2g1 +p2p1g0 + p2p1p0C0

C4 = g3 + p3g2 + p3p2g1 + p3p2p1g0 + p3p2p1p0C0

Carry generation circuit for the 4-th adder position

Signal propagation concerned with carry generation for any position of the adder incurs a delay equal to the
signal transition time through three logical gates, instead of, in the worst case, the propagation of a signal
through all the adder circuitry.

An exemplary carry look-ahead adder scheme (for 4-bit arguments) is shown below.

Carry look-ahead adder

Another solution for the adder which speeds-up addition is carry select adder (CSA). In this adder the
arguments bit sequences are divided into two halves. For each pair of half-sequences of argument bits
separate adders are built. For low-order bits it is one ripple carry adder. For high-order bits - two ripple carry
adders are used, working in parallel: one acting with the initial carry equal to 0 and another with the carry
equal to 0. When the carry from the low-order bits - adder is ready, the generated carry select one of the
results produced by the high-order bits - adder to be read as the addition result. Such an adder speeds-up
addition about 2 times, however at the cost of important build-up of the adder hardware. The constituent
adders in this solutions can be divided into smaller ones which work using the described idea of speculative
additions for conditional carries, thus further speeding-up the addition.

Carry select adder

3.4. Other combinational arithmetic units

A serial adder is built with use of a single elementary adder to which pairs of bits from argument consecutive
positions are supplied. Such addition implementation is very slow but the operation is done using a minimal
quantity of hardware. Serial adders were applied in early computers, when the cost and sizes of digital
circuits were very big. They were also used in electronic calculators where high operational speed was not
required.

Serial adders

In the first figure a serial adder is shown which includes an elementary adder and 3 registers. The added
components are stored in two shift registers. The initial carry and the carry generated for each pair of
argument bits is stored in the D flip-flop. The sum bit - the addition result of each pair of bits and the carry
from the previous position (taken from the D) is written into the shift register for the sum. The writes take
place with the rising edge of the clock signal supplied on the input C. The same signal shifts the contents of in
all the 3 registers on position to the right. After a shift has been completed, the elementary adder "sees" two
new argument bits and implements their addition with the carry from the D flip-flop.

The second schematic shows more economic serial adder design, which is based on only two shift registers.
Initially both registers store the arguments X and Y of the addition. After completion of each two bits addition
the result is written into the accumulator register, on the input position which is liberated as a result of
shifting the contents of this register by clock signals. At the same time, the carry generated on the basis of
addition of two argument bits and the old carry is written into the flip-flop. When all bits of arguments have
been shifted out, the accumulator register contains the result of addition and the D flip-flop contains the last
generated carry.

An important type of arithmetic units is the binary comparator. It is a combinational circuit composed of many
stages which compare pairs of bits on consecutive positions of compared numbers. It transfers 2 elementary
comparison result bits between positions (in a similar way as an adder does). After propagation of elementary
comparison results through all comparator stages, the final logical circuit composed of 3 gates, generates the
final comparison result on its 3 outputs: equal, smaller, greater.

Inputs and outputs of a comparator

Logic diagram of a comparator

One stage of a comparator and the result generator

Logical-arithmetical units are frequently produced as multi-functional integrated arithmetic modules, which
perform different arithmetical and logical operations as well as their combinations on arguments of given
length, for example 4-bit. By connecting many such units in ripple structure we can build arithmetical-logical
units for long (multi-bit) arguments.

Ripple structure of multi-functional integrated arithmetic modules

Below we can see the specification of an exemplary multi-functional arithmetic unit. The selection of a
function to be performed is done by setting the control inputs M, F 0, ..., F3.

For M=1 the circuit performs logical operations, for M=0 the circuit executes arithmetical operations or
combinations of logical and arithmetical operations. Inputs F i determine the selected operation for agiven M.
The arguments A, B are supplied on inputs Ai, Bi. The result appears on output Si. The pins Cn, Cn+1 are used
for input and output of a carry, which is useful when connecting modules in a ripple structure. The pins G, P
can be used to built more complicated adders. The pin A=B is used for comparison of numbers A, B.

Pins of multi-functional arithmetical-logical module

The table shown below describes functions and control principles for the multi-functional arithmetical module.
For M=0 and F1 F2 F3 F4 = 1001 the module performs arithmetic addition. For M=0 and F 1 F2 F3 F4 = 0110,
the circuit performs arithmetic subtraction. The comparison of A and B is done for M=0 and F 1 F2 F3 F4 =
1001 and Cn = 1, with egzamining outputs G, P: when equal to 00 then A<B, when 10 then A=B, when 11
then A>B. For M=1 and F1 F2 F3 F4 = 1001 the circuit furnishes the complement of A on the output S. For
M=1 and F1 F2 F3 F4 = 1011 the circuit furnishes on the logical product of A and B. For M=0 and different
combinations on inputs F, the circuit performs different mixed logical-arithmetical operations.