2014 IEEE International Conference on Advanced Communication Control and Computing Technologies (ICACCCT)

A Low Power Schmitt Trigger Design using SBT

technique in 180nm CMOS Technology
Ambothu Suresh1
1
School of VLSI Design & Embedded Systems, National Institute of Technology Kurukshetra, INDIA
1
sureshkumar0452@gmail.com

Abstract— This paper presents the effect of source voltage and
load capacitance on the performance of CMOS Schmitt
Trigger circuit with self-bias transistor (SBT) technique which
was used to reduce power. The CMOS Schmitt Trigger circuit
was modified by designing the transistors aspect ratio on the
basis of conventional CMOS Schmitt Trigger and it is
implemented using CADENCE Virtuoso in Spectra Simulator
using UMC-180nm technology for different modified design.
Results are compared in terms of propagation delay, power,
and energy- delay product. From the simulation results, the
modified CMOS Schmitt Trigger was able to operate between
0.8V to 1.5V voltage range.
provides better noise margin and noise stable operation than
the inverter. The important applications of Schmitt trigger
circuit which is broadly used in input buffer to improve noise
immunity, sub threshold SRAM [10-11], image sensor [4],
and pulse width modulation circuits [5]. The CMOS Schmitt
trigger is consist of three NMOS transistors(N1,N2,and N3),
and three PMOS transistors(P1,P2,and P3) fig.1(a) and
fig.1(b) shows the basic CMOS Schmitt trigger circuit design
and its DC transfer characteristics curve[1].

Keywords— Schmitt trigger, hysteresis, aspect ratio, propagation

delay, low power, leakage reduction.

I. INTRODUCTION
Schmitt trigger is important in electronics system. It is
used in analog and digital circuit as to convert irregular time
varying signal to a perfect shape (or) square wave to solve
noise problem. This circuit is broadly designed in different
fashion in order to operate the load with fast switching, low
power dissipation and low supply voltage, especially for the
high capacitive load problem [2], and it consist two states
like other multi-vibrators. Its output state depends on the Fig. 1 (a).CMOS Schmitt trigger circuit
input state, and will change only when the input voltage
cross a certain pre-defined voltage. When the input voltage is
at 0V and output state is high, and when the input voltage
increases from 0V to VDD, output is pulled down and
switching threshold voltage of the circuit is (VH), i.e. upper
threshold voltage. When the input decreases from VDD to 0V
then the output of the circuit is pulled up, and switching
threshold voltage is (VL) i.e. lower switching threshold
voltage. The voltage difference between the upper switching Fig. 1(b) DC transfer characteristics curve.
threshold voltage and lower switching threshold is called as
hysteresis voltage [1-4]. Schmitt trigger is implemented with II. CIRCUIT DESCRIPTION
the help of operational amplifier (op-amp) by connecting two In the fig. 2 (a) shows the modified Schmitt trigger [10],
current limiting resistors in closed loop path (positive which is divided into two, parts i.e. part1 and part2. Patr1 of
feedback).But this arrangement is not suitable for the the circuit consist of three PMOS (P1, P2 and P3) named as
integration circuit in CMOS (Complementary Metal Oxide p-sub circuit and part2 of the circuit consist of three NMOS
Semiconductor) technology due to (a) high gain of op-amp, (N1, N2 and N3) it is named as n-sub circuit. Where n-sub
(b) current limiting resistor values, (c) area utilization of the circuit gives the forward switching threshold voltage (VH)
resistor is poor [7]. and p-sub circuit controlled the reverse switching voltage
The main difference between Schmitt trigger and (VL), switching threshold voltages depends on the aspect
comparators lies in DC transfer characteristics[5] are the ratio of PMOS and NMOS transistors.
transfer characteristics of the comparator shows only one P-sub circuit of the modified Schmitt trigger shows two
switching threshold and Schmitt trigger shows two different PMOS are connected in parallel and two NMOS are
switching threshold points, which are positive-going and connected series in n-sub circuit which forms the NAND
negative-going input signal. The hysteresis of Schmitt trigger gate by modifying conventional Schmitt trigger according to

ISBN No. 978-1-4799-3914-5/14/$31.00 ©2014 IEEE 533

 2014 IEEE International Conference on Advanced Communication Control and Computing Technologies (ICACCCT)
De’morgan’s theorem. In p-sub circuit two PMOS are
connected in parallel, the resistance of the p-sub circuit is
reduced to half and propagation delay of the circuit is
decrease because propagation delay is more concentrate on
PMOS due to low mobility of PMOS compare to mobility of
NMOS. P3 and N3 are two feedback transistors which act as
pull up (P3) and pull down (N3) for the output at every time.
P3 and N3 gate terminal is directly connected to the output
terminal.
Fig. 2 (a) modified Schmitt trigger
The aspect ratio of the transistors is set according to their
arrangement. If two transistors that are connected in series
that are scaled by factor of 2 and if two transistors are
connected in parallel each transistor scaled by factor of 1,
aspect ratio of the transistor set according to the equation
(2.1) .
The aspect ratio of the transistor is set to be three to
create the symmetrical voltage transfer characteristics and to
maximize the noise margin, to make the hysteresis width of
the Schmitt trigger is rectangles the width of the PMOS
transistor has to be increased which are desirable in this
circuit.
When the input is 0V P1, P2 transistors turn ON ,and
output is high (VDD), pull up transistor (P3) is OFF source
and gate voltages are equal, and when the input is changed
from 0V to VDD then N1, N2 transistors are ON and output is
low, pull down transistor (N3) is OFF.
III. SELF –BIAS TRANSISTOR
Fig. 3 (a) NMOS self-bias transistor (b) PMOS self-bias transistor
A CMOS transistor act as a switch, which is controlled by
the gate voltage. The Self-Bias Transistor techniques are
used in the CMOS digital circuits to reduce the power in
both the active and standby mode. It is used in static and
dynamic CMOS circuits [13], fig. 3(a), 3(b) shows the
NMOS and PMOS self-bias transistors.
Fig. 3(c).modified Schmitt trigger with self-bias transistors connected
A Self-bias transistor is used in the Schmitt trigger as
shown in fig.3(c). In the Schmitt trigger PMOS self-bias
transistor is connected between the supply voltage (VDD)
and top of the pull-up network, NMOS self-bias transistor
is connected between the ground and bottom of pull-down
network. This technique reduces the standby leakage power
when the circuit is in off state, and also it reduces active
power [14]. The current flowing through the device depends
on the threshold voltage, gate to source voltage and drain
voltage as shows in equation (3.1).
Where ID drain current, K is process trans-conductance
parameter, W is minimum device width, L is channel length
of the given process technology, VDS drain to source voltage,
and gate to source voltage (VGS).
IV. SIMUTION RESULTS
The circuits are simulated with UMC-180nm technology
using cadence virtuoso spectra simulator at 1GHZ frequency.
The three designs (1st, 2nd and 3rd) represents the
conventional and modified Schmitt trigger with aspect ratio
of the transistors set according to [9], table I. shows the
transistor dimensions 1st and 2nd design represent the
conventional Schmitt trigger with respective aspect ratios so
we are not showing, and our main emphasis on design3
which represents the modified Schmitt trigger circuit. An
obtained results are compared in terms of performance
parameters, i.e. propagation delay, power, energy-delay
product.
534
 2014 IEEE International Conference on Advanced Communication Control and Computing Technologies (ICACCCT)
Table I. TRANSISTOR DIMENSIONS B. ENERGY DELAY PRODUCT
L=180nm Design1 Design2 Design3 The Energy-Delay Product of the circuit can be obtained
(W/L) (W/L) (W/L)
P1 8 6 3 by using equation (4.2) and which is directly proportional to
P2 8 6 3 the power-delay product and propagation delay of the circuit.
P3 1 3 3
N1 10 2 2
N2 10 2 2
(4.2)
N3 8 1 1 From the Energy-Delay Product tables design3 has less
A. PROPAGATION DELAY EDP compare to design1, and design2. And we can observe
that as load capacitance is increase EDP also increases with
Time taken for a Schmitt trigger logic gate output to respect to the load capacitance. Fig. 7, 8 &9shows the
change after one or more input have changed is known as Energy-Delay Product of the three designs at various load
propagation delay[3], Schmitt trigger is used in interconnects capacitances at CL=0.00Pf, CL=0.005Pf, and CL=0.010Pf.
as an alternate to buffer to minimize the propagation delay
and power. This circuit has the positive feature, the
switching threshold voltage can be adjusted and it can be
controlled. Where the propagation delay of the circuit is
more at low supply voltage and at high supply voltage delay
of the circuit is less.

From the propagation delay tables shows at lower supply Fig. 7 EDP at CL=0.00pF
voltage and lower load capacitance (0.005pF) 3rd design
gives less delay compared to design1 and design2. The
desig2 has more propagation delay compare to design1, and
design3, but the design1 gives less delay at supply voltage
(0.8v) and load capacitance (0.010pF). Fig. 4, 5, 6 shows the
propagation delay of the three designs at various load
capacitance i.e. CL=0.00pF, CL=0.005pF, and CL=0.010pF.

Fig. 8 EDP at CL=0.005pF

Fig. 4 Propagation delay at CL=0.00pF

Fig. 9 EDP at CL=0.010pF

Fig. 5 Propagation delay at CL=0.005pF
C. POWER ANALYSIS
In CMOS devices total contribution of power includes
static and dynamic components during the active mode of
operation. The standby leakage power due to standby
leakage current occurs when the circuit is in standby mode
[13]. The dynamic power occurs when the circuit is in active
mode due to change in transistor state from ON and OFF,
charging and discharging of load capacitance [12]. The short
circuit power is the other component of the total power,
which is due to the non- zero rise and fall time of the input
waveform.

Where is switching activity, f is operating

frequency, VDD is supply voltage, CL is load capacitance, and
Fig. 6 Propagation delay at CL=0.010pF ID is drain current of the circuit, comparison of various
power using self bias transistor technique for design3

535
 2014 IEEE International Conference on Advanced Communication Control and Computing Technologies (ICACCCT)
modified Schmitt trigger given in following table II and fig. [5] C. Kho Pham “Cmos Schmitt Trigger Circuit with controllable
10, 11 & 12shows the dynamic power with self-bias hysteresis using logical threshold voltage control circuit” IEEE
Vol.36, No.1821-1824, 2007.
transistor at various load capacitances, supply voltages.
[6] S.L.Chen and K.Ming-Dou, “A new schmitt trigger circuit in a 0.13µ
1/2.5v CMOS processes to receive 3. 3v input signals," IEEE
Table II. STATIC POWER OF MODIFIED SCHMITT TRIGGER Transaction on Circuits and System 2; Express Briefs, Vol.52, issue
USING SBT 7. pp. 361-365, 2005.
VDD(V) Design3 static power Design3 static power [7] S. Franco, Design with Operational Amplifier and Analog Integrated
without SBT with SBT Circuit, New York: McGraw-Hill,1988.
0.8 1.314p 1.202p [8] Sapawi, R.; Chee, R.L.S.; Sahari, S.K.; Julai, N.; , "Performance of
1 10.01p 4.882p CMOS Schmitt Trigger," International Conference on Computer and
1.2 1.729n 6.608p Communication Engineering ICCCE 2008., vol., no., pp.1317-1320,
1.5 1.953u 9.469p 13-15 May 2008.
[9] S. Franco, Design with Operational Amplifier and
Analog Integrated Circuit, New York: McGraw-Hill,
1988.
[10] Jay deep P. Kulkarni, Keejong Kim, and Kaushilc, “A 160mV robust
schmitt trigger based sub-threshold SRAM," IEEE Journal of the
solid-state circuit. Vol.42, No. 171-176, Oct 2007.
[11] V.Katyal, R. L. Geiger and D. J. Chen, “Adjustable Hysteresis CMOS
Schmitt Trigger," IEEE ISCAS, pp.1938-1941,2008.
[12] Swati Kundra, Priyanka Soni. “Low power Scmitt Trigger “ISSN
Fig. 10 Dynamic power at CL= 0.00pF 2222-1727 Vol.3, No.2, 2012.
[13] Aaron Arthurs, Justin Roork, and jiadi, “A Comparative study of
ultra-low voltage digital circuit design," International Solid State
Circuit Conference (ISSCC) 2012
[14] Ankur Goel, Baquer Mazhari “Gate Leakage and Its Reduction in
Deep Submicron SRAM” 18th International Conference on VLSI
Design held jointly with 4th International Conference on Embedded
Systems Design (VLSID’05) 1063-9667/05 $20.00 © 2005 IEEE.
[15] R. Sapawi, R.L.S Chee, S.K Sahari, S. Suhaili, Simulation of CMOS
Fig. 11 Dynamic power at CL=0.005pF Schmitt Trigger, Asia-Pacific Conference on Applied
Electronicmagnetics, 4-6 December 2007, Melaka.

Fig. 12 Dynamic power at CL=0.010pF

CONCLUSION
In this paper a modified Schmitt trigger is
designed, which is able to operate as low voltage as much
between (0.8V-1.5V) with self-bias transistor technique
to reduce the power. Which is giving very less power
compare to conventional circuit and modified circuit is
giving less propagation delay and less energy-delay
product.
REFERENCES
[1] Filanovsky, I.M.; Baltes, H.; "CMOS Schmitt trigger design,"
Circuits and Systems I: IEEE Transactions on Fundamental Theory
and Applications, vol.41, no.1, pp.46-49, Jan 1994.
[2] Dejhan, K., Tooprakai, P., Rerkmaneewan, T. Soonyeekan, C., A
high-speed direct bootstrapped CMOS Schmitt trigger circuit
,Semiconductor Electronics, 2004. ICSE 2004. IEEE International
Conference, 7-9 December 2004.
[3] Kulkarni, K. Kim, and K. Roy, “A 160mV robust schmitt trigger
based sub-threshold SRAM," IEEE J. Solid State Circuits, Vol.42,
NO. 10, pp. 2303-2313, October 2007.
[4] Pedroni, “LOW-Voltage high speed schmitt trigger and compact
window comparator," IEEE Electronics Letter, Vol.41, no.22, 1213-
1214, 2005

536