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f31 Book Arith Pres Pt1
f31 Book Arith Pres Pt1
Number Representation
Parts Chapters
1. Numbers and Arithmetic
2. Representing Signed Numbers
I. Number Representation 3. Redundant Number Systems
4. Residue Number Systems
Elementary Operations
II. Addition / Subtraction 7. Variations in Fast Adders
8. Multioperand Addition
Chapter Highlights
What goes on inside your calculator?
Ways of encoding numbers in k bits
Radices and digit sets: conventional, exotic
Conversion from one system to another
Dot notation: a useful visualization tool
Mar. 2015 Computer Arithmetic, Number Representation Slide 5
Numbers and Arithmetic: Topics
Unsigned integers
Signed-magnitude
3 + 1 fixed-point, xxx.x
2 + 2 floating-point, s 2 e e s
e in [2, 1], s in [0, 3]
i l
One can generalize to:
Arbitrary radix (not necessarily integer, positive, constant)
Arbitrary digit set, usually {–, –+1, . . . , –1, } = [–, ]
u = w.v
= ( xk–1xk–2 . . . x1x0 . x–1x–2 . . . x–l )r Old
= ( XK–1XK–2 . . . X1X0 . X–1X–2 . . . X–L )R New
(((((3 / 5) + 3) / 5 + 0) / 5 + 2) / 5 + 2) / 5
|-----| : : : :
0.6 : : : :
|-----------|
3.6
:
:
:
:
:
: Horner’s
|---------------------|
0.72
:
:
:
:
rule or
|-------------------------------|
2.144
:
:
formula
|-----------------------------------------|
2.4288
|-----------------------------------------------|
0.48576
+
(a) Addition
(b) Multiplication
Chapter Goals
Learn different encodings of the sign info
Discuss implications for arithmetic design
Chapter Highlights
Using sign bit, biasing, complementation
Properties of 2’s-complement numbers
Signed vs unsigned arithmetic
Signed numbers, positions, or digits
Extended dot notation: posibits and negabits
0 Bit pattern
1110 -7 +1 0010
(representation)
-6 +2
1101 Signed values 0011
-5 +3
(signed magnitude)
Decrement 1100 -4 _ + +4 0100 Increment
-3 +5
1011 0101
-
+2 +6
1010 - -1 +7 0110
-0
1001 0111
1000
Fig. 2.1 A 4-bit signed-magnitude number representation
system for integers.
Mar. 2015 Computer Arithmetic, Number Representation Slide 25
Signed-Magnitude Adder
Sign x Sign y x y
Selective
Selective
Comp
Complxx Complement
complement
___
Add/Sub
Add/Sub
Control
c out Adder cin
Sign
Selective
Selective
Comp
Compl s s complement
Complement
Sign s s
Fig. 2.2 Adding signed-magnitude numbers using precomplementation
and postcomplementation.
Mar. 2015 Computer Arithmetic, Number Representation Slide 26
2.2 Biased Representations
0000
1111 0001
-8 Bit pattern
1110 +7 -7 0010
(representation)
+6 -6
1101 Signed values 0011
_
+5 -5
(biased by 8)
Increment 1100 +4 -4 0100 Increment
1011
+3 + -3
0101
+2 -2
1010 +1 -1 0110
0
1001 0111
1000
M -2 +0 Unsigned
-1 +1 2
representations
-2 +2
3
Decrement
_ Signed values +3
Increment
+
+4 4
-N
+P
M-N
P
Fig. 2.4 Complement representation of signed integers.
1100 -4 _ + +4 0100
M = 2k
2k – x = [(2k – ulp) – x] + ulp
= xcompl + ulp
-5 +5
1011 0101
Range of representable
-6 +6
numbers in with k whole bits:
1010 -7 +7 0110
-8
from –2k–1 to 2k–1 – ulp
1001 0111
1000
Fig. 2.5 A 4-bit 2’s-complement number representation system for integers.
Mar. 2015 Computer Arithmetic, Number Representation Slide 32
1’s-Complement Number Representation
0000
1111 0001
+0 Unsigned
1110 -0 +1 0010
representations
-1 +2
1101 Signed values 0011 One’s complement = digit
-2 +3
(1’s complement) complement (diminished radix
1100 -3 _ + +4 0100
complement) system for r = 2
M = 2k – ulp
-5 +6 Range of representable
1010 -6 +7 0110 numbers in with k whole bits:
-7
from –2k–1 + ulp to 2k–1 – ulp
1001 0111
1000
Signed-magnitude
Selective
Selective
Comp
Complxx Complement
complement adder/subtractor is
___
significantly more
Add/Sub
Add/Sub
Control
complex than a
c out Adder cin
simple adder
Sign
Selective
Selective
Comp
Compl s s complement
Complement x y
Controlled
Sign s
Fig. 2.2 s complementation
0 1
Mux
_
2’s-complement y or y
adder/subtractor ___
needs very little Adder add/sub
cout cin
hardware other than 0 for addition,
s=x y 1 for subtraction
a simple adder Fig. 2.7
Sign removal
Sign Unsigned
f
logic operation
Adjustment
f(x, y)
f(x, y)
Fig. 2.8 Direct versus indirect operation on signed numbers.
Check:
x = (1 0 1 0 0 1 1 0)two’s-compl
–x = (0 1 0 1 1 0 1 0)two
27 26 25 24 23 22 21 20
64 + 16 + 8 + 2 = 90
Fig. 2.9 Interpreting a 2’s-complement number as having a
negatively weighted most-significant digit.
Mar. 2015 Computer Arithmetic, Number Representation Slide 39
Associating a Sign with Each Digit
Signed-digit representation: Digit set [, ] instead of [0, r – 1]
Example: Radix-4 representation with digit set [1, 2] rather than [0, 3]
3 1 2 0 2 3 Original digits in [0, 3]
2’s-complement number
Negative-radix number
+
(a) Addition
(b) Multiplication
Chapter Goals
Explore the advantages and drawbacks
of using more than r digit values in radix r
Chapter Highlights
Redundancy eliminates long carry chains
Redundancy takes many forms: trade-offs
Redundant/nonredundant conversions
Redundancy used for end values too?
Extended dot notation with redundancy
5 7 8 2 4 9
+ 6 2 9 3 8 9 Operand digits in [0, 9]
––––––––––––––––––––––––––––––––––
11 9 17 5 12 18 Position sums in [0, 18]
Fig. 3.1 Adding radix-10 numbers with digit set [0, 18].
ti
s i+1 si s i–1
s i+1 si s i–1
(Impossible for positional
system with fixed digit set)
s i+1 si s i–1
(a) Ideal single-stage carry-free. (b) Two-stage carry-free. (c) Single-stage with lookahead.
Binary
Binary Binary-to- One or more Redundant Output
Inputs
redundant arithmetic -to-binary
converter operations converter
Overhead Overhead
(often zero) (always nonzero)
11 9 17 10 12 18 18 = 10 (carry 1) + 8
11 9 17 10 13 8 13 = 10 (carry 1) + 3
11 9 17 11 3 8 11 = 10 (carry 1) + 1
11 9 18 1 3 8 18 = 10 (carry 1) + 8
11 10 8 1 3 8 10 = 10 (carry 1) + 0
12 0 8 1 3 8 12 = 10 (carry 1) + 2
1 2 0 8 1 3 8 Answer;
all digits in [0, 9]
1 1 2 0 2 0 2 = 2 (carry 1) + 0
1 1 2 1 0 0 2 = 2 (carry 1) + 0
1 2 0 1 0 0 2 = 2 (carry 1) + 0
2 0 0 1 0 0 2 = 2 (carry 1) + 0
1 0 0 0 1 0 0 Answer;
all digits in [0, 1]
Example 3.3: Convert from digit set [0, 18] to [6, 5] in radix 10 (same as
Example 3.1, but with the target digit set signed and redundant)
11 9 17 10 12 18 18 = 20 (carry 2) – 2
11 9 17 10 14 2 14 = 10 (carry 1) + 4
11 9 17 11 4 2 11 = 10 (carry 1) + 1
11 9 18 1 4 2 18 = 20 (carry 2) – 2
11 11 2 1 4 2 11 = 10 (carry 1) + 1
12 1 2 1 4 2 12 = 10 (carry 1) + 2
1 2 1 2 1 4 2 Answer;
all digits in [6, 5]
Example 3.4: Convert from digit set [0, 2] to [1, 1] in radix 2 (same as
Example 3.2, but with the target digit set signed and redundant)
Carry-free conversion:
1 1 2 0 2 0 Carry-save number
–1 –1 0 0 0 0 Interim digits in [–1, 0]
1 1 1 0 1 0 Transfer digits in [0, 1]
––––––––––––––––––––––––––––––––––––––––
1 0 0 0 1 0 0 Answer;
all digits in [–1, 1]
Fig. 3.7 Four encodings for the BSD digit set [–1, 1].
Posibit {0, 1}
(n, p) encoding
Two of the Negabit {–1, 0}
encodings
above Doublebit {0, 2} 2’s-compl. encoding
can be shown Negadoublebit {–2, 0}
in extended Unibit {–1, 1}
2’s-compl. encoding
dot notation
(a) Extended dot notation (b) Encodings for a BSD number
1 0 1 –1 0 1 –1 0 1 xi
Radix-8
+ 0 1 1 –1 1 0 0 1 0 yi GSD
with
1 1 2 –2 1 1 –1 1 1 pi
digit set
–1 0 –1 wi [4,7]
1 –1 0 t i+1
1 –1 1 1 0 1 1 –1 1 1 si
Fig. 3.9 Example of addition for hybrid signed-digit numbers.
ei t'i t (1)
i
t (2)
i
ti ti
s i+1 si s i–1
s i+1 si s i–1 s i+1 si s i–1
(a)
(a)Three-stage carryestimate
Three-stage carry estimate. (b) Three-stagerepeated
(b) Three-stage repeated-carry.
carry (c)Tw
(c) Two-stage parallel-carries
o-stage parallel carries
1 1 0 1 0 BSD representation of +6
1 0 0 0 0 Positive part
0 1 0 1 0 Negative part
0 0 1 1 0 Difference =
Conversion result
The negative and positive parts above are particularly easy to obtain
if the BSD number has the n, p encoding
Chapter Highlights
Moduli, range, arithmetic operations
Many sets of moduli possible: tradeoffs
Conversions between RNS and binary
The Chinese remainder theorem
Why are RNS applications limited?
Mar. 2015 Computer Arithmetic, Number Representation Slide 69
Residue Number Systems: Topics
We will see later how the weights can be determined for a given RNS
Result
Fine tuning: Combine pairs of moduli 2 & 13 (26) and 3 & 7 (21)
RNS(26 | 21 | 17 | 11) M = 102 102
RNS(22 | 3) M = 12
RNS(32 | 23 | 7 | 5) M = 2520
RNS(11 | 32 | 23 | 7 | 5) M = 27 720
RNS(13 | 11 | 32 | 23 | 7 | 5) M = 360 360
(remove one 3, combine 3 & 5)
RNS(15 | 13 | 11 | 23 | 7) M = 120 120
4 + 4 + 4 + 3 + 3 = 18 bits
Fine tuning: Maximize the size of the even modulus within the 4-bit limit
RNS(24 | 13 | 11 | 32 | 7 | 5) M = 720 720 Too large
We can now remove 5 or 7; not an improvement in this example
Binary
Binary Binary-to- One or more RNS-to- Output
Inputs
RNS arithmetic binary
converter Operations converter
(2 | 3 | 2)RNS(7|5|3) = (2 | 0 | 0) + (0 | 3 | 0) + (0 | 0 | 2)
= 2 (1 | 0 | 0) + 3 (0 | 1 | 0) + 2 (0 | 0 | 1)
= 2 15 + 3 21 + 2 70
= 30 + 63 + 140
= 233 = 23 mod 105
Therefore, x = (23)ten
Errors can be estimated and kept in check for the particular application
That is, with fast log-time adders, addition needs O(log log k) time
ti
s i+1 si s i–1 Mod-8 Mod-7 Mod-5 Mod-3
Unit Unit Unit s i+1 si
Unit s i–1
(Impossiblerepresentation
Positional for positional does not
system with
support fixedcarry-free
totally digit set) addition; 3 3 3 2
s i+1 si s i–1
but it appears that RNS does allow Result
(a) Ideal single-stage carry-free. (b) Two-stage carry-free. (c) Single-stage with lookahead.
digitwise arithmetic
mod 8 mod 7 mod 5 mod 3