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SRI SIDDHARTHA INSTITUTE OF TECHNOLOGY, TUMKUR.

(An Autonomous Institution under Visvesvaraya Technological University, Belgaum.)

B.E., SEMESTER END EXAMINATIONS - AUGUST 2012

ML653 : DSP Architecture

TIME: 3.00 Hrs MAX MARKS: 100

1.a) With a neat block diagram, explain the scheme of a DSP system.
8M

b) An analog signal is given as x(t) = sin 480TTt + 3sin 720ut.

i) Determine the Nyquist sampling rate for x(t) 5M
ii) Determine the type and the cutoff frequency of the antialiasing filter.
c) Show that the variance of error is the same both in rounding and truncation error

OR
2.a) Let x(n)=[3,2,-2,0,7]. It is interpolated using an interpolation filter bk=[0.5, 1, 0.5],
6M
With interpolation factor 2. Determine the interpolated sequence.
b) For the FIR filter y(n)=(x(n)+x(n-1))/2. Determine a) system function b) frequency
response c) group delay. 6M

c) Explain with example, IEEE-754 single and double precision floating point
8M
representation format.

3.a) What are guard bits? Explain the structure of MAC unit with accumulator guard bits. 7M

b) Explain briefly the organization of on-chip memory in DSPs.

8M
c) Explain pipelined operation in DSP.
5M

OR
4.a) Compare the following:
i) Harvard architecture and Von Neumann architecture 8M
ii) Microcoded control and hard wired control
b) Explain the purpose of program sequencer.
6M

c) List the major architectural features used in a DSP to achieve high speed of
3M
program execution.
d) Consider MAC units whose inputs are 16-bit' numbers. If 256 products are to be
summed up in this MAC, how many guard bits should be provided for the 3M
accumulator to prevent overflow condition from occurring?

5.a) Explain the functional block diagram of barrel shifter unit of TMS320C54XX
processor. •
 b) Write a program to find the sum of series of signed numbers as specified below.
4M /i ' •

^ -.r- 6M
i=410/i
Assume AR1 as pointer to x(i) and AR2 as counter for the numbers.
c) Give the memory mapping of TMS320C54XX processor for
i) MP/MC=0, OVLY=1, DRC>M=0 4M
ii) MP/MC=1, OVLY=1, DROM-1
d) Differentiate between MAC and MACD instructions. 4M
OR
6.a) Explain the following addressing modes of TMS320C54XX processor
8M
i) Circular addressing ii) Direct addressing
b) Generate next two indices for a 16-pt DIT-FFT using Bit-reversed addressing mode
if the present index is ‘Ah’. 3M

c) Explain the pipeline operation of the following sequence of TMS320C54XX

instructions if the initial value of AR3 is 80 and values stored in memory location 80,
81, 82 are 1, 2 & 3.
5M
LD *AR3+, A
ADD *AR3+, A
STL A, *AR3+
d) Describe the operation of the following instruction
i) MPY *AR2-, *AR4+0, B 4M
ii) MAC *AR5+, *AR4-, A, B

7.a i) Determine the value of the following 16-bit numbers represented using the given
Q-notation 4400h as a Q0 number, Q15 number and Q7 number.
6M
ii) Represent each of the following as 16-bit numbers in the desired Q-notation,
0.3125 as a Q15 number, -0.3125 as a Q15 number and 3.125 as a Q7 number.
b) Write a TMS320C54XX subroutine to implement butterfly computation for 8-point
DIT-FFT algorithm. 8M

c) Explain Decimation filters. Give the implantation of digital decimation of a factor of 3

6M
& lowpass filter of length 5.
OR
8.a) w rite a program to multiply two Q 15 numbers. 8M

b) i) Derive the equation to implement a butterfly structure in DITFFT algorithm.

ii) How many add/subtract and multiply operations are needed to compute the
butterfly structure? 8M

iii) Determine the optimum scaling factor.

c) i) What minimum size FFT must be used to compute a DFT of 40 samples?
ii) How many stages are required for FFT computation?
4M
iii) How many butterflies are there per stage?
iv) How many butterflies are needed for the entire computation?

9.a) Describe a simple algorithm for heart rate determination using QRS interval,
10M

b) Explain encoding and decoding scheme for the PPM receiver. 10M
 OR
10.a) How is speech produced? Explain briefly the digital model of speech production,
8M
b) With a neat block diagram explain JPEG encoding and decoding.
12M
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