An Efficient Method for ECSM Characterization of

CMOS Inverter in Nanometer Range Technologies

I 2 I I'
Baljit Kaur , Sandeep Miryala , S.K.Manhas and Bulusu Anand
I
Indian Institute of Technology Roorkee, Roorkee, India
2
Politecnico di Torino, Torino
* anandfec @iitr.emet.in

Abstract-Accurate estimation of delay is a major challenge
in current nanometer regime using Non Linear Delay Model
(NLDM) due to issues such as parametric variation, nonlinear
capacitance value etc. It demands a large number of simula­
tions to be performed for getting the accurate delay values.
To partly solve this issue, people have started using Effective
Current Source Model (ECSM), which stores certain predefined
Threshold Crossing Point (TCP) of the output voltage waveform
with respect to different input transition time (TR) values and
load capacitance (Cl)' In this work, we propose an analytical
timing model relating 10% - 90% TCPs with Cl and TR values.
We also derive the relationship between the cell size and the
model coefficients. We also derive the region of validity of the
model in (TR, Cl) space and determine its relationship with cell
size. The proposed model is in good agreement with HSPICE
simulations with a maximum relative error of 2.5%. We verified
the proposed model with technology scaling. We use this model
and the relationships to reduce the number of simulations in
ECSM library characterization.
Index Terms-ECSM, transition time, load capacitance, CMOS
inverter, TCP
TR and Geff' ECSM stores the times at which the output
voltage waveform crosses certain predefined a% threshold
points while CCSM stores the output current values at different
threshold points [7]. Both the vendor models are equivalent
and one can de derived from other. Vendor CSMs use Lookup
Table (LUT) based format for characterization data.
ECSM characterization is a computationally tedious task.
In addition PVT variations and frequent device model updates
require lot of re-characterization. In this paper, we address
the problem of reducing the number of SPICE simulation in
ECSM library characterization shown in fig. 1. For this, we
used an approach of analytically modeling TCPs as a function
of Gl (= Geff) and TR values. We derived the region of
validity of our models in (TR, Gl) space. We then derived the
relationships of the model coefficients and regions of validity
with inverter size.
Input Slope Output Slope

-II
�TC"P P.
I. INTRODUCTION
TCP..
Scaling down of CMOS technologies below 65nm leads
the design process to face some challenges like short channel t=O t=T
effect, interconnect coupling, process variation etc. Beyond
65nm technology node, small variation in delay values due
to these effects can be also significant fraction of total delay.
Therefore, an accurate timing model is required to perform
(a) ECSM characterization overview
circuit analysis based on standard cell library characterization.
Recently, Current Source Models (CSM) have become im­
portant in standard cell characterization and Static Timing Input Transition Time (TR)
Analysis (STA) [1]. CSMs ideally support arbitrary input TRI • • • • • •
CI TR2 TRn
waveforms and output loads since their model parameters
are waveform and load independent [2]. One of the first CII Vll Vn Vnl
CSM models proposed by Croix et al. [3] is a Vi-Va (input
voltage, output voltage) based model in which a fixed output CI2 V1 2 V22 Vn2
•
capacitance is used. Later, Keller et al. [4] added a miller •

capacitance having a fixed value between input and output

node. Further a more complex CSM model proposed by Li "n Vln V2n Vnn
et al. [5] and Fatemi et al. [6], where Vi-Va based input, (b) LUT of ECSM vectors; For each set of C1 and
TR,the characterization data is a vector V
output and Miller capacitances are used. However vendor
CSMs presently impose some more constraints; they povide Figure J. ECSM characterization of CMOS inverter

CSM data for a set of input slew TR and effective capacitance

Geff· The Paper is organised as follows. In section II we described
Two popular vendor CSMs are Effective CSM (ECSM) our simulation setup. In Section III we derived our models. In
and Composite CSM (CCSM). For a given set of values of section IV we checked the validity of proposed models with
978-1-4673-4953-6/13/$3l.00 ©2013 IEEE 665 14th Int'l Symposium on Quality Electronic Design
respect to technology node. In section V we used these models
to reduce the number of simulations for ECSM characteriza­
tion.
II. SIMULATION SETUP
In this paper we used HSPICE simulations at 32nm and
22nm technology node. In these simulations we used BSIM
Predictive Technology device Models (PTM) 1 for the two
technologies. We keep pin ratio 2Wp/Wn=2.5 to obtain equal
inverter's (shown in fig. la) rise and fall transition times.
Therefore Wn can represent the size of inverter.
III. DERIVATION AND VALIDATION OF TCP MODEL
In this section, we assumed the rising input transition for
the derivation on TCPs model, similar analysis is valid for
falling input transition. For our derivation, we classified the
TCPs into two regions:
• Region I: when Vin 2: Vdd (for TCPs > TR )
t
t
• Region II: when Vin < Vdd (for TCPs < TR)
A. Derivation of the model in Region I
In this section we derived the relationships of tTCPs with
TR, Cl and size of inverter (Wn) for Region I. For this
derivation we used our earlier work in [8]. In [8], we derived
a relationship between a 50% delay and TR, Cl values. This
model is valid when Vout(TR) 2: Vdsat (Refer to fig. 2).
Where, Vdsat is the drain to source voltage (Vds) at which
velocity saturation ocuurs. In this derivation we had assumed
that the discharging NMOS operates either in saturation or
in linear region when Vout (�) which is TCP50% in
= of trb from Fig. 3 and validate (2) in Fig. 6. In following
the present case. We now observe that the same assumptions
are valid for all the TCPs under Region I if the constraint
Vout(TR) 2: Vdsat is followed. As a representative, we
derived model for tTCP60% shown in Fig. 2. This is because
tTCP60% > TR .
constants extracted by fitting model (1) into HSPICE simulated
data. The following observations has been made from the
semi-empirical model, as was done in [7] for 50% delay:
• Observation 1: Kl is a linear function of l/Wn
• Observation 2: K2 and K3 both are independent of Wn
The region of validity the 50% delay model in [8] is also
applicable for TCP60%:
t6.Q(TR) = STTR :s; (Cl + Cp)(Vdd - Vdsat) (2)
Where t6.Q(TR) is the output discharge from 0 to TR,
ST is a constant proportional to Wn, Cp is the inverter's
parasitic capacitance proportional to Wn and Vdd is the power
supply voltage3. Further we use the term trb, it denotes
the maximum value of TR which satisfy (2). Equation (2)
shows linear relationship between trb and Cl. The following
observations have made by fitting this linear relationship in
HSPICE simulated data:
• Observation 3: Slope of trb vs Cl plot is proportional to
l/Wn
• Observation 4: Intercept is a constant with Wn
Please note that though pinch-off based saturation of the
device was assumed in [7], the results are valid for a velocity
saturation based approach followed in this paper.
1) Verification of model: In this section we verified the
model in Region I using HSPICE simulated data for all the
TCPs (in our case, TCP60%, TCP50%, ....TCPlO%) which
have values smaller than Vdsat. Using curve fitting (as shown
in Fig. 3) on the simulated values of t(TCP60%), we extracted
the coefficients (Kl, K2, K3) of (1). We extract the values
figures we use the term TRin, it represents the 20-80% of TR
value.
tTCP versus TRin plot for different CI tTCP6O'J(, versus C1 plot for different T Rln
,O%
450
:
2� ��--���-r --��
400
/ ...
..

".:/
200
Ydd
350 ..
Vin Vi . .-
Q. 150
Veld -# •.
� •
.
l!(
Vout'TRL.. u 100 ..
J!(
CI.

VdsU- $ :�
i 200 ". -
•
/
50
•
.
.

150 . ... . �x)(

50 100 150 200 2� 300

:: '(It'M"
100
� 50
TRin(PS)
o�������-J
o 5 10 15 W � � 35 �
F
C,If )

'·out
Figure 3. Variation of tTCP60% with respect to TRin and Cl values

Figure 2. CMOS inverter with input and output waveforms for T CP60% Here, the points are the simulated data and the discontinuous
lines are the curve fitting of the proposed model. In Fig. 4 we
Therefore; testify Observation 1 that Kl is a linear function of l/Wn and
Fig. 5 confirms the validity of Observation 2 that K2 and K3
(1) both are independent of Wn. In Accordance with Observation
Here, t(TCP60%) defines the time at which output waveform 3, slope of trb versus Cl i.e. Strb varies linearly with l/Wn
crosses a voltage level of 0.6Vdd and K1, K2 and K3 are the as shown in Fig. 6.

I Obtained from htlp:llptm.asu.edul 3 We assume that the value of V dsat is very weakly dependent on the values
2Wp : PMOS device width; Wn : NMOS device width of V ds,as in [9]
 Verification of observation 1
Vcs =
Tn
� x t

(3)
Where Vcs is the gate source voltage of inverter's NMOS
device, t is the time axis and TR is the transition time of
input rising from 0 to Vdd. The velocity saturated current [9]
2 1,;LJ'--L--1....L..L.-.L..I
6 8 10 12 14 16 18 20 22
1
becomes;
1000*1fWn(nm' )

Figure 4. Variation of constant K 1 with Wn

(4)
K31slndependenlolWn Where K is the transconductance parameter and W repre­
sents the width of the CMOS inverter.
Let at the output tc,Q be the charge passing through the

+------+------+
NMOS device from to = ( )
� TR to h(refer to Fig. 7);
------ -+ -------+

D.Q r I dt (5)
lto
=

)
The value of � is kept much smaller than 1 in CMOS
(
Figure 5. Variation of constant K2 and K3 with Wn
technology. For our case it is 0.2.
t
r l Vdd.t _
dt
D.Q
(6)
(3
( 11th)
lto TR
=

300 I"'""T--....-r-T--."'" Variation of trb slope with Wn for TCP6I)%

26r-;r-r-"--r-....-�
250 24 Where, D.Q O.lVdd(Cl + Cp) and (3 KWn. Here, Cl
= =

22
20 and Cp are the load and parasitic capacitances, respectively.
., 200
.s
.s. 150 5 . , .
16
The integral in (6) resolves into a quadratic expression solving
which we obtain;
14
'2
100
'0
(7)
50 -l'-'--1....L..L-L..J...I
2 3 4 5 6 7 8 9 10 6
�6�.�'0�'2-'�4�'�6�'.�20��
C1(fF) 1000'1IWn(nm-1) Where,
Figure 6. Strb variation with Wn (8)

B. Derivation of the model in Region II

In this section we derived the relationships of tTCPs
and
K2 =
( 0. 2(C + Cp)
� ) (9)
with TR, Cl and size of inverter (Wn) for Region II when
Vout(TR) < Vdsat (Refer to Fig. 7). In this derivation we We obtained the values of Kl and K2 by fitting (7) on
assumed that the discharging NMOS operates in velocity HSPICE simulation data. Further, using (7) to (9), we observed
saturation when Vout(TR) < Vdsat. As a representative, we that;
derived model for tTCPgo% shown in Fig. 7. This is because • Observation 5: Kl is independent of Wn and Cl

tTCPgo% < TR . • Observation 6: K2 is proportional to VCi

• Observation 7: K2 is a linear function of j;J;

Vout Vin
Vdd Similar to subsection 3.1, the region of validity of proposed
O.9Vdd---------------- 1
model for Region II will be:
L
Vdsat--.---------.------ -- ---

I
Equation (10) shows a linear relationship between trb and
Cl. Therefore, Observations 3 and 4 will remain valid for this
proposed model in Region II. It has been observed that the
same assumptions are valid for all the TCPs under Region
gnd II since the constraint Vout(TR) < Vdsat is followed. We
represented the TCP90% for the verification of model in
Figure 7. CMOS inverter with input and output waveforms for T CPgo% Region II.
1) Verification of model : In this section we verified the
The input waveform (PWL) is assumed to be rising ramp proposed model in Region II using HSPICE simulated data for
with transition period TR; all the TCPs (in our case, TCPgo%, TCPso%,TCP70%) which
have values larger than Vdsat. As a representative, the model Verification of observation 1

verification is done for T C P90% with respect to different 10 ��-r����

TR, Cl and Wn values and extracted the coefficients Kl and

K2 of (7) through curve fitting. In Fig. 8 the variation of
tTCPgo% versus TRin for several values of Cl is shown.
///
/
tTCP versus TRin plot for different C1
//+
9O% 3 +//
90�� 2 '-'�--'-����
��--����
6 8 10 12 14 16 18 20 22
80
1000*1IWn(nm-')
70
� 60 (a) Variation of constant Kl with
') 50 Wn
J 40
30 K,isindopendenl0fWn
20
10����--����
o 10 20 30 40 50 60 70 80 90

TRin(ps) t---------J=--------+

Figure 8. Variation of tTCPgO% with respect to TRin ,;: 2

t---------J=--------;-
In Fig. 9, we verified Observation 5 that Kl is independent
>'5

of Cl and Wn. In Fig. 10, we confirmed the validity of 0.5 40 50 6()

,4�0 --t:-:
W,j,nm) Wn(nm)
70 80 90 100 110 120 130 140 150 " 60�"-!"::-:!::-
.. -t,,0;:-:,
!-::-,,-:!::
'
",:-:' :::- ,,,:':::
..�,,0
Observations 6 and 7 that constant K2 varies linearly with
(b) Variation of constant K2and K3 with Wn
VCl and respectively.
I*.
300 Variation of t,-b slope with Wn for TCPsO%
32��---r--.-.-�""
K,lslndependemolWn 30
250

"'
200
So
.f. 150

100

o. ----1----+---+--- �------+------ 50
2 3 4 5 6 7 8 9
0.2
10
C,(fF)
° 2�3�4�5�6�7�'�9�'" (C) Variation of
CI(fF) trb with Cl

Figure 9. Variation of constant Kl with Cl and Wn Figure 11. Verification of proposed model for Region 1 at 22nm technology
node
We derived the region of validity of (7) similar to the way
we did it for (1). Therefore, the region of validity of (7) would
be the same as that of (1) as shown in Fig. 9. We also verified the Observations 5-7 for TC P90% in
Region II and the results are shown in Fig. 12. Hence, the
K21s a linear function of "(/IJVn) proposed models are valid with the technology scaling.
K2 is proportional to -Ic,
8 cl=2f --+-­
cl::6f --+<--
7 a --
[J
,X"
cl=IOf lit: _ .
V. REDUCTION IN RUNTIME CHARACTERIZATION
� 6 ,><'
u;- ' ..
� 5 , ,l( In this section, we used the proposed model of Sections
'" 4 ,.x'
:.: ,, III to save the number of HSPICE simulations in ECSM (or
3
2
CCSM) characterization. Using model equations, within the
1.5 2 2.5 3 3.5 region of validity, we can get the values of all TCPs directly
-IC,(fF) � ':-: .0.� -':-: 0.0:-
9 �. 0 :-' 0:-L.,:-, 0:-L.':- 3-=-'0.'4:- -=-'0.15
2 :-':0.,7
without simulations. Hence, it saves runtime in characteriza­
v(lIIVn) (nm)

Figure 10. Variation of constant K2 with Cl and Wn

tion effort in standard cell characterization. On the other hand,
the TCP values which are out of validity bound in Region I and
II, can be calculated from HSPICE simulations. We have done
this characterization for CMOS inverter with minimum sized
IV. IMPACT OF TECHNOLOGY SCALING ON PROPOSED
inverter and repeat this for other sizes of inverter standard cell
MODELS
(2X and 3X). We generated the ECSM LUTs for all TCPs
In this section we verifed that the proposed models devel­ within typical ranges of TR and Cl values. We assumed the
oped in the previous section remains valid with scaling of maximum value of TR to be 250ps and Cl to be 36fF. Here,
technology node. For this, we verified the proposed models the LUT for TC P90% of Region II is shown in Table I which
using HSPICE simulated data at 22nm technology node. Fig. shows that the proposed models covers about half of the LUT's
11 shows the verification of Observations 1-3 for T CP60% as TR , Cl points and leads the reduction in HSPICE simulation
predicted in section II for Region I. for standard cell library chracterization. In the Table I, the
 K,isindependentolCI K,lslndependentolWn Table II
PERCENTAGE SAVING IN HSP ICE SIMULATION USING ECSM

Number of data points

in LUT obtained using:
TCPs Matrix % saving
Proposed HSPICE
---+----+---�--- �------�-------+ model
7x7 22 27 45(39)
o"
!:50-!
:--!:: ..I::-+.07 -!08 ::-!:-09 -:!Ol O:-:l::
l 0l -:!2l 0:-:,I:
03 ,L:- 4l 0�'50 T CP600/0 8x8 29 35 45(41)
9x9 36 45 44(41)
(a) Variation of constant Kl with C1 and Wn

K2 is proportional to ..fe, K21s a linear function of v(liJVn)

10 I"""'"T"""T""""T"" models to reduce runtime in characterization effort for standard

I ,,/ cl=2f --+-­
Wn=48nm x
'" ",x cl:6f - �-- cell library characterization while maintaing the accuracy. We
a cl=lOf - - . _ .
Wn=96nm I!l

' ,'" observed that standard cell library characterization can be done
/x ,"
..
X'
�_ 5 . · with a significantly lesser number of HSPICE simulations
/, � ... s ···., ...
$ .
. ,"'
'" ' .... (approximately 40% reduction). It is also in good agreement
N 4
..,
",,
.EJ •.
• • ••
with HSPICE simulated results having relative error of 2.5%
••
•

I I I I
or less. We ensured the validity of proposed model for different
1.5 2 2.5 3.5 sizes of CMOS inverter and also with technology scaling.
-Ie, (IF)
As a future work, we will derive a similar model for other
(b) Variation of constant K2 with Cl and Wn
logic gates, multi-stage standard cells and sequential circuit
Figure 12. Verification of proposed model for Region II at 22nm technology
elements. In future, the standard cell characterization would
node
be needed at several Process, Voltage and Temperature (PVT)
comers in deep sub-micron technologies. We will use our
symbol ' - ' shown for such TCPs values that can be extracted models to save the number of simulations to be done by
using HSPICE simulations only. HSPICE.

Table I
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V I. CONCLUSION AND FUTURE WORK

We have proposed the timing models which stores all the

TCPs within typical ranges of TR and Cl values. We used these