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    Sushma Patil CV

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    Ashok Chetan
    Sushma Patil is seeking a career opportunity to utilize her training and skills in electronics and communication. She has a Bachelor's degree in electronics and communication from B.L.D.E.A Engineering College with an aggregate of 65% and has completed professional training in design for testability. Her skills include VHDL, Verilog, and design for test. She has experience with projects involving scan insertion, ATPG pattern generation, and testing of digital cameras.

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    Sushma Patil CV

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    Ashok Chetan
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    Sushma Patil is seeking a career opportunity to utilize her training and skills in electronics and communication. She has a Bachelor's degree in electronics and communication from B.L.D.E.A Engineering College with an aggregate of 65% and has completed professional training in design for testability. Her skills include VHDL, Verilog, and design for test. She has experience with projects involving scan insertion, ATPG pattern generation, and testing of digital cameras.

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    Sushma Patil CV(2)

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    Sushma Patil is seeking a career opportunity to utilize her training and skills in electronics and communication. She has a Bachelor's degree in electronics and communication from B.L.D.E.A Engineering College with an aggregate of 65% and has completed professional training in design for testability. Her skills include VHDL, Verilog, and design for test. She has experience with projects involving scan insertion, ATPG pattern generation, and testing of digital cameras.

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    © All Rights Reserved
    Download as PDF, TXT or read online from Scribd
    Flag for inappropriate content
    Download as pdf or txt
    54 views2 pages

    Sushma Patil CV

    Uploaded by

    Ashok Chetan
    Sushma Patil is seeking a career opportunity to utilize her training and skills in electronics and communication. She has a Bachelor's degree in electronics and communication from B.L.D.E.A Engineering College with an aggregate of 65% and has completed professional training in design for testability. Her skills include VHDL, Verilog, and design for test. She has experience with projects involving scan insertion, ATPG pattern generation, and testing of digital cameras.

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    of 2

    SUSHMA PATIL

     C/o. S.D, Patil "Krushi Krupa"  24.04.1996  9035495558


    Building Shantineketan Colony
    sushmapatil96@gmail.com
    Bagalkot Road, V ijayapura
    586101

    PROFILE
    Secure a responsible career opportunity to fully utilize my training and skills, while
    making a significant contribution to the success of the company.

    EDUCATION
    2014 - 2018 B.L.D.E.A Engineering College V ijayapura
    Major:Electronics and Communication
    A ggregate:65%

    2012 - 2014 T ungal Independent PU College V ijayapura


    Major: PCMB
    A ggregate: 87%

    2011 - 2012 SECAB English Medium High School V ijayapura


    Major:Science and Mathematics
    A ggregate:95.84%

    PROFESSIONAL TRAINING
    09.2018 - 04.2019 Anora Semiconductor Labs Pvt. Ltd
    Position: Trainee Product Development Engineer.
    Completed the training in DFT on A TPG, CTS and basics of Python using Cadence, CTS Tester
    and Pycharm.

    03.2019 - 06.2019 ChipEdge T echnologies Pvt. Ltd


    Position: Trainee.
    Completed Design for Testability (DFT) training from ChipEdge Technologies Pvt. Ltd,
    Bangalore,using Synopsys tools.
    Course Outline: A SIC Flow, DFT fundamentals, SCA N Design, SCA N DRC, SCA N Insertion,
    Scan Compression, Boundary Scan/JTA G, Fault models, A TPG Coverage , A TPG for Struck-at
    and Transition fault models, Pattern simulations, Debug simulation failures, Logic BIST and
    Memory BIST Concepts.
    Tools Used in Training : DFT Compiler, Tetramax, V CS and BSD Compiler.

    SKILLS WORKSHOPS AND INTERNSHIP


     Beginner : Python, Cadence. A ttended workshop on IoT.
    A ttended workshop on Entrepreneurship.
     Intermediate : V HDL, V erilog.
    Undergone Internship at Nano Robotics Embed
     Operating Systems : Windows, Linux. Technologies on A dvanced Embedded System.
     Interests : Design for Test, Logic Design.
    PROJECTS
    Project Title: Scan insertion and DRC analysis.
    -Technology : 28nm
    -Design : Design with about 16k flops
    -No. of Clocks : 2
    -Tools Used : DFT Compiler
    -Role : Performed Scan insertion by defining constraints and different scan configurations. A nalyzed and fixed Scan
    DRC violations. Scan insertion with Compression logic.

    Project Title: A TPG pattern generation and simulation for Stuck-at and Transition fault models.
    -Technology : 28nm
    -Design : Design with about 11k flops
    - No. of Clocks : 2
    -Tools Used : Tetramax for A TPG and V CS for pattern simulation
    -Role : A TPG pattern generation for Stuck-at and Transition fault models. Generated Basic and fast sequential patterns
    using Tetramax. ZERO delay and SDF based Chain and Scan pattern simulations.

    Project Title: DTMF Chip.


    -Tools used: Cadence.
    -Description: Performed A TPG Scan.
    -My Role: A nalysed the scripts, debugged errors and broken scan chain warnings(TSV -384 and TSV -385).

    Project Title: Pattern Testing of Digital Cameras on CTS Tester.


    -Tools used: CTS Tester and V Mware.
    -Description: Testing Patterns given by the DFT engineers for various voltage corners and frequencies.
    -My Role: Worked on Singapore and San Diego Projects like- HA NA , KONA , Moorea and Poipu.

    Project Title: Smart street light and garbage monitoring system using Raspberry Pi. (Feburary to July 2018)
    -Recognition: This project was awarded as the best project by V isvesvaraya Technological University, Belagavi.
    -My Role: To involve in the design, interfacing and developing prototype of the entire project.

    PERSONALITY
     Communicative and friendly.  Punctual, Creative and Organised.
     Responsible and good team player.  Motivating and goal oriented.

    LANGUAGES
    English     
    Hindi    
    Kannada     

    HOBBY

     
    Badminton Listening
    Music

    I agree that my personal data will be processed in order to recruit for the position I am applying for.

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