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UCC25600 8-Pin High-Performance Resonant Mode Controller: 1 Features 3 Description
UCC25600 8-Pin High-Performance Resonant Mode Controller: 1 Features 3 Description
UCC25600 8-Pin High-Performance Resonant Mode Controller: 1 Features 3 Description
UCC25600
SLUS846C – SEPTEMBER 2008 – REVISED JUNE 2015
Device Information(1)
PART NUMBER PACKAGE BODY SIZE (NOM)
UCC25600 SOIC (8) 3.91 mm × 4.90 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
UCC25600
VS
8 GD1 OC 3
5 GD2 RT 2
7 VCC DT 1
6 GND SS 4
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
UCC25600
SLUS846C – SEPTEMBER 2008 – REVISED JUNE 2015 www.ti.com
Table of Contents
1 Features .................................................................. 1 7.3 Feature Description................................................. 10
2 Applications ........................................................... 1 7.4 Device Functional Modes........................................ 13
3 Description ............................................................. 1 8 Application and Implementation ........................ 14
4 Revision History..................................................... 2 8.1 Application Information............................................ 14
8.2 Typical Application ................................................. 18
5 Pin Configuration and Functions ......................... 3
6 Specifications......................................................... 4 9 Power Supply Recommendations...................... 22
6.1 Absolute Maximum Ratings ...................................... 4 10 Layout................................................................... 22
6.2 ESD Ratings ............................................................ 4 10.1 Layout Guidelines ................................................. 22
6.3 Recommended Operating Conditions....................... 4 10.2 Layout Example .................................................... 23
6.4 Thermal Information .................................................. 4 11 Device and Documentation Support ................. 24
6.5 Electrical Characteristics........................................... 5 11.1 Community Resources.......................................... 24
6.6 Typical Characteristics .............................................. 7 11.2 Trademarks ........................................................... 24
7 Detailed Description .............................................. 9 11.3 Electrostatic Discharge Caution ............................ 24
7.1 Overview ................................................................... 9 11.4 Glossary ................................................................ 24
7.2 Functional Block Diagram ......................................... 9 12 Mechanical, Packaging, and Orderable
Information ........................................................... 24
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
• Added ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation
section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and
Mechanical, Packaging, and Orderable Information section. ................................................................................................ 1
D Package
8-Pin SOIC
Top View
DT 1 8 GD1
RT 2 7 VCC
OC 3 6 GND
SS 4 5 GD2
6 Specifications
6.1 Absolute Maximum Ratings
(1)
over operating free-air temperature range (unless otherwise noted)
MIN MAX UNIT
Supply voltage, VCC 22 V
Voltage, GD1, GD2 –0.5 VCC + 0.5 V
Gate drive current – continuous, GD1, GD2 ±25 mA
Current, RT –5 mA
Current, DT –0.7 mA
Lead temperature (10 seconds) 260 °C
Operating junction temperature, TJ –40 125 °C
Storage temperature, Tstg –65 150 °C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
1 350
0.9
Ivcc - Bias Supply Current - mA
0.7 250
0.6
200
0.5
150
0.4
0.3
100
0.2 OC Open -40 °C
50 25 °C
0.1
125 °C
0 0
6 7 8 9 10 11 12 13 14 0 1 2 3 4 5
Vvcc - Bias Supply Voltage - V IRT - RT Current - mA
Figure 1. Bias Supply Current vs Bias Supply Voltage Figure 2. Switching Frequency vs RT Current
1000 1000
900 - 40 °C 900
25 °C
800 800
125 °C
700
DT - Dead Time -
DT - Dead Time -
700
600 600
500 500
400 400
300 300
200 200
-40 °C
100 100 25 °C
125 °C
0 0
0 100 200 300 400 500 600 700 0 5 10 15 20 25 30 35 40 45
IDT - DT Current - uA RDT - DT Resistor - kOhm
Gate Drive
14 1.4 14 0.7
Voltage
Gate Drive Sink
12 Current 1.2 12 0.6
Gate Drive Voltage - V
Gate Drive Current - A
Gate Drive Voltage - V
4 0.4 4 0.2
2 0.2 2 0.1
0 0 0 0
-2 -0.2 -2 -0.1
0 100 200 300 400 500 600 0 200 400 600 800 1000
Time - ns Time - ns
Figure 5. Gate Drive Falling, VCC = 15 V Figure 6. Gate Drive Rising, VCC = 15 V
UVLO Threshold -
200
150 10
100
50
0 8
-60 -40 -20 0 20 40 60 80 100 120 140 -60 -40 -20 0 20 40 60 80 100 120 140
Tj - Junction Temperature - °C Tj - Junction Temperature - °C
1
18
0.5
17
16 0
-60 -40 -20 0 20 40 60 80 100 120 140 -60 -40 -20 0 20 40 60 80 100 120 140
Tj - Junction Temperature - °C Tj - Junction Temperature - °C
Figure 9. VCC Overvoltage Threshold vs Temperature Figure 10. Overcurrent Threshold vs Temperature
100
80
On Time Mismatch - ns
60
40
20
0
0 50 100 150 200 250 300 350
Switching Frequency - kHz
7 Detailed Description
7.1 Overview
Due to high power density and high efficiency requirements, LLC topology is employed in many applications. The
LLC resonant converter has many unique characteristics and improvements compared with hard-switch bridge
topology and phase-shift full bridge. For example, LLC has a simple structure, and could achieve primary
MOSFET zero voltage switching (ZVS) and the secondary rectifier zero current switching (ZCS) from no load to
full load.
The UCC25600 device is an LLC-resonant half-bridge controller which integrates built-in, state-of-the-art
efficiency boost features with high-level protection features to provide cost-effective solutions.
2.25V
T +
J TSD 20V
160oC/140oC OV
Thermal 18V
DT 1 +
ShutDown
2.5V 7 VCC
Feed RT
2
back
Ic
OSC 8 GD1
Vss
GD_Stop 6 GND
6V
5uA 170uA
OC
OC + 3
Vss 1V
SS
4
OC_latch +
Css + 2V
1.2V/1V
FAULT
SET
S Q
R CLR
Q
4V
1.2V
Vss
Gate driver
t ss _ delay t ss
To prevent a long delay between the ON command and appearance of a gate driver signal, the SS pin current is
set as two different levels. When the SS pin voltage is below 1.2 V, its output current is 175 μA. This high current
could charge the soft-start pin capacitor to 1.2 V in a short period of time, and reduce the time delay. This time
delay can be calculated using following equation:
1.2V
tSS _ delay = CSS
175m A
(1)
Lr
From half bridge
TR
Lm
Cs
To OC D2 Rs
Cp Rp D1 Cr
The general concept of this sensing method is that the ac voltage across the resonant capacitor is proportional to
load current.
According to the FHA model, peak voltage of the ac component on the resonant capacitor can be calculated as:
4 jf L Q + 1
VCr _ pk = nVo n n2 e
p f n Ln
(4)
Therefore, the resonant capacitor voltage reaches its maximum value at the minimum switching frequency and
maximum load. According to this equation, the current sensing network components can be calculated. Due to
the nature of FHA, the final circuit parameters need to be verified through actual hardware test.
2
Transfer ac voltage across resonant VCr _ pk (max )
RS
capacitor into current source Rs =
2 PRs (max)
(5)
10
CS Blocking dc voltage on resonant capacitor Cs =
Rs f min (6)
Rs
RP Load resistor of the current source Rp = p
VCr _ pk (max )
(7)
10
CP Filter capacitor Cp =
R p f min (8)
7.4.2 VCC
When VCC becomes above 10.5 V, the device is enabled and, after all fault conditions are cleared, the gate
driver starts with soft start. When VCC drops below 9.5 V, the device enters the UVLO protection mode and both
gate drivers are actively pulled low. When VCC rises above 20 V, the device enters VCC overvoltage protection
mode and the device is disabled with both gate drivers actively pulled low. The VCC overvoltage protection will
recover with soft start when the VCC voltage returns below 18 V.
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
Cr Lr n:1:1
Lm
The LLC resonant converter is based on the series resonant converter (SRC). By using the transformer
magnetizing inductor, zero-voltage switching can be achieved over a wide range of input voltage and load. As a
result of multiple resonances, zero-voltage switching can be maintained even when the switching frequency is
higher or lower than resonant frequency. This simplifies the converter design to avoid the zero-current switching
region which can lead to system damage. The converter achieves the best efficiency when operated close to its
resonant frequency at a nominal input voltage. As the switching frequency is lowered, the voltage gain is
significantly increased. This allows the converter to maintain regulation when the input voltage falls low. These
features make the converter ideally suited to operate from the output of a high-voltage, boost PFC pre-regulator,
allowing it to hold up through brief periods of ac line-voltage dropout.
Due to the nature of resonant converter, all the voltages and currents on the resonant components are
approximately sinusoidal. The gain characteristic of the LLC resonant converter is analyzed based on the first
harmonic approximation (FHA), which means all the voltages and currents are treated as a sinusoidal shape with
the frequency the same as the switching frequency.
According to the operation principle of the converter, the LLC resonant converter can be drawn as the equivalent
circuit shown in Figure 15.
Cr Lr
Vge Lm Re Voe
Vo 1 Lr / Cr f Lm
M= f0 = Qe =
VDC / 2 2p Lr Cr fn = Ln =
Re f0 Lr
(14) (15)
(11) (12) (13)
Following the definitions in Table 3, the converter gain at different switching frequencies can be written as:
Ln ´ fn2
M=
é(Ln + 1) ´ fn2 - 1ù + j é(fn2 - 1) ´ fn ´ Qe ´ Ln ù
ë û ë û (16)
Because of the FHA, this gain equation is an approximation. When the switching frequency moves away from the
resonant frequency, the error becomes larger. However, this equation can be used as a design tool. The final
results need to be verified by the time-based simulation or hardware test.
From Equation 16, when the switching frequency is equal to the resonant frequency, fn = 1 and converter voltage
gain is equal to 1. Converter gain at different loads and inductor ratio conditions are shown in Figure 16 through
Figure 19.
2 2
Qe = 0.1 Qe = 0.1
Qe = 0.2 Qe = 0.2
Qe = 0.5 Qe = 0.5
Qe = 1 Qe = 1
1.5 Qe = 2 1.5 Qe = 2
Qe = 5 Qe = 5
M M
1 1
0.5 0.5
0 0
0.1 0.5 1 1.5 2 0.1 0.5 1 1.5 2
fn fn
Figure 16. M vs fN Figure 17. M vs fN
2 2
Qe = 0.1 Qe = 0.1
Qe = 0.2 Qe = 0.2
Qe = 0.5 Qe = 0.5
Qe = 1 Qe = 1
1.5 Qe = 2 1.5 Qe = 2
Qe = 5 Qe = 5
M M
1 1
0.5 0.5
0 0
0.1 0.5 1 1.5 2 0.1 0.5 1 1.5 2
fn fn
Figure 18. M vs fN Figure 19. M vs fN
Based on its theory of operation, the LLC resonant converter is controlled through pulse frequency modulation
(PFM). The output voltage is regulated by adjusting the switching frequency according to the input and output
conditions. Optimal efficiency is achieved at the nominal input voltage by setting the switching frequency close to
the resonant frequency. When the input voltage drops low, the switching frequency is decreased to boost the
gain and maintain regulation.
The UCC25600 resonant half-bridge controller uses variable switching frequency control to adjust the resonant
tank impedance and regulate output voltage. This 8-pin package device integrates the critical functions for
optimizing the system performance while greatly simplifying the design and layout.
8.1.3 Oscillator
With variable switching frequency control, UCC25600 relies on the internal oscillator to vary the switching
frequency. The oscillator is controlled by the current flowing out of the RT pin. Except during soft start, the
relationship between the gate signal frequency and the current flowing out of the RT pin can be represented as:
1 1
fS = » I RT ´ 83Hz / m A
2 6 ns ´ 1 A
+ 150ns
I RT
(18)
Because the switching frequency is proportional to the current, by limiting the maximum and minimum current
flowing out of the RT pin, the minimum and maximum switching frequency of the converter could be easily
limited. As shown in Figure 20, putting a resistor from the RT pin to ground limits the minimum current and
putting a resistor in series with the opto-coupler limits the maximum current.
UCC25600
Maximum
frequency limiting
R1 RT
Minimum
R2
frequency limiting
æ 1 1 ö
I f max = 2.5V ç + ÷
è R1 R2 ø (21)
2.5V
I f min =
R2
(22)
12V@25A
+
+ +
11V
12V Bias
(External)
+
+ +
1
fr =
2p ´ Lr ´ Cr (29)
(g) Combine the above two equations:
Lr = 55µH (30)
(h) Calculate Lm:
Lm = Ln × Lr = 275 µH (31)
2. Calculate Rdt. In the UCC25600, dead time can be adjusted through a single resistor from DT pin to ground.
With an internal 2.25-V voltage reference, the current flow through the resistor sets the dead time.
td = 20ns + Rdt × 24ns/kΩ
where
• td = 300 ns
• Rdt = 11.7 kΩ (32)
3. Calculate CSS. Refer to Soft Start for more details.
tss = 25 ms (33)
tss = 2.8 V/5 µA × Css (34)
Css = 44.6 nF (35)
4. A 47nF capacitor is selected. Calculate RT1 and RT2. Refer to Oscillator for more details. RT1 and RT2 are
used to limit maximum switching frequency and minimum switching frequency. RT1 and RT2 can be
calculated based on following equations:
Ifmax = 6 ns/(1/2fmax - 150 ns) (36)
Ifmin = 6 ns/(1/2fmin - 150 ns) (37)
Ifmax = 2.5 V(1/RT1 + 1/RT2) (38)
Ifmin = 2.5 V/RT2 (39)
5. Combine the four equations above:
RT1 = 511Ω (40)
RT2 = 2.37 kΩ (41)
6. Calculate Rs, Cs, Rp, and Cp. Refer to Overcurrent Protection for more details.
Rs = 300 kΩ (42)
Cs = 22 pF (43)
Rp = 4.99 kΩ (44)
Cp = 1 µF (45)
60 180
45 135
P h as e (D eg )
30 90
G a i n (d B )
15 45
0 0
-15 -45
-30 -90
-45 -135
Gain Phase
-60 -180
10 100 1000 10000 100000 1000000
Frequency (H z)
Figure 23. Typical Output Voltage Turn On (TP15) Figure 24. Full System Loop Compensation (TP19 and
TP21)
Figure 25. Typical Soft-Start Waveform Figure 26. Typical Resonant Tank Current and Resonant
Capacitor Voltage
10 Layout
11.2 Trademarks
E2E is a trademark of Texas Instruments.
is a registered trademark of ~Texas Iinstruments.
All other trademarks are the property of their respective owners.
11.3 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
11.4 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
www.ti.com 29-Sep-2017
PACKAGING INFORMATION
Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) (6) (3) (4/5)
UCC25600D ACTIVE SOIC D 8 75 Green (RoHS CU NIPDAU Level-2-260C-1 YEAR -40 to 125 25600
& no Sb/Br)
UCC25600DR ACTIVE SOIC D 8 2500 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 125 25600
& no Sb/Br)
UCC25600DRG4 ACTIVE SOIC D 8 2500 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 125 25600
& no Sb/Br)
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com 29-Sep-2017
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com 9-Aug-2018
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com 9-Aug-2018
Pack Materials-Page 2
PACKAGE OUTLINE
D0008A SCALE 2.800
SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT
SEATING PLANE
.228-.244 TYP
[5.80-6.19]
.004 [0.1] C
A PIN 1 ID AREA
6X .050
[1.27]
8
1
.189-.197 2X
[4.81-5.00] .150
NOTE 3 [3.81]
4X (0 -15 )
4
5
8X .012-.020
B .150-.157 [0.31-0.51]
.069 MAX
[3.81-3.98] .010 [0.25] C A B [1.75]
NOTE 4
.005-.010 TYP
[0.13-0.25]
4X (0 -15 )
SEE DETAIL A
.010
[0.25]
.004-.010
0 -8 [0.11-0.25]
.016-.050
[0.41-1.27] DETAIL A
(.041) TYPICAL
[1.04]
4214825/C 02/2019
NOTES:
1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches.
Dimensioning and tolerancing per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed .006 [0.15] per side.
4. This dimension does not include interlead flash.
5. Reference JEDEC registration MS-012, variation AA.
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EXAMPLE BOARD LAYOUT
D0008A SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT
8X (.061 )
[1.55]
SYMM SEE
DETAILS
1
8
8X (.024)
[0.6] SYMM
(R.002 ) TYP
[0.05]
5
4
6X (.050 )
[1.27]
(.213)
[5.4]
EXPOSED
METAL EXPOSED
METAL
.0028 MAX .0028 MIN
[0.07] [0.07]
ALL AROUND ALL AROUND
4214825/C 02/2019
NOTES: (continued)
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EXAMPLE STENCIL DESIGN
D0008A SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT
8X (.061 )
[1.55] SYMM
1
8
8X (.024)
[0.6] SYMM
(R.002 ) TYP
5 [0.05]
4
6X (.050 )
[1.27]
(.213)
[5.4]
4214825/C 02/2019
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
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