Tape out Steps.

1) Do literature survey. Finalize the architecture / circuit, specifications etc.

2) Draw block diagram of your system/circuit.
3) Do pin out and area estimate.
4) Implement each block (schematic and layout). See whether you are meeting block level
specs, if any.
5) Do pin out and area estimate, again.
6) Implement top level schematic. In the test bench add bond wire model and do
simulations. Check whether you are meeting the specs. (Note: Complete the top level
schematic at least by one month from tape out date.)
7) Top level layout: interconnect all the blocks, do shielding of critical signals, put guard
rings.
8) Compare pre and post layout results.
9) Add De Cap’s, ESD.
10) Put dummy blocking layer and slot blocking layer over required area. If any ARC errors,
drop antenna diodes at the required location.
11) Stream out the GDS file.

Tape out Checklist

1. Please check that you are using latest design kits and tool versions.
2. Perform LVS, DRC, Antenna violations and Density checks. Do an ERC to ensure that you
have not put any structure in an opposite config: PTAP to VDD or NTAP to ground and so
on and do not leave any taps floating. Minimize ERC errors.
3. Check for Off grid errors. Keep xsnap ; ysanp spacing : 5nm 5nm
4. Please check for the presence of pad opening layer (PASV_RDL) on all the pads.
5. Put ESD diodes on all DC pads (leave RF pads alone).
6. Leave minimum 10um clearance from the die edge for all the active circuits. This has to
be addressed at the top level (container) cell.
7. If wafer probing, verify that there is enough clearance between North – South and East
– West pads so that landing will not be a problem.
8. If packaging, look at critical RF/Analog signal routing from package edge to board edge.
Make modifications in top level pin arrangement in silicon, if necessary.
9. Check all pins that carry high currents and ensure that the on-chip metals/vias are
sufficient in width/number to support the currents. Add multiple parallel paths from
pads for VDD, GND and RF In to reduce the resistance.

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10. Run a Transient simulation on your circuit using your test bench and PEX extracted
netlist. Provide a 1-tone input at an RF frequency (usually highest freq. of design) and
make sure that you see a proper output. Look at all the bias pins and make sure that
they have reasonable bias voltages (between 0 & VDD) and currents.
11. Add dummy blocking layers around your critical circuit components or you can put your
own Dummies.
12. Add slot blocking on the signal metal traces which are more than 5um wide but less
than 10um wide. Any signal trace more than 10um will be slotted irrespective whether a
slot blocking layer is added or not.
13. Do shielding of critical signals.
14. In your top level test bench ensure that you have added bond wire parasitics and
perform simulations.
15. Please do corner simulations. i.e SS, FF, TT, SF, and FS
16. Please check the test equipment’s operational ranges. So that it doesn’t affect your
testing.
17. Please check the Pad pitch / probe pitch and ensure it is maintained in the layout.
Wedge probe is not symmetric. You cannot use same probe for north south or east west
orientation.
18. Circuits which require choking on DC biases and supply should be simulated with
realistic values. Remember DA v.1
19. Process has same cap density for both MOM and MIM caps.
20. Please add DECAPs and also check the results of design after adding DECAP. Use MOS
caps if needed.
21. Inductor usage : Check for Q degradation : 10 to 4
22. Check for variation in differential circuits. Do Monte Carlo simulations
23. If you have drivers on chip then check whether you will require an external buffer or
not.
24. If possible try to pin out signals from individual blocks for better testability,
controllability and observability.
25. Try to have Serial Bus Interface / Scan for testing and controlling. Add some default
state in chip when using scan so that chip can be tested even when scan fails.
26. Once you stream out GDS, stream in same GDS and do an LVS check on your streamed
in layout with respect to the schematic whose layout was streamed out. Also check for
missing / blinking vias, transistors etc.
27. Check PIPO.log file for half paths in routing.
28. Never done but circuit should be checked up for latch up issues.
29. In 65nm technology there are five different types of PEX extraction. If possible do
different extractions and check for variations in results.