Wideband Millimeter-Wave Open

Experimentation Platform
Jesús O. Lacruz, Diego Juara, Joerg Widmer
IMDEA Networks Institute

Highlights Phased Array Antennas

• Flexible transceiver design using a single FPGA,
simple and modular, with comparatively low cost.
• More than 2GHz bandwidth, compatible with 5G
and beyond and 802.11ad/ay WLAN.
• Integrated with 60GHz RF frontend with phased
array (16+16 antenna elements) and 6 bit phase- Example of four pre-defined beam patterns in the phased array antennas

shift resolution for beamforming

Preliminary Experiments Results
• Up to 40m communication range for IEEE 802.11ad
Example setup:
MCS12 single carrier frames (expected max. range
around 100m for lower MCSs). • 20m LOS communication channel
• Open-source hardware blocks compatible with • Transmission of fully standard compliant Single
scaled-down bandwidth systems (e.g., USRP X310). Carrier IEEE 802.11ad frames using MCS 1 to MCS 12
Hardware Experimentation Platform • Signal captured with the FPGA system and decoded
offline using a MATLAB-based baseband receiver
• 60 GHz RF frontend model.
• 2.16GHz RF bandwidth
• 16+16 phased array antenna

MCS 10
MCS 1

MCS 11
MCS 2

MCS 4

MCS 5

MCS 6

MCS 7

MCS 8
MCS 3

MCS 12
MCS 9
Received Signal

• 2-channel baseband
• Packet detection
clock board
• Freq. offset estimation
and correction
• Symbol sync.
• Boundary detection

Packet Detector Output Boundary Detector

• Core i7 processor board • FPGA board + AD/DA

converters
• FPGA board with high-speed
PCIe connection to processor • 20GB of DDR memory
• 1.5 million logic blocks • Channel estimation
• Channel equalization
• Fine frame sync.
• Phase noise reduction
• Demapping
Baseband Transceiver Architecture • Channel decoding

Channel Impulse Response

DDR4 ADC CLK
AMC599 FPGA+AD/DA 8GB (1,76 GHz) STF CEF HEADER DATA BFT
FPGA
ADC_I 802.11ad Single Carrier Frame Fields
DDR Rx I/Q Signals
Preamble
Write
Processing ADC_Q
Core
Successfully transmission,
reception and offline decoding
DDR over a 20m LOS link for up to
DAC_I IEEE 802.11ad MCS12 frames
Read Tx Blocks
PCIe to
Core Tx I/Q Signals
AXI DAC_Q

Constellations of the received data symbols for MCS 6 (left)

and MCS 12 (right) over a 20m outdoor LOS channel
DDR4 DAC CLK
8GB (3,52 GHz)
On-going Work
PCIe AMC726 • Step-by-step translation of the receiver processing
Processor Board blocks to the FPGA.
Phased Array Antennas • Test a scaled-down system with reduced
bandwidth in USRP X310 SDR devices (GNU-Radio +
• Antenna Wave Vector with 64 beam patterns
RFNoC framework).
(selectable/updated through SPI from the FPGA)
• Extend the platform to low-order MIMO systems
• Full 2.16GHz IEEE 802.11ad channel bandwidth (multiple AMC599 boards in the same chassis).
• 6 bit resolution for phase, 4 bits for amplitude • Exploit (limited) full-duplex capability for radar
© IMDEA Networks Institute