Department Department of Electrical Engineering Dept.

Code EE
Course Title Digital Logic Design Course Code EE 227
Pre-requisite(s) - Credit Hours 3+1

Course To introduce the classical logic design techniques for analysis and design of
Objective combinational and sequential circuits.

No. Assigned Program Learning Outcome (PLO) Level Tool

An ability to design solutions for complex engineering problems and design
systems, components or processes that meet specified needs with appropriate
3 R F
consideration for public health and safety, cultural, societal, and environmental
considerations.
I = Introduction, R = Reinforcement

E = Evaluation, A = Assignment, Q = Quiz, M = Midterm, F=Final, L = Lab, P = Project, W = Written

Report.

Taxonomy
No. Course Learning Outcome (CLO) Statements Assessment PLO
Levels
Tools
Identify and explain fundamental concepts of digital logic
1 design including basic and universal gates, number base M C2 3
conversions and arithmetic operations
Apply Boolean Algebra & Karnaugh Methods to Optimize
2 M C3 3
logic circuits
Analyze the digital functional blocks: Encoders/Decoders,
3 Multiplexers/Demultiplexer, Exclusive-ORs, Comparators, M, F C4 3
and Arithmetic functional blocks, AOI for different I/O
Design the combinational circuits by using digital functional
4 M, F C5 3
blocks
Analyze the sequential circuits by using different memory
5 F C4 3
blocks: Latches and Flipflops
6 Design the sequential circuits by using latches and flipflops F C5 3
7 Analyze the various types of counters & registers F C4 3
8 Design the various types of counters & registers F C5 3
Analyze and derive equations for the implementation of
9 Boolean functions using ROM, PLAs and PALs and design F C4 3
memory using RAM ICs