EC601-Digital System Design

Project Report
ELECTRONIC VOTING MACHINE

Submitted to: Submitted by:

Dr. Dhaval Shah Utkarsh Agrawal (16bec111)
Kamya Ahuja (16bec113)
INTRODUCTION TO PROBLEM STATEMENT
Electronic voting machine is a device used by the voters to cast vote to their
respective parties. When button corresponding to the party is pressed, the vote
count will increase and the machine ensures that one voter can cast only one vote.

The project aims to build an Electronic Voting Machine which takes three parties
into consideration and counts the votes of these parties and display the count of
these votes on seven segment display. Quartus version 13.0 is the synthesis tool
used and the code for this project is written in Verilog HDL.

WORKING METHODOLOGY
The voting machine is powered up using a switch “master_enable” .There is
another switch “en “ which allows the voters to cast their votes to the respective
parties, this enable is reset once the voter has cast his/ her vote thus indicating that
he can’t vote more than once. “en_led” is used to indicate whether the voter can
vote or not. There are three buttons for three different parties and three
corresponding LEDs for each for example LED_1 glows if party_1 gets the vote. If
the voter presses two buttons at a time corresponding to two parties, invalid LED
glows indicating invalid voting. The count is incremented upon the casting of
votes. The count of votes (maxmum:15) for each party is displayed on a pair of
seven segment display one indicating the LSB of votes and the other indicating the
MSB of votes ,So here six “seven segment displays” are used .

FLOWCHART OF CODE
It shows how the flow of code procedure and what processes are done at each step.
 At clock signal
the process
starts.

If either of the
If both enable
enable inputs is
inputs are ON
zero

Check the
Turn ON enable Turn ON invalid
button pressed
led led
by the user

If more than
If only one key is
one keys are
pressed
pressed

Increment the Turn ON the Turn ON invalid

specific counter respective led led

Display the
count on seven
segment
RTL View

TTL View
WAVEFORM

CONCLUSION
This project helped us clear various concepts of Verilog including the
concepts of usage of push buttons, implementing behavior modelling
with the help of switch case, using clock to synchronize all the devices
and switches, etc. This project also taught us to use two seven segment
displays together to display a two digit number.
REFERENCES
1. S. Palnitkar, Verilog HDL: a guide to digital design and synthesis. Taipei, Taiwan: Sun/Pearson,
2009.
APPENDIX
Code [Verilog HDL]
module elect ( b1, b2, b3, led, master_enable, en, en_led, inval_led, s1, s2, s3, s4, s5, s6, clk );

input b1, b2, b3;

input master_enable;
input en, clk;

output reg en_led, inval_led;

output reg[2:0] led;
output [6:0] s1, s2, s3, s4, s5, s6;

reg [3:0] ctr1, ctr2, ctr3;

reg enable;

initial
begin
ctr1 = 4'b0;
ctr2 = 4'b0;
ctr3 = 4'b0;
enable = 1'b0;
en_led = 1'b0;
led = 3'b000;
inval_led = 1'b0;
end

seven_seg seg1 (ctr1, s1 ,s2);

seven_seg seg2 (ctr2, s3 ,s4);
seven_seg seg3 (ctr3, s5 ,s6);

always@(posedge clk) begin

if (master_enable && en) begin

enable = 1'b1;
en_led = 1'b1;
led = 3'b000;
inval_led = 1'b0;
end

else begin
enable = 1'b0;
en_led = 1'b0;
 led = 3'b000;
inval_led = 1'b0;
end

if (b2 && b3 && ~b1 && enable) begin

ctr1 = ctr1 + 4'b1;
led[2:0] = 3'b001;
en_led = 1'b0;
enable = 1'b0;
end

else if (b1 && b3 && ~b2 && enable) begin

ctr2 = ctr2 + 4'b1;
led[2:0] = 3'b010;
en_led = 1'b0;
enable = 1'b0;
end

else if (b1 && b2 && ~b3 && enable) begin

ctr3 = ctr3 + 4'b1;
led[2:0] = 3'b100;
en_led = 1'b0;
enable = 1'b0;
end

else if (b1 && b2 && b3 && enable)

inval_led = 1'b0;
else
inval_led = 1'b1;
end
endmodule

module seven_seg(binary, seg1, seg2);

input [3:0] binary;

output reg [6:0] seg1,seg2;

always @(binary) begin

case (binary) //case statement
0 : begin
seg1 = 7'b1000000;
seg2 = 7'b1000000;
end
1 : begin
seg1 = 7'b1111001;
seg2 = 7'b1000000;
end
2 : begin
seg1 = 7'b0100100;
seg2 = 7'b1000000;
end
3 :begin
seg1 = 7'b0110000;
seg2 = 7'b1000000;
end
4 : begin
seg1 = 7'b0011001;
seg2 = 7'b1000000;
end
5 : begin
seg1 = 7'b0010010;
seg2 = 7'b1000000;
end
6 : begin
seg1 = 7'b0000010;
seg2 = 7'b1000000;
end
7 : begin
seg1 = 7'b1111000;
seg2 = 7'b1000000;
end
8 : begin
seg1 = 7'b0000000;
seg2 = 7'b1000000;
end
9 : begin
seg1 = 7'b0010000;
seg2 = 7'b1000000;
end
10 : begin
seg1 = 7'b1000000;
seg2 = 7'b1111001;
end
11 : begin
seg1 = 7'b1111001;
seg2 = 7'b1111001;
end
 12 : begin
seg1 = 7'b0100100;
seg2 = 7'b1111001;
end
13 : begin
seg1 = 7'b0110000;
seg2 = 7'b1111001;
end
14 : begin
seg1 = 7'b0011001;
seg2 = 7'b1111001;
end
15 : begin
seg1 = 7'b0010010;
seg2 = 7'b1111001;
end
default : begin
seg1 = 7'b1111111;
seg2 = 7'b1111111;
end
endcase
end
endmodule