Low-Power Ic Design: Outline: System-On-Chip Design (For Es)

SYSTEM-ON-CHIP DESIGN 2
LOW-POWER IC DESIGN September 18, 2018

September 18, 2018
LOW-POWER IC DESIGN: OUTLINE
• Sources of power dissipation
• Signal transition probabilities
SYSTEM-ON-CHIP DESIGN (FOR ES) • Power simulation and estimation techniques
LOW-POWER IC DESIGN • RT-level low-power design: with variable and constant voltage
• Clock and power gating
• Approximate computing
• Further reading
© Sabih H. Gerez, University of Twente, The Netherlands
SYSTEM-ON-CHIP DESIGN 3 SYSTEM-ON-CHIP DESIGN 4

LOW-POWER IC DESIGN September 18, 2018 LOW-POWER IC DESIGN September 18, 2018
ACKNOWLEDGEMENT SOURCES OF POWER DISSIPATION

• Most material in this presentation is original; however, for a few IN CMOS
slides material has been taken from: • Charging and discharging
VDD
– Wolf, W., Modern VLSI Design, System-on-Chip Design, Third Edition, nodes due to switching:
Prentice Hall PTR, Upper Saddle River, New Jersey, (2002). © W
– Material taken from scientific publications with explicit author and date
capacitive dissipation. Energy
a R out
reference. © …
loss:
C
• A direct short-circuit path
through both p-type and n-type VSS
transistors during switching:
short-circuit dissipation
• Leakage
© Sabih H. Gerez, University of Twente, The Netherlands © Sabih H. Gerez, University of Twente, The Netherlands
POWER DISSIPATION EQUATION POWER VS. ENERGY

• The rest of this presentation is about power, energy per
• The power related to charging and discharging nodes is: second.
• Keep in mind that quite often it is energy that matters more than
power.
– In a battery-powered system e.g., the energy consumption determines
• Where: the battery lifetime.
– : clock frequency
• If some computations need to be done, we may use less power
– : effective capacitance, average capacitance switched in one
clock cycle
by taking more time to finish it, but in the end the consumed
– : power-supply voltage
energy may be more.
• Conclusion: be aware of the distinction between power and
energy.

WAYS TO REDUCE POWER GLITCHING: SWITCHING NOT

• Reduce clock frequency CONTRIBUTING TO FUNCTION
• Reduce effective capacitance • Example, using unit-delay simulation (1 time unit for each signal
• Reduce supply voltage: transition):
– Has a quadratic effect on power savings 1-0-0-0
– Has a negative effect on switching delay
0-0-1-1
• Avoid unnecessary switching (glitching)
1-0-0-0
0-0-1-0 ©W
• Glitches propagate through the logic resulting in unnecessary
power consumption
SWITCHING ACTIVITY: TRANSITION SWITCHING ACTIVITY FOR LOGIC

PROBABILITY GATES
• Probability of some signal s being logic ‘1’: • Probability of gate inputs being ‘1’ can be translated to
• Then the signal transition probability for a signal that is probability of outputs being one:
temporally uncorrelated, becomes:
• Examples:
• Assumption: inputs switch independently (often not true)


TEMPORALLY CORRELATED SIGNALS SPATIALLY CORRELATED SIGNALS

• One should be careful with the assumption that signals are • Signal having a common origin will be spatially correlated.
temporally independent. • In case of reconvergent fanouts independence is lost.
• A clock signal, for example, will always have 2 transitions per
clock period, even when its probability of being ‘1’ is 0.5.
• Consider the MSB of a sine wave sampled 20 times per period Output s1 of G1 s2 G2
s2 and s3 are
and encoded in 2’s complement. Its probability of being ‘1’ is G1 spatially
0.5. However, its transition probability is 0.1 (two transitions per reconverges s1 correlated
period). in G2 s3
• MSBs in a bus, representing mostly small numbers, using 2’s

complement encoding, will also be spatially correlated.
POWER-ESTIMATION TECHNIQUES (1) POWER-ESTIMATION TECHNIQUES (2)

• Circuit-level simulation • Analysis-based estimation:
– Use e.g. SPICE – Propagation of probabilities
– All currents and voltages are known – Correction for correlated signals
– Power can be computed accurately • Architecture-level estimation:
– Time consuming – Based on characterization of building blocks, such as ALUs, memories,
• Gate-level simulation etc.
– Simulate standard-cell netlist – Combined with switching activity at the blocks’ inputs.
– Keep track of switching activities
– Combine with known power numbers for each cell
– Glitches are taken into account
– Most reliable estimation method in “digital design flow”.

OPTIMIZATION AND HIERARCHY VOLTAGE REDUCTION

• The impact of design decisions decreases with the hierarchical • Most effective
level. • Difficult to apply on individual designs:
• Design choices at the system level can have an effect of – Standard-cell library has been characterized for a specific voltage range.
several orders (say, a factor of 100) of magnitude on • Even more difficult to use multiple voltages:
performance (speed, power). Think e.g. of a decision to store – For the digital circuitry on the same IC
data on chip or on external memory. – Within the same clock domain.
• The effect of decisions at lower levels of abstraction (RT level, • Still, quite some research has been performed on designing
gate level or circuit level) is far smaller (say, from a factor 2 with multiple voltages in the same clock domain
down to some 10% improvement).
AREA-POWER TRADE-OFF (1) AREA-POWER TRADE-OFF (2)

• Suppose a processor P0 with effective capacitance Ceff • Suppose now that two processors
performs some task with given deadline operating at some can be deployed to perform the
frequency-voltage combination (f,V) . task:
• So, its power consumption is: – The effective capacitance will more
than double (some overhead to
distribute tasks).
– The task’s deadline can now be met
by reducing the operating frequency
to about half the original value.
– No positive effect on power if voltage
is kept constant.

AREA-POWER TRADE-OFF (3) COMPUTATIONAL MARGIN

• As the frequency was halved, the voltage can also be more or • Critical path determines maximal
less halved without causing circuit malfunction (of course, the clock period.
voltage cannot be reduced indefinitely). • Critical path may be reduced by constant
area
• In the new situation: increasing parallelism. clock
• Use the created slack or period
computational margin in the clock
period, to reduce voltage.
• So, there may be power-area trade-
off (if the effective capacitance has
less than quadratic growth).
Power reduction at the power
expense of area!
MULTIPLE-VOLTAGE DESIGN MULTIPLE-VOLTAGE DESIGN EXAMPLE

• Consider two supply voltages Vdd,H (higher one) and Vdd,L (lower Level
Vdd,L domain
one). converter
• The idea is to “slow down” non-critical paths in the design and G1 G2
reduce power in this way.
• Transition from the lower to the higher voltage requires a level
converter to recover the logic ‘1’ level.
• Level converters also dissipate power.
• Research resulted in algorithms that automatically partition the
circuit for the different voltages. Vdd,H domain
G1 and G2 are outside critical
path and may be slowed down

MULTIPLE-VOLTAGE AT CHIP LEVEL CONSTANT-VOLTAGE RTL POWER

• Intra-block multiple-voltage design is more an academic REDUCTION
research topic than a practical issue.
• In practice, multiple voltages on chip are used on a per-block • Targeted to removing unnecessary switching including
basis. glitching.
• Some blocks can permanently operate at a lower voltage; for • The easiest thing is to turn off entire block of a design when not
some blocks, the voltage can be varied on demand (known as in use:
dynamic voltage and frequency scaling). – Example: some blocks on a radio IC are only used for transmitting others
only for receiving; the IC will probably do neither most of the time.
• Some blocks can be turned off completely.
– Implemented by clock gating or power gating.
1.8 V 1.2 V – Clock gating is easier to implement, but less effective.
0.9 to 1.4 V
BLOCK-LEVEL CLOCK GATING PREVENT COMBINATIONAL ACTIVITY
‘0’ 0
bus 1
Subblock Bus activity

in design unseen by
combinational
No activity logic in subblock
enable in clock
subtree enable
clock Clock gate clock

PREVENT GLITCH PROPAGATION WITH PREVENT GLITCH PROPAGATION WITH

REGISTERS (1) REGISTERS (2)
• One normally can’t just add registers without modifying circuit
functionality:
– Pipelining is allowed in acyclic data flow; it increases the latency (number
Signal with high
of clock cycles for input to propagate to output).
glitching activity
– Retiming is always allowed (it does not change the number of registers in
cyclic or acyclic path).
Retiming
INTRA-BLOCK CLOCK GATING (1) INTRA-BLOCK CLOCK GATING (2)

• Registers do not always change value at each clock cycle; they
sometimes keep their previous value (e.g. no “else” branch for
new state computation in VHDL).
• In the latter case, the clock can be disabled.
• This saves power consumption in the clock tree and inside the
0
register.
• This idea is encountered in many places, for example: 1
– Theeuwen, F. and E. Seelen, Power Reduction Through Clock Gating by Often implemented by
Symbolic Manipulation, VLSI '97, Gramado, Brazil, (1997). flipflops with enable port
• Also implemented in Synopsys tools.
hold clock

INTRA-BLOCK CLOCK GATING (3) GLITCH-FREE CLOCK-GATING CELL
Negative edge-
triggered flipflop
to prevent clock
glitching (latch is
also possible) © Pedram 2005
Figure 7
Hold and gating
hold logic should
clock-gating consume less power
cell than saved by
clock disabling clock.
PARTIAL PRECOMPUTATION LOGIC (1) PARTIAL PRECOMPUTATION LOGIC (2)

• Consider single-bit register, computed from multiple bits: A_MSB
B_MSB
A_LSB
B_LSB g1: predictor for f =0
• Part of input register can be disabled when output only depends
g2: predictor for f =1
on other part of input register.
• Requires predictor functions that also consume power.
• See Figure 7 of [Pedram 1996]. © Pedram 1996
• Comparator function is a good example. Figure 7

ERROR-TOLERANT DESIGN RAZOR-FLIPFLOP STRUCTURE

• If the voltage is too low (or the frequency too high), the circuit
will fail for its critical paths.
• Instead of designing for worst-case, one can also accept the
failures and think of a method to deal with them.
• Assuming that the critical paths are not sensitized often, one
may accept some performance overhead to fix the failures
while operating at a subcritical voltage.
• An example is to detect and repair failures by means of so-
called razor flipflops.
Ernst, D., N.S. Kim, S. Das, S. Pant, R. Rao, T. Pham, C. Ziesler, D. Blaauw, T. Austin,
K. Flautner and T. Mudge, "Razor: A Low-Power Pipeline Based on Circuit-Level Timing
Speculation", 36th International Symposium on Microarchitecture (MICRO-36'03), pp. 7-
18, (2003). © Ernst et al. 2003 Figure 1a
RAZOR-FLIPFLOP TIMING RAZOR-FLIPFLOP PRINCIPLES

• Shadow latch inside flipflop is clocked by delayed clock.
• If new clock edge comes before data is stable, wrong data may
be clocked in by main flipflop. Shadow latch will clock right data
value (under some conditions).
• Difference between data in main flipflop and data in latch
(EXOR) will generate error signal.
• Error signal is used to insert extra clock cycle in which data
from shadow latch is used while other parts of the circuit are
halted by e.g. clock gating.
• Use razor flipflops only for flipflops in near-critical paths.
© Ernst et al. 2003 Figure 1b

POWER GATING POWER GATING: SWITCHES (1)

• Clock gating preserves the circuit’s state. sleep VDD
c VDD
• For situations when batteries should last extremely long
Header p-type network
(several years), as for a node in a sensor network, clock gating
is not enough. Leakage cannot be neglected.
transistor c a b
• The solution is to turn off the power: power gating.
p-type network out
a b b
• Only a small subcircuit remains powered:
– It periodically turns on and off the processor;
out n-type network c
– It stores the state information in retention memory;
b a
– It may operate at a reduced clock frequency (32 kHz is a typical n-type network c
frequency for the sleep mode). a Footer sleep
VSS transistor
VSS
POWER GATING: SWITCHES (2) POWER-MANAGEMENT UNIT

• Switches need to be designed carefully: • Finite state machine in the always-on domain
– They should have low resistance (low voltage drop, high currents) • Controls analog circuitry to provide appropriate voltages
– They should have low leakage
• Takes care of generating the sleep signals with the right timing
• In the same way that gates controlled by the same clock belong
to the same clock domain, gates controlled by the same “sleep”
signal belong to the same power domain. Examples:
– Always-on domain
– Radio domain
– DSP domain
– Peripheral domain

ISOLATION CELL RETENTION FLIP-FLOP

• Signals in unpowered domains may be “floating”. • Stores information while part of the circuit is asleep.
• Isolation cells make sure that other logic is unaffected. • The most important thing is that it remains powered.
• That either a constant 0 or 1 is output to active logic. • Think of the master-slave flip-flop: one can have the master
latch being turned off for further power reduction while the slave
0 latch remains powered.
Unpowered Active
logic 1 logic
sleep
DESCRIBING “POWER INTENT” ARCHITECTURAL CONSIDERATIONS

• Power signals (Vdd, Vss) are not explicitly represented in
• Traditional processor has the Von Neumann architecture:
hardware descriptions written in VHDL or Verilog.
– Program code and data in same memory.
• So, how can we simulate or synthesize circuits with multiple – This bottleneck not only affects performance but power as well (larger
power domains? memories require more energy per access).
• Answer: using descriptions external to VHDL/Verilog. – Time and energy is lost in memory transfers.
• Universal Power Format (UPF) is such a description: – Multiplexing data and code streams destroys temporal correlation.
– Standardized by the IEEE. • Low-power architectures have locality of reference:
– Constructs for specifying power domains. – a high degree of parallelism
– Allows for references to signals in HDL that control sleep states. – with local memories to avoid data transport across large distances.
– Specifies values for isolated signals.
– Supported by Synopsys, Questasim, etc.
• Also: Common Power Format (CPF), from Cadence.

SOFTWARE-LEVEL STRONGARM 1100 POWER STATES

LOW POWER DESIGN
• Compact code not only reduces the clock cycles needed for
some computation, but also the switching activity and therefore
the power consumption.
• Software (e.g. operating system that knows about the tasks to
be performed) can control:
– Voltage
– Clock frequency
• Having dedicated co-processors for computation-intensive
tasks will, in general, reduce power.
• Careful choice of sleep policy contributes to power reduction © Benini 2001
(wake-up time is relevant). Figure 7
PRESS RELEASE FEBRUARY 2006 SOME HISTORY

• ARM and Handshake Solutions announce availability of • Interest in asynchronous logic as old as synchronous logic
clockless processor ARM996HS™ (important research results already reported in 1950s)
– Handshake Solutions is a Philips spin-off • Has received less attention because more complicated design
– Processor comparable to ARM968E-S, a clock-gated synchronous procedure
processor • Research has always continued and has resulted in
– Clockless processor uses 2.8 times less power implementations of complex ICs. Examples:
– No extra area – ARM-compatible AMULET processors (University of Manchester):
Amulet 1 (ARM6, 1994), Amulet 2 (ARM 7, 1996), Amulet 3 (ARM 9,
– Very low electro-magnetic emissions (EME)
2000)
– Synchronous interface – DCC error corrector (Philips, 1994)
– Fits in conventional design and test flow – 80C51 microcontroller (Philips, 1998)
• Handshake Solutions no longer exists .


REGISTER TRANSFERS ASYNCHRONOUS PIPELINE

• Clock signals are critical in synchronous designs © Sparsoe 2001
– Strict timing margins
– Large clock tree circuitry Figure 1.1
– Significant power consumption in clock tree
• Asynchronous “clocking” of memory elements is a low-power
alternative
– Based on request and acknowledge signals
– New data can be stored when successor has copied current data
• See Figure 1.1 of [Sparsoe 2001]
HANDSHAKE PROTOCOLS GALS SYSTEMS

• A mechanism is necessary to indicate that produced data in • The larger the IC, the more difficult it becomes to have
some logic stage is valid and can be processed by the next. synchronicity across the entire IC in current and future
• This can be done by additional signals that accompany the data technologies.
 bundled-data protocols. • Solution is the globally asynchronous locally synchronous
• Or, the validity can be encoded in the data itself. E.g. two wires (GALS) approach to system design.
per bit: • So, knowledge of asynchronous design also comes of use in
– 01  zero conventional design.
– 10  one
– 00, 11  transition

PROBABILISTIC COMPUTING APPROXIMATE COMPUTING

• Reduce supply voltage to the point that a circuit’s output is no • Power-accuracy trade-off similar to probabilistic computing, but
longer error free. now the circuits are deterministic: they produce errors by
• Errors occur in a rather unpredictable way, hence probabilistic design!
or stochastic computing. • Think of a transistor-level circuit for a full adder:
• Use this type of logic for the LSBs in the data path. – Remove some strategically chosen transistors.
– This will cause errors in the circuit’s truth table.
• For some signal-processing applications, this results in
– On the other hand, the circuit area is reduced and hence the power
interesting power-accuracy trade-offs.
consumption.
– Again, such circuits are mainly used for the LSBs in the data path.
APPROXIMATE ADDERS (1) APPROXIMATE ADDERS (2)

• Example from © Gupta 2013: • Truth tables: © Gupta 2013
24 transistors 11 transistors

ERROR MEASURES POWER ESTIMATION IN SOC COURSE

• From a signal-processing point of view, the introduced errors • New option for automatic clock gating during synthesis.
can be seen as noise. • Create a separate post-synthesis VHDL configuration for each
• So, the quality of an approximate circuit can be expressed in scenario that you want to investigate.
some form of signal-to-noise ratio. – Each scenario can e.g. have a different input data stream.
• See, Han 2013 for pointers to different error measures. – The scenario should be simulated at the same clock frequency as for
which the design was synthesized.
• Make sure that the scenarios simulate correctly.
• In Questasim, generate a so-called backward SAIF (switching
activity interface format) file for the scenario.
• Let Synopsys Design Compiler/Power Compiler combine the
SAIF data with the design data to deliver a power report.
FURTHER READING (1) FURTHER READING (2)

• Review papers: • Some books:
– Pedram, M., Power Minimization in IC Design: Principles and – Chandrakasan, A.P. and R.W. Brodersen, Low Power Digital CMOS
Applications, ACM Transactions on Design Automation of Electronic Design, Kluwer Academic Publishers, Boston, (1995).
Systems, Vol.1(1), (January 1996). – Rabaey, J.M. and M. Pedram (Eds.), Low Power Design Methodologies,
– Pedram, M. and A. Abdollahi, Low-Power RT-Level Synthesis Kluwer Academic Publishers, Boston, (1995).
Techniques: A Tutorial, IEE Proceedings on Computers and Digital – Benini, L. and G. De Micheli, Dynamic Power Management, Design
Techniques, Vol.152(3), pp. 333-343, (May 2005). Techniques and CAD Tools, Kluwer Academic Publishers, Boston,
– Benini, L., G. De Micheli and E. Macii, Designing Low-Power Circuits: (1998).
Practical Recipes, IEEE Circuits and Systems Magazine, Vol.1(1), pp. 6- – Piguet, C. (Ed.), Low-Power Electronics Design, CRC Press, Boca
25, (2001). Raton, (2005).
– Alioto, M., Ultra-Low Power VLSI Circuit Design Demystified and
Explained: A Tutorial, IEEE Transactions on Circuits and Systems-1:
Regular Papers, Vol.59(1), pp. 3-29, (January 2012).

FURTHER READING (3) FURTHER READING (4)

• Some more books: • Approximate computing:
– Piguet, C. (Ed.), Low-Power Processors and Systems on Chips, Taylor – Han, J. and M. Orshansky, "Approximate Computing: An Emerging
and Francis, Boca Raton, (2006). Paradigm for Energy-Efficient Design", 18th European Test Symposium
– Otis, B. and J. Rabaey, Ultra-Low Power Wireless Technologies for (ETS), (2013).
Sensor Networks, Springer, (2007). – Gupta, V., D. Mohapatra, A. Raghunathan and K. Roy, Low-Power
– Mohanty, S.P., N. Ranganathan, E. Kougianos and P. Patra, Low-Power Digital Signal Processing Using Approximate Adders, IEEE Transactions
High-Level Synthesis for Nanoscale CMOS Circuits, Springer, (2008). on Computer-Aided Design of Integrated Circuits and Systems,
Vol.32(1), pp. 124-137, (January 2013).
SYSTEM-ON-CHIP DESIGN 65
LOW-POWER IC DESIGN September 18, 2018
FURTHER READING (5)

• A book by an expert in the field (on-line copy available through
the UT Library):
– Rabaey, J., Low Power Design Essentials, Springer, (2009).
– http://www.springerlink.com/content/978-0-387-71712-8
• Asynchronous design:
– Sparsoe, J. and S. Furber (Eds.), Principles of Asynchronous Circuit
Design, A Systems Perspective, Kluwer Academic Publishers, Boston,
(2001).
– Chapters 1 to 8 freely available: http://www2.imm.dtu.dk/~jspa/
• You are welcome to search in my database:

– http://www.bibix.nl/literature-db/search.html
© Sabih H. Gerez, University of Twente, The Netherlands

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SYSTEM-ON-CHIP DESIGN 2

LOW-POWER IC DESIGN September 18, 2018

© Sabih H. Gerez, University of Twente, The Netherlands

SYSTEM-ON-CHIP DESIGN 3 SYSTEM-ON-CHIP DESIGN 4

ACKNOWLEDGEMENT SOURCES OF POWER DISSIPATION

POWER DISSIPATION EQUATION POWER VS. ENERGY

SYSTEM-ON-CHIP DESIGN 7 SYSTEM-ON-CHIP DESIGN 8

WAYS TO REDUCE POWER GLITCHING: SWITCHING NOT

SWITCHING ACTIVITY: TRANSITION SWITCHING ACTIVITY FOR LOGIC

• Assumption: inputs switch independently (often not true)

SYSTEM-ON-CHIP DESIGN 11 SYSTEM-ON-CHIP DESIGN 12

TEMPORALLY CORRELATED SIGNALS SPATIALLY CORRELATED SIGNALS

• MSBs in a bus, representing mostly small numbers, using 2’s

POWER-ESTIMATION TECHNIQUES (1) POWER-ESTIMATION TECHNIQUES (2)

SYSTEM-ON-CHIP DESIGN 15 SYSTEM-ON-CHIP DESIGN 16

OPTIMIZATION AND HIERARCHY VOLTAGE REDUCTION

AREA-POWER TRADE-OFF (1) AREA-POWER TRADE-OFF (2)

SYSTEM-ON-CHIP DESIGN 19 SYSTEM-ON-CHIP DESIGN 20

AREA-POWER TRADE-OFF (3) COMPUTATIONAL MARGIN

MULTIPLE-VOLTAGE DESIGN MULTIPLE-VOLTAGE DESIGN EXAMPLE

SYSTEM-ON-CHIP DESIGN 23 SYSTEM-ON-CHIP DESIGN 24

MULTIPLE-VOLTAGE AT CHIP LEVEL CONSTANT-VOLTAGE RTL POWER

BLOCK-LEVEL CLOCK GATING PREVENT COMBINATIONAL ACTIVITY

Subblock Bus activity

SYSTEM-ON-CHIP DESIGN 27 SYSTEM-ON-CHIP DESIGN 28

PREVENT GLITCH PROPAGATION WITH PREVENT GLITCH PROPAGATION WITH

INTRA-BLOCK CLOCK GATING (1) INTRA-BLOCK CLOCK GATING (2)

SYSTEM-ON-CHIP DESIGN 31 SYSTEM-ON-CHIP DESIGN 32

INTRA-BLOCK CLOCK GATING (3) GLITCH-FREE CLOCK-GATING CELL

PARTIAL PRECOMPUTATION LOGIC (1) PARTIAL PRECOMPUTATION LOGIC (2)

SYSTEM-ON-CHIP DESIGN 35 SYSTEM-ON-CHIP DESIGN 36

ERROR-TOLERANT DESIGN RAZOR-FLIPFLOP STRUCTURE

RAZOR-FLIPFLOP TIMING RAZOR-FLIPFLOP PRINCIPLES

SYSTEM-ON-CHIP DESIGN 39 SYSTEM-ON-CHIP DESIGN 40

POWER GATING POWER GATING: SWITCHES (1)

POWER GATING: SWITCHES (2) POWER-MANAGEMENT UNIT

SYSTEM-ON-CHIP DESIGN 43 SYSTEM-ON-CHIP DESIGN 44

ISOLATION CELL RETENTION FLIP-FLOP

DESCRIBING “POWER INTENT” ARCHITECTURAL CONSIDERATIONS

SYSTEM-ON-CHIP DESIGN 47 SYSTEM-ON-CHIP DESIGN 48

SOFTWARE-LEVEL STRONGARM 1100 POWER STATES

PRESS RELEASE FEBRUARY 2006 SOME HISTORY

• Handshake Solutions no longer exists .

SYSTEM-ON-CHIP DESIGN 51 SYSTEM-ON-CHIP DESIGN 52

REGISTER TRANSFERS ASYNCHRONOUS PIPELINE

HANDSHAKE PROTOCOLS GALS SYSTEMS

SYSTEM-ON-CHIP DESIGN 55 SYSTEM-ON-CHIP DESIGN 56

PROBABILISTIC COMPUTING APPROXIMATE COMPUTING

APPROXIMATE ADDERS (1) APPROXIMATE ADDERS (2)

SYSTEM-ON-CHIP DESIGN 59 SYSTEM-ON-CHIP DESIGN 60

ERROR MEASURES POWER ESTIMATION IN SOC COURSE

FURTHER READING (1) FURTHER READING (2)

SYSTEM-ON-CHIP DESIGN 63 SYSTEM-ON-CHIP DESIGN 64

FURTHER READING (3) FURTHER READING (4)

FURTHER READING (5)

• You are welcome to search in my database:

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