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Testing The Simulink Model by CompactRIO
Testing The Simulink Model by CompactRIO
I. Vesely*. M. Sir**
D. Zmecnik***
*Faculty of Electrical Engineering and Communication, Brno University of Technology, Center for Research and Utilization
of Renewable Energy Sources, Czech republic (Tel:+42051141148; e-mail: xvesel43@stud.feec.vutbr.cz).
** Faculty of Electrical Engineering and Communication, Brno University of Technology
Czech Republic (Tel +420541141308; e-mail: xsirmi00@stud.feec.vutbr.cz).
*** Faculty of Electrical Engineering and Communication, Brno University of Technology
Czech Republic (Tel:+42051141148; e-mail: xzamec11@stud.feec.vutbr.cz).
Abstract: This article describes the testing of the Matlab model using NI CompactRIO real-time
embedded controllers. If workplace has MATLAB and LabVIEW, the realization of testing becomes
much cheaper than buying the Matlab real-time modules. The paper describes how to install all the
programs and how to connect these programs each other, so we could easily test and debug MATLAB
model using CompactRio and Labview.
Keywords: Matlab Simulink, LabView, CompactRIO, connection, SITL, simulation, DC motor, dll
cd C:\SimulationInterfaceToolkit
NISIT_AddPaths;
NISITServer('start',6011);
Fig. 1. Matlab model
If Vxworks63gccdist is not copied to the root directory C:\.
the path in file setup-gcc.bat (\gccdist\supp\setup-gcc.bat) has CompactRIO cards. This means that the Matlab model is in
to be changed. In file the command set the form of DLLs, directly connected to the input and output
GCCPATH=c:\gccdist must be changed to the current path of cards. In the second way, inputs or outputs data of the
e.g. set GCCPATH=i:\gccdist. cards are modified or other functions, which Simulink model
does not contain, are added to the program.
And the last change is in the directory of Simulation Interface
Toolkit. The file nidll_vxworks.tlc from C:\ 2.1 First way
SimulationInterfaceToolkit\2010\VxWorks\ModelInterface\tm
w\R2007b\ is copied to C:\ SimulationInterfaceToolkit\ In this case, the model of the DLLs form is directly connected
2010\ModelInterface\tmw\R2007b\. to the inputs and outputs of CopactRio cards. (National
And in file nidll_vxworks.tmf (C:\SimulationInterfaceToolkit\ Instrument, 2010b).
2010\ ModelInterface\ tmw\ R2007b\) the version is changed For connection of the Matlab model and the inputs and
from SIT_VERSION=5.0 to current version in our case outputs, the bitfile must be created first. Bitfile define the
SIT_VERSION= 2010. analog, digital, and pulse width modulation (PWM) inputs
and outputs of the FPGA device.( National Instrument
4. CREATING DLL AND FILE .OUT 2008a).
To create bitfile we use project that is already created in
Now everything is set and a Simulink model (Fig.1) of our LabVIEW examples. The file name is sitfpga cRIO IO.lvproj
application can be created and then converted into a DLL. If and it is located in the directory
we can see the following text during start, the Matlab is set \LabVIEW2010\vi.lib\addons\SimulationInterface\_IOTypes\
correctly (National Instrument 2011a). Plugins\NI-FPGA\FPGA IO Source\
SIT: Added paths for Simulation Interface Toolkit Version 2010 This project is mostly created for other chassis or c series
Starting the SIT Server on port 6011 modules, which we do not use. Therefore, we must revamp
SIT Server started the project. The most important part (sit IO cRIO.vi file) has
to be copied to another folder and then the project has to be
Simulink model must contain SignalProbe block and the rebuilt into our configuration. (It is a change of Compact Rio
LabView is connected via inport and outport (Fig. 1). IP address and adding of our chassis and c series modules).
Unconnected inports can be used for monitoring waveforms After this adjustment we upload the sit IO cRIO.vi file back
in the processor of CompactRIO. The DLL file and other into the FPGA and we rebuild it for our configuration.
files, that are generated together, are need for connecting to During editing a file, it is important not to change the
LabVIEW environment. This interconnection provides structure in the gray boxes
Simulation interface toolbox. If we don't want to run the In the file, all inputs and outputs do not have to be used but
model in real-time mode, we need only DLL file which is only those that are needed. The modified file is compiled to
generated by nidll.tlc. Because in our case we need to use create bitfile. This bitfile, that is created in the directory
real-time mode, additional files must be created, mainly .out project / FPGA Bitfiles, is copied to a directory with other
file which is generated by nidll_vxworks.tlc. These files are bitfiles (\LabVIEW 2010\vi.lib\addons\Simulation
generated in Matlab Simulink. The different versions of Interface\_IOTypes\Plugins\NI-FPGA\FPGA Bitfiles\). Since
Matlab Simulink may have different paths to the generator. In the file has not standard name it must be renamed to SIT
Matlab R2010b Simulink path is → − connection manager could found it. In our case its name is
ℎ → …→ sitfpga cRIO-9074 IO.lvbitx.
− ℎ , where nidll.tlc is selected as
System target file and then we click on build. For The connecting manager
nidll_vxworks.tlc it is same. Now we have all files that we Now we can make connections. In the blank vi we create
need to connect with LabView. control and indicators by which we want control Matlab
model and display a variety of waveforms. Connection is
5. THE CONNECTION OF DLLs WITH LABVIEW done using the SIT Connection Manager that we can find in
the tools. In this manager we select the real-time target. At
The first thing we need to know is what type of connections
the beginning, we set IP addresses and the type of compact
of dll and LabVIEW and CoppactRio we will need. We can
Rio (Fig.2). Next we enter the path of model dll and path to
choose one of the two ways. In the first way, we do not need
the directory of project in the Model and Host category.
to change the data which are sent or received from
Fig. 2. SIT Connection Manager
Fig. 4. FPGA
In the category Mappings we connect the controls from
LabVIEW with variables, which we want to control in the input signals or output signals from the cards, or we add more
model, and connect the indicators with variables, which we functions to the program. These additional functions can be
want to monitor. The connection of model with the inputs programmed into the RT microprocessor or directly into the
and outputs of cards is done in the Hardware I / O category. FPGA of CompactRio. These changes may be different
Here we select Configure HW I/O. Then we click the right conversion of signal from cards, evaluation of encoder
mouse button on IP address and select Add Device- NI-FPGA signals, and additional functions. These changes are very
and now we can see bitfile that we have created. If there is time consuming and they could be programmed directly into
bitfile not displayed, it may mean that we renamed it poorly the FPGA e.g. PWM.
or we save it to another directory. After confirming (press During the connecting of model with LabVIEW we proceed
OK), we can connect the inputs and the outputs of cards with as well as in the first case. We use SIT connection manager
the inport and the outport of Matlab model (Fig. 3). This again, where we set the IP address, path to the directory with
setting could be found in the video (National Instrument, the DLL and the project directory and we connect each
2008b) control and indicator block with Matlab model in the
After everything is connected and set up, SIT connect Mappings category. But unlike the first method, we do not
manager creates a project ProjectName_Driver.lvproj, which create bitfile, if we want to use FPGA. Connection is done in
is used for communication between the model in a format a project which was created by Sit connect manager. Created
DLLs and LabVIEW. At the same time in the original file .vi project contains only the RT CompactRIO Target, where
SIT creates a model for the simulation controlling of there are files vi working with dll of Matlab model. So that
LabVIEW mode. we can work with signals from the card, we can add FPGA
by classical way (National Instrument, 2009b). In our case we
2.2 Second way use the FPGA to generate PWM and evaluation of the
encoder signals (Fig 4).
As it has been said before in the second way, we change the Data from the cards are first processed in the FPGA and then
send to the Real Time Processor where they are connected to
the inputs of the Matlab model. For this connection we use an
already created file ProjectName_Base Rate Loop.vi, which
is saved in the directory subVIs of CompastRio RT Target.
This file contains several parts which we can change. They
are flat sequence (Fig.5)- Init Code, where initialization is
performed before running the model, Read Code, where the
data entering into the model, Write code, where data alighting
from the Matlab model and Close Code, where final
instruction are written. The file also contains blocks for
reading and writing to I / O when using bitfile. But this was
not used in our project.
DLL PC
motor
LabView
encoder
Fig. 6. Base Rate Loop with other function Fig. 8. Front page of LabView project
, chassis and c series module, it is more compact. For various <http://zone.ni.com/devzone/cda/tut/p/id/11654%23toc4
applications, we can buy only those cards which we need. >.
Another big advantage is the presence of an FPGA, which we National Instrument. NI Developer Zone [online]. 2010a [cit.
use in many applications. In our case it was the generating of 2011-11-16]. Communicating with the SIT Server
PWM and the work with the signals of encoder. The (Simulation Interface Toolkit). Available from:
connection of these two environments does not restrict the <http://zone.ni.com/reference/en-XX/help/371504F-
simulation. And for easy connection of the LabView control 01/lvsitconcepts/sit_c_communicating_with_the_sit_serv
with Matlab model we can easily debug the application at er/>.
runtime. National Instrument. NI Developer Zone [online]. 2010c [cit.
2011-12-07]. Communicating with the SIT Server
8. ACKNOWLEDGEMENTS
(Simulation Interface Toolkit). Available from:
The research has been supported by Czech Science <http://zone.ni.com/reference/en-XX/help/371504F-
Foundation under the project 102/09/H081 “SYNERGY - 01/lvsitconcepts/sit_c_communicating_with_the_sit_serv
Mobile Sensoric Systems and Network“, “Research of er/>.
Modern Methods and Approaches in Automation“ from the National Instrument. NI Developer Zone [online]. 2011a [cit.
Internal Grant Agency of Brno University of Technology 2011-11-16]. Building a LabVIEW User Interface for a
(grant No. FEKT-S-11-6) and European Regional Simulink® Model with LabVIEW Simulation Interface
Development Fund under project No. Toolkit. Available from:
CZ.1.05/2.1.00/01.0014. <http://zone.ni.com/devzone/cda/tut/p/id/3057>.
National Instrument. National Instrument [online]. 2011b [cit.
2011-11-16]. CompactRIO Real-Time Controllers.
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<http://sine.ni.com/nips/cds/view/p/lang/en/nid/14155>.