LOGO

A. Abdul Razak, ST., MT., M.Eng, Ph.D.

Control Unit
and Instruction Process
 Decomposition of a Computer’s Organization LOGO

Computer

Connections
(High/Low-Speed)
Processor + Interface Devices

Memory

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 Decomposition of a Computer’s Organization LOGO

Processor =
Datapath + Control

Control Datapath
Control Signals Processing of
Orchestrates the
correct sequence data according
of micro- to instructions.
instructions or
Status Signals
micro-stages in
the processing of
instruction.

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 Decomposition of a Computer’s Organization LOGO

Data Memory

Datapath Memory Interface (Buses + Regs)

Register
File

Data Mem

Register File
ALU
ALU
O/P Reg.

Source: Patterson Fall 97

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 Decomposition of a Computer’s Organization LOGO

Instruction Memory
Control

Memory Interface (Addr. Bus)

Instruction Mem PC IR

Prog Counter
PC Status
Upd.
Instruction Reg Datapath
CU C.U.
Control

Source: Patterson Fall 97

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 Basic Functions of the C.U. LOGO

 The CU functions by sending signals in each

state that do the following:
 Read Selection = Connection to a bus from various
sources (e.g., buses, registers) using Muxes or Tri-
State Buffers (+ Decoders). Only one source can be
read onto a bus.
 Write Selection = Loading one or more registers w/
the data at the input of the registers.

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 Basic Functions of the C.U. LOGO

 Read occurs at the beginning of a clock cycle (cc)

 The corresponding write into the target register
occurs at the rising edge of the next cc (assuming
Read finishes by that time; in general the Write
occurs at the rising edge of the next cc after the Read
finishes).
 Control signals for both need to be valid in the
current cc
r1 r2
Read
Write/Load 0 1
Period sel=0 2:1 Mux
Bus

sel=0, ldrb=1 ra rb rc rd
ldra=0 ldrb=1 ldrc=0 ldrd=0

Source: Patterson Fall 97

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 Basic Functions of the C.U. LOGO

r1 r2
Read 0 1
Period Write/Load sel=1 2:1 Mux
Bus

sel=1, ldrb=1, ra rb rc rd
ldrd=1 ldra=0 ldrb=1 ldrc=0 ldrd=1

 The C.U. orchestrates the processing of instructions

along a datapath by a simple sequence of Read and
Write selects in each cc
 A Register-Transfer-Like Notation:
 Read Operation: r2 => Bus (r2 o/p connected to the bus)
 Write Operation: rb <= Bus; rd <= Bus (Bus value written/loaded
to registers rb, rd
 Note final effect of the above Read and Write in the same cc (I.e.
Read and Write select control signals valid in the same cc) is :
rb <= r2; rd <= r2 Source: Patterson Fall 97

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 Instruction Process LOGO

Instruction: ADD r2 r3 r7 [r2 <- r3 + r7]

Data Memory
Instruction Memory

Memory Interface (Buses + Regs)

Memory Interface (Addr. + Data Bus)

PC IR
Register
File
PC
Upd.

C.U.
ALU

O/P Reg.
Source: Patterson Fall 97

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 Instruction Processing: Phase 1 -- Fetch LOGO

Instruction: ADD r2 r3 r7 [r2 <- r3 + r7]

Data Memory
Instruction Memory

Memory Interface (Buses + Regs)

Memory Interface (Addr. + Data Bus)

Source & dest reg addr

PC IR
Register
1 1 File
PC Load IR when
Upd.
Instr. Avail
C.U. [IR <= Data Bus]
Connect PC to
Addr. Bus & ALU
Read Mem. Status signals
Onto Data Bus O/P Reg.
[PC=>Addr Bus; Mem[PC] => Data Bus]
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 Instruction Processing:
LOGO
Phase 2 -- Decode & Incr. PC

Instruction: ADD r2 r3 r7 [r2 <- r3 + r7]

Data Memory
Instruction Memory

Memory Interface (Buses + Regs)

Memory Interface (Addr. + Data Bus)

PC IR
Register
2 File
PC Decode State
Upd. 2
Start State for ADD

Load PC w/ o/p
of Update H/W ALU
[PC <= PC Upd o/p]
O/P Reg.

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 Instruction Processing:
LOGO
Phase 3 --Read Operands in RF

Instruction: ADD r2 r3 r7 [r2 <- r3 + r7]

Data Memory
Instruction Memory

Memory Interface (Buses + Regs)

Memory Interface (Addr. + Data Bus)
Register
File r3
PC IR
3 r7
PC
Upd.

C.U.
Connect regs specified 3
ALU
by source fields of IR to
Load appr. internal regs of
Buses A and B
ALU w/ Bus A, B data O/P Reg.
[r3 => BusA; r7=> BusB]
[rega <= Bus A; regb<= BusB
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 Instruction Processing:
LOGO
Phase 4 --Execute (in ALU)

Instruction: ADD r2 r3 r7 [r2 <- r3 + r7]

Data Memory
Instruction Memory

Memory Interface (Buses + Regs)

Memory Interface (Addr. + Data Bus)

PC IR
Select ADD FU to Register
connect to ALU o/p reg File
PC
Upd. [ADD o/p => ALU o/p]
4
C.U.
ADD
ALU
4
Load o/p reg O/P Reg.
w/ ALU o/p [o/p reg <= ALU o/p]
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 Instruction Processing:
LOGO
Phase 5 --Write Back (to RF)

Instruction: ADD r2 r3 r7 [r2 <- r3 + r7]

Data Memory
Instruction Memory

Memory Interface (Buses + Regs)

Memory Interface (Addr. + Data Bus)

PC IR
Register
PC File
Upd.
5
C.U.
ALU
Write data on write
port to reg specified in O/P Reg.
dest filed of IR [r2 <= o/p reg]
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LOGO

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