Technical Diagnosis of Basic Logic Gates

Z. Tucaković
Automatic Control and Electronics Department, Faculty of Electrical Engineering Sarajevo
Sarajevo, Bosnia and Herzegovina
ztucakovic1@etf.unsa.ba

Abstract - In this paper, fault diagnosis of elementary logic

gates is presented and most common causes of gate failure
with a special focus on the diagnostic tests are discussed.
The practical part of this paper includes the solution
implementation, and more specifically, building the testing
prototype. To support this, electrical schematic of the circuit
is included, as well as the final design of the device.

I. INTRODUCTION
During laboratory assignments in electronics, different
problems might occur. Resistors, capacitors, transistors, as
well as other components in complex devices such as
logic gates might be dysfunctional or damaged. Many Figure 1: Common symbols for logic gates (NOT, AND, OR, NAND,
integrated chips have several integrated logic gates on NOR) and symbols according to IEC
them (i.e. gate 7400 has four NAND gates, each with two
inputs). If one gate on a chip is damaged, usually another
TABLE I. TRUTH TABLE FOR ABOVE MENTIONED OPERATIONS
gate is used. After that, the chip is left in the laboratory
and the person coming next will assume it is fully A B A’ B’ A˄B A˅B A|B A↓B
functional. 0 0 1 1 0 0 1 1
That is the reason behind checking the functionality of 0 1 1 0 0 1 1 0
a chip. It can be done by setting logic zeros and logic ones 1 0 0 1 0 1 1 0
on inputs of logic gates. This can be a cumbersome task,
1 1 0 0 1 1 0 0
and that is the reason why automation of the process is
useful, easier and faster. Automation of logic gates
functionality check is the subject of this paper. The Sheffer’s and Peirce’s operation, respectively [6].
prototype of a device which checks the functionality of Symbols of all these gates are given in Figure 1.
basic logic gates has been made and the user would be
provided with the information which gates inside the chip In Table I the truth tables for aforementioned
are functional. References [1] and [2] deal with this operations are given.
problem.
III. CAUSES OF LOGIC GATES MALFUNCTION
In the second chapter, theoretical basis for basic logic
gates is given. In the third and fourth chapter, causes of A malfunction of a logic gate is a physical defect of
malfunction and generation of diagnostic tests are one or more of its components, which causes malfunction
analyzed. Fifth chapter contains description of the of the entire system. Sometimes, a logic gate is
prototype structure and its parts (specifically power supply, permanently damaged. This class of malfunctions is
microcontroller [3], display [4], keyboard, zero insertion caused by errors in element production or by the
force socket, as well as integrated chip, whose components aging [7].
functionality will be tested). In the sixth chapter the The class of temporary malfunctions is caused by
algorithm of testing is presented, and in the seventh is badly synchronized structures or asynchronous structures
given programming code that implements the algorithm. of digital systems, different disturbances caused by
Chapter eight contains appendices, i.e. photos of the internal noise or external influences. In this class there
prototype and its electronic scheme. are categories of random and categories of occasional
malfunctions. Occasional malfunctions can become
II. THEORETICAL BASIS FOR BASIC LOGIC GATES permanent with time, and these malfunctions are then
The logic gate is an electronic circuit or a device, called constant malfunctions. They usually occur in
implementing a Boolean function [5]. Basic logic gates digital systems, discrete systems or in integrated circuits.
are usually NOT, AND, OR, NAND and NOR gates, and They occur in the lowest levels of integration, as well as
they represent logical negation, conjunction, disjunction, in Large-scale integration (LSI) and Very-large-scale-
integration (VLSI).

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 However, in digital systems which use LSI and VLSI
components, temporary malfunctions often occur. They
are a special problem regarding malfunction detection,
especially in attempts to identify what causes them. Many
methods, which are formed for detection and
identification of constant malfunctions can be used for
diagnostics of temporary malfunctions, if diagnostics
programs are processed in an on-line mode of the digital
system. This applies only to digital systems, which
include at least one digital computer.
In Figure 2, an implementation of a NOT gate is
shown. The input is marked as x, and the output as y. If
this circuit works correctly, then y should be negated x.
Possible physical defect of the NOT gate (Figure 2)
and the value of output in that case are shown in Table II.
In these cases, output holds the same value for both
inputs (0 and 1). That value is permanent 0 or permanent
1 (p-0 or p-1), and represents a class of constant
malfunctions.
Multiple malfunctions are also possible, but they are
rare and can cause other types and classes of
malfunctions. In essence, malfunction in a circuit also
appears when a logic gate does not have output. That is
defined by the truth table of a given operation. In this
paper, the accent is not on finding the reason of
malfunction, but on the identification of malfunction (if
one exists).
Figure 2: Possible implementation of NOT gate [7]
TABLE II. POSSIBLE PHYSICAL DEFECTS OF NOT GATE (FIGURE 2)
[7]
Physical defects Value of output y
Base (b) of transistor T is open-circuited
Collector (c) is open-circuited
Emitter (e) is open-circuited
Points b and c are short-circuited
Points b and e are short-circuited
Points c and e are short-circuited
Resistor Rc is open-circuited
Resistor Rc is short-circuited
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IV. DIAGNOSTICS TEST GENERATION
Inspecting the functionality of logic gate varies from
one gate to another. For example, if the integrated chip
7400 is inspected (it consists of four NAND gates with
two inputs, and its pin arrangement is shown in Figure 3),
then each of four NAND gates will be inspected as
described in the following text, and results will be
compared with the results of ideal, correct NAND gate.
Every method of checking logic gate functionality
must set gate inputs on logic zeros or ones and compare
output to the ideal, expected output (output of the
functional gate). If they are not identical, inspected logic
gate has a malfunction. If they are identical, next
combination of logic zeros and ones should be set on
inputs. This process continues until there are no
combinations left untested.
There are many methods for checking logic gate
functionality. In this paper, two will be considered:
- Checking logic gate functionality using sequential logic,
- Using a microcontroller.
Basic properties of each method are:
1. Size of prototype
Use of both sequential logic and microcontroller
results in small final product, especially if a printed
circuit board (PCB) is used.
2. Connections between components
Sequential logic demands much more components
than a microcontroller, which makes the final product
more complicated and increases the probability that
one of used components has a malfunction. In
sequential logic, a large number of flip-flops is
necessary, because the final product is quite
complicated automaton. On the other hand, there are
less components if a microcontroller is used, but it
requires a source code for it.
3. Necessity for additional elements and the
increase of the number of gates that are able to
inspect
Sequential logic cannot provide simple addition of
external components (without making the prototype
extremely complicated), unlike microcontroller.
1 Keyboard, display and other elements that make the
0 prototype more user friendly, can be easily added to
1 microcontroller. The user utilizes a keyboard to
specify which logic gate will be tested. Every
0
additional component functionality must be
1 implemented in the code, but it doesn’t require much
0 effort.
0
Subject to the above mentioned advantages, a
1 microcontroller is chosen to be used for testing the
functionality of a logic gate.
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 Figure 3: Pin arrangement of 7400 chip
Figure 4: Block structure of the system
V. SYSTEM STRUCTURE
The system consists of a microcontroller, a keyboard,
a display and some additional elements, such as zero
insertion force socket and an integrated chip whose
functionality is tested [1], [2]. Figure 4 shows a block
structure of the prototype. The central element is a
microcontroller. It communicates with a logic gate,
keyboard and display. Communications Microcontroller-
gate and microcontroller-keyboard are bidirectional,
unlike microcontroller-display which uses unidirectional
communication (a display is used only for displaying data
sent by microcontroller).
1. Power supply
Very important element of the developed system is
power supply. For this matter, 230V/50Hz AC voltage
is used. Microcontroller and logic gates demand 5V
DC for their power supply, therefore AC-DC
conversion is needed and the following elements are
used: filter, switch, fuse, transformer, rectifier and
regulator, resistors and capacitors (shown in Figure 8,
lower part).
2. Microcontroller
Microchip’s microcontroller PIC16F1939 is used for
this purpose [3].
3. Display
Liquid Crystal Display (LCD) AV1624 of ANAG
VISION is used for displaying results of logic gate
testing, as well as user-machine interaction. Two rows,
each with 16 characters can be displayed
simultaneously [4].
4. Keyboard
Using a keyboard, a user can enter a number of a
logic gate to be tested. The keyboard has 16 buttons
(4 rows and 4 columns) and eight pins. First four pins
represent rows, the rest represent columns. When a
button is pushed, pins corresponding the column and
MIPRO 2016/SP
Figure 5: Pin rearrangements of gates 7400, 7402, 7404, 7408 and
7432 and gate numeration inside the chip
the row of that button are on the same potential.
5. Zero insertion force socket
The zero insertion force socket (ZIF) is used to
simplify usage for users. In this case, ZIF with 20 pins
is used. An integrated chip, which is to be tested, is
put in ZIF. Afterwards, the chip cannot be pulled out
without moving the handle, there is a firm connection
between ZIF and the integrated chip.
6. Integrated circuit
Testing of aforementioned gates is done for this
matter. The following gates are used:
- 7400 - consists of four NAND gates with two inputs,
- 7402 - consists of four NOR gates with two inputs,
- 7404 - consists of six NOT gates,
- 7408 - consists of four AND gates with two inputs,
- 7432 - consists of four OR gates with two inputs.
Figure 5 shows pin rearrangements of listed gates.
VI. TESTING ALGORITHM
Testing algorithm is shown in Figure 6 via flow charts
[1].
VII. SOURCE CODE
The algorithm is developed in programming language
C, and written into the microcontroller. Code must include
functions for initialization of microcontrollers’ ports and
initialization and testing the functionality of
aforementioned gates, a function for identifying which
button on keyboard is pressed (if any) and the main
function in which, depending on the button pressed,
certain procedures are given.
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Figure 6: Testing algorithm of the prototype
A port (eight pins) connected with the keyboard is
initialized as half input and half output port. Integrated
chip to be tested is connected with two ports. The port
connected to LCD is the output port. Pins connected to the
integrated chip (via ZIF) are initialized as output pins if
corresponding pin of the chip is input, and vice versa. A
pin connected to power supply of the chip is declared as
output. All mentioned pins are digital outputs or inputs.
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Figure 7: Final design of the prototype
The procedure of functionality testing is described
earlier. Every gate is presumed to be without malfunction
until proven contrary. If for every combination of inputs,
output of gate is identical to the expected output, then the
gate is without malfunctions. If for at least one
combination of inputs, the output is different, then the gate
has a malfunction.
Checking whether any button is pressed is done by
checking whether two pins (one from first half and the
other from second) are on same potential, and that is done
by setting one by one, four output pins on logic one, and
testing if there is a logic one on any of input pins.
In the main function, depending on pressed button,
certain procedure is given. If a user enters more than six
digits that symbolize the gate’s name, an error message
will be written on LCD. If the gate name entered is not in
database (7400, -02, -04, -08 and -32), there will be an
error message.
VIII. FINAL PRODUCT
Figure 7 shows the final design of the prototype. In
Figure 8 complete electronic scheme of the prototype is
shown.
IX. CONCLUSION
In this paper, entire process of planning and
production of electronic device is given. First, theoretical
basis of logic gates, causes of malfunction and
malfunction diagnosis are explained. After that, thorough
analysis and planning software (programming code), as
well as hardware (electronic components) is made.
Functionality of code was checked, first through
simulation, and later by a number of experiments on a real
circuit. After numerous verifications, the final version of
code is obtained. Only after that, the device could be built,
and packed in a box. In that way, the prototype is simpler
and safer for usage. Final product can be commercialized,
and be very useful during laboratory assignments.
MIPRO 2016/SP
 Figure 8: Complete electronic scheme of the prototype

The prototype, besides for checking functionality of [2] A.A. Shinde, M.A. Tarkunde, “IC Tester Using 89s52
logic gates, can be used for identification of unknown 14- Microcontroller”, International Journal of Computational
Engineering Research, vol. 2, issue 7, pp.24-27, November 2012.
pinned logic gate from 74-series. It is advised to
[3] Microchip’s PIC16F1939 Microcontroller Datasheet,
implement functionalities for a larger number of logic http://ww1.microchip.com/downloads/en/DeviceDoc/40001574C.
gates through the programming code. pdf
[4] ANAG VISION’s AV1624 LCD Datasheet, http://www.iq-
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Engineering Sarajevo, Sarajevo, 2006.
Technology and Advanced Engineering, vol. 3, issue 6, pp.175-
178, June 2013. [6] Ž. Jurić, “Diskretna matematika za studente tehničkih nauka”,
Faculty of Electrical Engineering Sarajevo, Sarajevo, 2011.
[7] Dž. Hasanbegović, “Osnove tehničke dijagnostike digitalnih
sistema”, Svjetlost, Sarajevo, 1985.

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