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    2A.Syllabus BTES-302-18 DELAB

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    Gaurav Soni
    This document outlines the course plan for the Digital Electronics Lab course at Apeejay Institute of Management & Engineering Technical Campus for the third semester of the B-TECH Computer Science program. The course runs from July 2019 to November 2019 and includes 11 experiments covering topics like logic gates, adders, decoders, multiplexers, flip-flops, and counters. The faculty in charge of the course is Mr. Gaurav Soni and the course outcomes are for students to be able to realize combinational and sequential circuits using logic gates as well as various types of flip-flops and counters.

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    2A.Syllabus BTES-302-18 DELAB

    Uploaded by

    Gaurav Soni
    22 views2 pages
    This document outlines the course plan for the Digital Electronics Lab course at Apeejay Institute of Management & Engineering Technical Campus for the third semester of the B-TECH Computer Science program. The course runs from July 2019 to November 2019 and includes 11 experiments covering topics like logic gates, adders, decoders, multiplexers, flip-flops, and counters. The faculty in charge of the course is Mr. Gaurav Soni and the course outcomes are for students to be able to realize combinational and sequential circuits using logic gates as well as various types of flip-flops and counters.

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    This document outlines the course plan for the Digital Electronics Lab course at Apeejay Institute of Management & Engineering Technical Campus for the third semester of the B-TECH Computer Science program. The course runs from July 2019 to November 2019 and includes 11 experiments covering topics like logic gates, adders, decoders, multiplexers, flip-flops, and counters. The faculty in charge of the course is Mr. Gaurav Soni and the course outcomes are for students to be able to realize combinational and sequential circuits using logic gates as well as various types of flip-flops and counters.

    Copyright:

    © All Rights Reserved
    Download as DOCX, PDF, TXT or read online from Scribd
    Flag for inappropriate content
    Download as docx, pdf, or txt
    22 views2 pages

    2A.Syllabus BTES-302-18 DELAB

    Uploaded by

    Gaurav Soni
    This document outlines the course plan for the Digital Electronics Lab course at Apeejay Institute of Management & Engineering Technical Campus for the third semester of the B-TECH Computer Science program. The course runs from July 2019 to November 2019 and includes 11 experiments covering topics like logic gates, adders, decoders, multiplexers, flip-flops, and counters. The faculty in charge of the course is Mr. Gaurav Soni and the course outcomes are for students to be able to realize combinational and sequential circuits using logic gates as well as various types of flip-flops and counters.

    Copyright:

    © All Rights Reserved
    Download as DOCX, PDF, TXT or read online from Scribd
    Flag for inappropriate content
    Download as docx, pdf, or txt
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    Apeejay Institute of Management & Engineering Technical Campus, Jalandhar

    Course: B-TECH (CSE) Semester: 3rd

    Course Plan for Digital Electronics Lab

    BTES-302-18

    Course Outcomes-

    At the end of this course student will demonstrate the ability to:

    1. Realize combinational circuits using logic gates.

    2. Realize sequential circuits using logic gates.

    3. Realize various types of Flip-flops and counters

    List of Experiments:

    1. To verify the Truth-tables of all logic gates.

    2. To realize and verify the Half & full adder circuits using logic gates.

    3. To realize Half & fullsubtractor circuits using logic gates.

    4. To realize Encoder and Decoder circuits

    5. To realize Multiplexer circuits

    6. To realize 4-bit binary-gray & gray-binary converters.

    7. To realize comparator circuit for two binary numbers of 2-bit each.

    8. To realize Full adder & fullsubtractor circuits using encoder.

    9. To design Full adder & fullsubtractor circuits using multiplexer.

    10. To design and verify the Truth tables of all flip-flops.

    11. To design Mod-6/Mod-9 synchronous up-down counter.

    Faculty Incharge : Mr. Gaurav Soni


    Date of Submission: 03.08.2019

    Session : July 2019 - November 2019


    Session : July 2019 - November 2019

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