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CMOS Design of 2:1 Multiplexer Using Complementary Pass Transistor Logic

Conference Paper · March 2012

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 CMOS Design of 2:1 Multiplexer Using Complementary
Pass Transistor Logic
1
Diwaker Pant, 2Ankita Pandey, 3Rajesh Mehra
1, 2
ME (Regular), Department of Electronics and Communication Engineering, NITTTR
Chandigarh
3
Associate Professor, Department of Electronics and Communication Engineering, NITTTR
Chandigarh

E-mail: 1 diwaker.pant@gmail.com , 2 pandey3686ankita@yahoo.co.in

Abstract - This paper compares the use of complementary pass-transistor logic (CPL) as more power-
efficient than conventional CMOS design. However, new comparisons performed on more efficient
CMOS circuit realizations and demonstrate CPL to be superior to conventional CMOS in most cases
with respect to speed, area, and power-delay products. This is basically explained by the fact that CPL
gates uses less transistors, have smaller capacitances, and are faster than gates in complementary
CMOS. In this paper 2:1 Multiplexer is designed using the conventional CMOS design and CPL logic
design and the results are compared using Microwind and DSCH2 CMOS layout tools.
Keywords – CMOS, CPL, DSCH2, MUX.

I. INTRODUCTION

With advancements in large scale integration, millions of transistors can be placed on a single chip for
implementation of complex circuitry [1]. As a result of placing so many transistors in such a small
space, major problems of heat dissipation and power consumption have come into the picture. Research
has been conducted to solve these problems. Solutions have been proposed to decrease the power supply
voltage, switching frequency and capacitance of transistor Depending on the application, the kind of
circuit to be implemented, and the design technique used, different performance aspects become
important, disallowing the formulation of universal rules for optimal logic styles .

In this paper we have designed 2:1 MUX by using CMOS and CPL on MICROWIND/ DSCH2. Number
of transistors is less in CPL than in CMOS and hardware requirement is also low, other parameters are
area, speed, Power consumption and various parameters are compared for corresponding circuit. Various
parameters of 2:1 MUX are studied on the basis of CMOS and CPL technology. We have studied the
circuit on the basis of Mcrowind DSCH2 tools. Section II gives a brief description of conventional
CMOS design, section III describes Complementary pass transistor logic design. In section IV
conventional CMOS design is compared with Complementary Pass transistor logic by the help of
Microwind DSCH2 tool.

II. CONVENTIONAL CMOS LOGIC STYLE

The logic style used in circuits basically influence the speed, size, power dissipation, and the wiring
complexity of a circuit. The circuit delay is determined by the number of inversion levels, the number of
transistors in series, transistor sizes (i.e., channel widths), and intra- and inter-cell wiring capacitances.
Circuit size depends on the number of transistors and their sizes and on the wiring complexity (gate,
diffusion, and wire capacitances), the latter of which in turn is a function of the same parameters that
also control circuit size. Finally the wiring complexity is determined by the number of connections and
their lengths and whether single-rail or dual-rail logic is used. All these characteristics may vary
considerably from one logic style to another and thus make the proper choice of logic style crucial for
circuit performance [1].

Fig. 1 Schematic of 2:1 MUX using CMOS Logic in DSCH2

Logic gates in conventional or complementary CMOS (also simply referred to as CMOS in the sequel)
are built from an MOS pull-down and a dual PMOS pull-up logic network. Any logic function can be
realized by NMOS pull-down and PMOS pull-up networks connected between the gate output and the
power lines [2]. Non-monotonic gates, such as XOR and multiplexer, require more complex circuit
realizations but are still quite efficient. Other advantages of the CMOS logic style are its robustness
against voltage scaling and transistor sizing (high noise margins) and thus reliable operation at low
voltages and arbitrary (Even minimal) transistor sizes (ratio less logic) [3]. Input signals are connected to
transistor gates only, which facilitates the usage and characterization of logic cells. The layout of CMOS
gates is straightforward and efficient due to the complementary transistor pairs. Basically, CMOS fulfills
all the requirements regarding the ease-of-use of logic gates. An often mentioned disadvantage of
complementary CMOS is the substantial number of large PMOS transistors, resulting in high input loads
i.e. power, delay and area increased). In fig.1 schematic circuit diagram of 2:1 MUX using conventional
CMOS logic design is shown. Basic circuit uses the 12 MOS transistor [3] for performing multiplexers
operations. In fig. 2 shows the timing operation performed on 2:1 MUX conventional CMOS logic
design, the rise delay and fall delay calculated is 0.012 ns and 0.012 ns respectively.

Fig. 2 Timing Diagram of 2:1 MUX using CMOS Logic in DSCH2

After successful simulation, above designs are implemented using Microwind 3.1 CMOS layout tool for
its ease of use and availability. Microwind integrates traditionally separated front-end and back-end chip
design into an integrated flow, accelerating the design cycle and reduced design complexities. It tightly
integrates mixed-signal implementation with digital implementation, circuit simulation and verification.
The layouts are implemented in 90nm technology. Fig 3 shows the circuit layout of 2:1 MUX using

conventional CMOS logic design. The width of layout is 21.7 µm (434 lambda) and height is 7.0 µm
(140 lambda), Surface area is 151.9 µm2. Complete parametric analysis of conventional CMOS logic
design is given in section IV.
 Fig. 3 Layout of 2:1 MUX using CMOS in MICROWIND

III. COMPLEMENTRY PASS TRANSISTOR LOGIC STYLE

Traditionally, hand-crafted PTL has been successfully used to implement digital systems which are
smaller, faster, and more energy efficient than static CMOS implementations for the same designs.
The basic difference of pass-transistor logic compared to the CMOS logic style is that the source side
of the logic transistor networks is connected to some input signals instead of the power lines [5]. The
advantage is that one pass-transistor network (either NMOS or PMOS) is sufficient to perform the
logic operation, which results in a smaller number of transistors and smaller input loads, especially
when NMOS networks are used (power , delay and area decreased) [5]. However, lack of a systematic
methodology restricts the use of pass transistors in industry circuits.

Fig. 4 Schematic of 2:1 MUX using CPL in DSCH

Recently, there have been a number of attempts developing synthesis tools targeting PTL. It is common
to use this logic family for multiplexers and latches. Static and dynamic types of pass transistor logic
exist, with differing properties with respect to speed, power and low-voltage operation. As integrated
circuit supply voltages decrease, the disadvantages of pass transistor logic become more significant; the
threshold voltage of transistors becomes large compared to the supply voltage, severely limiting the
number of sequential stages. Because complementary inputs are often required to control pass transistors
additional logic stages are required. For proper operation, design rules restrict the arrangement of
circuits, so that sneak paths, charge sharing, and slow switching can be avoided, Simulation of circuits
may be required to ensure adequate performance. In fig. 5 shows the timing operation performed on 2:1
MUX CPL design, the rise delay and fall delay calculated is 0.005 ns and 0.004 ns respectively.

Fig. 5 Timing Diagram of 2:1 MUX using CPL in DSCH2

Fig. 6 shows the circuit layout of 2:1 MUX using CPL design. The width of layout is 11.3 µm (226
lambda) and height is 5.8 µm (116 lambda), Surface area is 65.5 µm2. Complete parametric analysis of
CPL design is given in section IV.

Fig. 6 Layout of 2:1 MUX using CPL in MICROWIND

 IV. PARAMETRIC ANALYSIS

S.N. Parameters Conventional CMOS PASS TRANSISTOR LOGIC

1 Width of Layout 21.7 µm (434 lambda) 11.3 µm (226 lambda)
2 Height Of Layout 7.0 µm (140 lambda) 5.8 µm (116 lambda)
3 Surface Area of Layout 151.9 µm2 65.5 µm2
4 Power Consumption 12.204 µW 1.381 µW
5 Rise Delay 0.012 ns 0.005 ns
6 Fall delay 0.012 ns 0.004 ns
7 No. of Transistor required 12 6

V. CONCLUSION

The advantages of high functionality with few pass-transistors and of small input capacitances in the
CPL style and less wiring overhead makes it better choice. The investigation result represented show
that for all simple and complex logic gates under realistic circuit conditions complementary Pass
transistor logic performs much better than complementary CMOS logic styles if low power
consumption, speed, area, delay (rise and fall) and number of MOS transistors are of concern. CPL also
compares favourably with regard to speed and layout efficiency. Test results validate simulations of 2:1
Multiplexer, that CMOS and CPL technologies has been compared both have their advantages and
disadvantages. It is seen that CMOS is good in reliability, but on the other side CPL has the benefits of
hardware reduction having lesser number of transistors (half in number approx.), reduces the circuit
delay, and less number of components reduces the area of layout up to 57 % approximately and power
consumption of the circuit.

REFERENCES

[1] A. P. Chandrakasan and R. W. Brodersen , “Low Power Digital CMOS Design, Kluwer,
Norwell MA. 1995.
[2] Neil Weste, Harris & Banerjee, CMOS VLSI Design: A Circuits and Systems Perspective, 3rd
Edition, Pearson Education, Boston, 2005, p1-16.
 [3] Zimmermann, R.; Fichtner, W.; “Low-Power Logic Styles: CMOS versus Pass-Transistor Logic”
IEEE Transaction on Solid-State Circuits, Volume 32, Page(s) 1079-1090, Publication Year:
1997
[4] Microwind user manual and DSCH user manual. Retrieved February 2012 from Microwind
commercial website: http://www.microwind.net.
[5] Zhou, H.; Aziz, A.; “Buffer Minimization in Pass Transistor Logic”, IEEE Transactions on
Computer-Aided Design of Integrated Circuits and Systems, Volume 20, Page(s ) 693-697, May
2001.

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