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  • DSP Experiment 4-2

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    Samarth
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    This document describes the implementation of an asymmetric 4-tap FIR filter using the C54x DSP and provides two methods: 1. A basic implementation using MPYM and MACM instructions to multiply input samples by coefficients and accumulate the results. 2. An optimized implementation using the FIRSADD instruction to simultaneously subtract, multiply, and add-accumulate input samples and coefficients in a single cycle. Both methods initialize registers and memory pointers, set up circular addressing mode for coefficients, and store the output in a repeating loop. The FIRSADD method processes two samples per cycle for improved performance.

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    Dsp experiment 4

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    This document describes the implementation of an asymmetric 4-tap FIR filter using the C54x DSP and provides two methods: 1. A basic implementation using MPYM and MACM instructions to multiply input samples by coefficients and accumulate the results. 2. An optimized implementation using the FIRSADD instruction to simultaneously subtract, multiply, and add-accumulate input samples and coefficients in a single cycle. Both methods initialize registers and memory pointers, set up circular addressing mode for coefficients, and store the output in a repeating loop. The FIRSADD method processes two samples per cycle for improved performance.

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    © All Rights Reserved
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    10 views3 pages

    DSP Experiment 4-2

    Uploaded by

    Samarth
    This document describes the implementation of an asymmetric 4-tap FIR filter using the C54x DSP and provides two methods: 1. A basic implementation using MPYM and MACM instructions to multiply input samples by coefficients and accumulate the results. 2. An optimized implementation using the FIRSADD instruction to simultaneously subtract, multiply, and add-accumulate input samples and coefficients in a single cycle. Both methods initialize registers and memory pointers, set up circular addressing mode for coefficients, and store the output in a repeating loop. The FIRSADD method processes two samples per cycle for improved performance.

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    © All Rights Reserved
    Download as PDF, TXT or read online from Scribd
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    of 3

    FIR Filter Implementation

    Madhukar kumar Deshant R. Fusate Agni swaroop


    2014EE10451 2014EE10436 2014EE10439
    A. Asymmetric FIR Filter (4-tap Filter)

    N .set 4
    M .set 4
    .mmregs
    .def start

    start
    BCLR C54CM
    BCLR AR0LC ;Linear Mode
    AMOV #010000h,XAR0 ;Starting Address for Input
    BCLR AR1LC ;Linear Mode

    AMOV #010020h,XAR1 ;Starting Address for Output


    BSET CDPLC ;Circular Addressing

    BSET SATD ;To Saturate Accumulator


    BSET FRCT ;To shift Accumulator left by one bit

    AMOV #000100h,XCDP ;Starting Address for coefficient

    MOV #0h,BSAC ;Offset for circular Addressing of CDP


    MOV #N,BKC ;Size of Block for Circular Addressing
    MOV #0,AC0

    MOV #(M+N-2),BRC0 ;Initializing for local block repeat


    MOV #N,T0 ;Offset to move pointer of AR0 back.

    RPTBLOCAL LOOP
    MPYM *AR0-,*CDP+,AC0

    RPT #N-3
    MACM *AR0-,*CDP+,AC0

    MACM *(AR0+T0),*CDP+,AC0
    LOOP MOV HI(AC0),*AR1+ ;Storing Output

    IDLE
    B. FIR Filter (Using FIRSADD)

    N .set 4;h
    M .set 4;x
    .mmregs
    .def start

    start
    BCLR C54CM
    BCLR AR0LC ;Linear Mode
    AMOV #01000h,XAR0 ;Starting Address for Input X
    AMOV #01000h-N+1,XAR2 ;Second Pointer for X
    BCLR AR1LC ;Linear Mode

    AMOV #010020h,XAR1 ;Starting Address for Output


    BSET CDPLC ;Circular Addressing
    BSET SATD ;To Saturate Accumulator
    BSET FRCT ;To shift Accumulator left by one bit
    AMOV #000100h,XCDP ;Starting Address for coefficient H
    MOV #0h,BSAC ;Offset for circular Addressing of CDP
    MOV #N/2,BKC ;Size of Block for Circular Addressing
    MOV #0,AC0
    MOV #0,AC1
    MOV #(M+N-2),BRC0 ;Initializing for local block repeat BR0+1 times
    MOV #N/2,T0 ;Offset to move pointer of AR0 back.
    RPTBLOCAL LOOP
    MOV #0,AC0
    MOV #0,AC1
    ADD *AR2+,*AR0-,AC0
    FIRSADD *AR2,*AR0,*CDP+,AC0,AC1
    MACM *CDP+,AC0,AC1
    MOV *(AR0+T0),*AR0
    LOOP MOV HI(AC1),*AR1+ ;Storing Output

    IDLE

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