Professional Documents
Culture Documents
ADC Architectures
ADC Architectures
Lecture 19
ADC Converters
– ADC architectures and design (continued)
• Flash ADC and its sources of error: comparator offset,
sparkle code & meta-stability
– Comparator design
• Single-stage open-loop amplifier
• Cascade of open-loop amplifiers
• Problem associated with DC offset
– Cascaded output series cancellation
– Input series cancellation
– Offset cancellation through additional input pair plus offset
storage capacitors
• Latched comparators
• Comparator examples
EECS 247 Lecture 19: Data Converters- Flash ADC- Comparator Design © 2009 Page 1
ADC Architectures
• Slope type converters
• Successive approximation
• Flash
• Time-interleaved / parallel converter
• Folding
• Residue type ADCs
– Two-step
– Pipeline
–…
• Oversampled ADCs
EECS 247 Lecture 19: Data Converters- Flash ADC- Comparator Design © 2009 Page 2
Flash ADC
• B-bit flash ADC:
– DAC generates all possible 2B -1
levels VREF VIN fs
EECS 247 Lecture 19: Data Converters- Flash ADC- Comparator Design © 2009 Page 3
1 1
Encoder
0
1
1
1
Ts 1
Time
EECS 247 Lecture 19: Data Converters- Flash ADC- Comparator Design © 2009 Page 4
Flash Converter Characteristics
VIN VREF fs
• Very fast: only 1 clock cycle
per conversion
– ½ clock cycleÆ VIN & VDAC
comparison
– ½ clock cycleÆ 2B -1 to B
Encoder
encoding
• High complexity:
2B-1 comparators
EECS 247 Lecture 19: Data Converters- Flash ADC- Comparator Design © 2009 Page 5
.. Output reference)
. – Signal dependent sampling
R time
R
• Comparator output:
R/2 – Sparkle codes (… 0001011111)
– Metastability
EECS 247 Lecture 19: Data Converters- Flash ADC- Comparator Design © 2009 Page 6
Flash ADC Converter
Example: 8-bit ADC Comparator Offset Considerations
VREF VIN fs
• 8-bitÆ 255 comparators
R/2
• VREF=1V Æ 1LSB=4mV R
R
• DNL<1/2LSB Æ
Comparator input referred .. Digital
Encoder
offset < 2mV .. Output
.
• Assuming close to 100% R
yield, 2mV =6σoffset
R
Æ σoffset < 0.33mV
R/2
EECS 247 Lecture 19: Data Converters- Flash ADC- Comparator Design © 2009 Page 7
EECS 247 Lecture 19: Data Converters- Flash ADC- Comparator Design © 2009 Page 8
Flash ADC Converter
Example (continued)
Trade-offs:
– Allowing larger DNL e.g. 1LSB instead of 0.5LSB:
• Increases the maximum allowable input-referred offset voltage by
a factor of 2
• Decreases the required device WxL by a factor of 4
• Reduces the input device area by a factor of 4
• Reduces the input capacitance by a factor of 4!
– Reducing the ADC resolution by 1-bit
• Increases the maximum allowable input-referred offset voltage by
a factor of 2
• Decreases the required device WxL by a factor of 4
• Reduces the input device area by a factor of 4
• Reduce the input capacitance by a factor of 4
EECS 247 Lecture 19: Data Converters- Flash ADC- Comparator Design © 2009 Page 9
Flash Converter
Maximum Tolerable Comparator Offset versus ADC Resolution
Assumption:
Maximum Comparator Voffset [mV]
102
DNL=0.5LSB
Note:
Graph shows 10 VREF=2V
max. tolerable
offset, note that VREF=1V
depending on min
1
acceptable yield,
the derived offset
numbers are
associated with 10-1
2σ to 6σ offset 4 6 8 10
voltage ADC Resolution
EECS 247 Lecture 19: Data Converters- Flash ADC- Comparator Design © 2009 Page 10
Typical Flash Output Encoder
VDD
Thermometer b3 Binary
code b2
1-of-n b1 B-bits
code b0
0 • Thermometer code
0 Æ 1-of-n decoding
0
• Final encoding Æ
1 NOR ROM
1
0 • Ideally, for each
1 code, only one ROM
row is on
0
1 b3 b2 b1 b0
Thermometer to Binary encoder ROM OutputÆ 0 0 1 1
EECS 247 Lecture 19: Data Converters- Flash ADC- Comparator Design © 2009 Page 11
Sparkle Codes
VDD
b3
Erroneous 0 b2
(comparator offset?) b1
b0
Correct Output:
0 1000
1
1 Problem: Two rows
0 are on
0
1 Erroneous Output:
1 1110
0
1
Æ Up to ~ ½ FS
error!!
EECS 247 Lecture 19: Data Converters- Flash ADC- Comparator Design © 2009 Page 12
Sparkle Tolerant Encoder
0 0
0 1
1 0
0 0
1 0
EECS 247 Lecture 19: Data Converters- Flash ADC- Comparator Design © 2009 Page 13
Meta-Stability
Different gates interpret
0 metastable output X differently
0
0 Correct output: 1000
1
X Erroneous output: 0000
1
1 Solutions:
0 –Add latches to comparator
1 outputs (high power)
–Gray encoding
Ref: C. Portmann and T. Meng, “Power-Efficient Metastability Error Reduction in CMOS Flash
A/D Converters,” JSSC August 1996, pp. 1132-40
EECS 247 Lecture 19: Data Converters- Flash ADC- Comparator Design © 2009 Page 14
Gray Encoding
Example: 3bit ADC
Thermometer Code Gray Binary
T7 T6 T5 T4 T3 T2 T1 G3 G2 G1 B3 B2 B1
0 0 0 0 0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 1 0 0 1 0 0 1 G1 = T1T3 + T5 T7
0 0 0 0 0 1 1 0 1 1 0 1 0
0 0 0 0 1 1 1 0 1 0 0 1 1
G2 = T2 T6
0 0 0 1 1 1 1 1 1 0 1 0 0 G3 = T4
0 0 1 1 1 1 1 1 1 1 1 0 1
0 1 1 1 1 1 1 1 0 1 1 1 0
1 1 1 1 1 1 1 1 0 0 1 1 1
EECS 247 Lecture 19: Data Converters- Flash ADC- Comparator Design © 2009 Page 15
Voltage Comparators
VDD
Vi+ +
Vout (Digital Output)
Vi- -
EECS 247 Lecture 19: Data Converters- Flash ADC- Comparator Design © 2009 Page 16
Voltage Comparator
Architectures
Comparator architectures:
• High gain amplifier with differential analog input & single-ended large
swing output
– Output swing has to be compatible with driving digital logic circuits
– Open-loop amplificationÆ no frequency compensation required
– Precise gain not required
• Sampled-data comparators
– T/H input
– Offset cancellation
EECS 247 Lecture 19: Data Converters- Flash ADC- Comparator Design © 2009 Page 17
1.8V
Av Mi n = ≈ 10,000
0.18mV
EECS 247 Lecture 19: Data Converters- Flash ADC- Comparator Design © 2009 Page 18
Comparator Design
1-Single-Stage Amplification
• Amplifier maximum Gain-Bandwidth product (fu) for a given technology,
typically a function of maximum device ft
f
fu = un i t y-g a i n f r e q uency, fo=- 3d B f r eq u en cy fo = u
AV
Example: fu=10 GHz & AV = 10,000
Magnitude
1 0GH z
fo = ≈ 1MHz
1 0,0 00 Av
1
τ set t li ng = = 0 . 16 μ s ec
2π fo fu=0.1-10GHz
A l l o w a f ew τ f or ou t p u t t o s et t l e
1 f0 fu freq.
fCMax.
l ock → ≈ 1 .2 6MHz
5τ s ett li ng Assumption: Single pole amplifier
Too slow for majority of applications!
Æ Try cascade of lower gain stages to broaden frequency of operation
EECS 247 Lecture 19: Data Converters- Flash ADC- Comparator Design © 2009 Page 19
Comparator Design
2- Cascade of Open Loop Amplifiers
One stage:
EECS 247 Lecture 19: Data Converters- Flash ADC- Comparator Design © 2009 Page 20
Open Loop Cascade of Amplifiers
EECS 247 Lecture 19: Data Converters- Flash ADC- Comparator Design © 2009 Page 21
EECS 247 Lecture 19: Data Converters- Flash ADC- Comparator Design © 2009 Page 22
Open Loop Cascade of Amplifiers
Offset Voltage
• Choice of # of
stage
Æbandwidth vs
offset tradeoff
Input-referred offset Æ
EECS 247 Lecture 19: Data Converters- Flash ADC- Comparator Design © 2009 Page 23
EECS 247 Lecture 19: Data Converters- Flash ADC- Comparator Design © 2009 Page 24
Open Loop Cascade of Amplifiers
Step Response
•Assuming linear behavior
EECS 247 Lecture 19: Data Converters- Flash ADC- Comparator Design © 2009 Page 25
Ref: J.T. Wu, et al., “A 100-MHz pipelined CMOS comparator ” IEEE Journal of Solid-State
Circuits, vol. 23, pp. 1379 - 1385, December 1988.
EECS 247 Lecture 19: Data Converters- Flash ADC- Comparator Design © 2009 Page 26
Offset Cancellation
Ref: J.T. Wu, et al., “A 100-MHz pipelined CMOS comparator ” IEEE Journal of Solid-State
Circuits, vol. 23, pp. 1379 - 1385, December 1988.
EECS 247 Lecture 19: Data Converters- Flash ADC- Comparator Design © 2009 Page 27
Offset Cancellation
Output Series Cancellation
• Amp modeled as ideal
+ Vos (input referred)
1- Store offset:
• S1, S4Î open
• S2, S3Æ closed
Æ VC=AxVOS
Ref: J.T. Wu, et al., “A 100-MHz pipelined CMOS comparator ” IEEE Journal of Solid-State
Circuits, vol. 23, pp. 1379 - 1385, December 1988.
EECS 247 Lecture 19: Data Converters- Flash ADC- Comparator Design © 2009 Page 28
Offset Cancellation
Output Series Cancellation
2- Amplification phase:
• S2, S3Æ open
• S1, S4Î closed
ÆVC=AxVOS
Circuit requirements:
• Amp not saturate during offset
storage
• High-impedance (C) load Æ Cc not
discharged
• Cc >> CL to avoid attenuation
• Cc >> Cswitch avoid excessive
additional offset due to charge
injection
EECS 247 Lecture 19: Data Converters- Flash ADC- Comparator Design © 2009 Page 29
Offset Cancellation
Cascaded Output Series Cancellation
EECS 247 Lecture 19: Data Converters- Flash ADC- Comparator Design © 2009 Page 30
Offset Cancellation
Cascaded Output Series Cancellation
VC1=A1xVos1
VC2=A2xVos2
VC3=A1xVos3
EECS 247 Lecture 19: Data Converters- Flash ADC- Comparator Design © 2009 Page 31
Offset Cancellation
Cascaded Output Series Cancellation
VX= ε3
VC1=A1xVos1- ε3
VC2=A2x(Vos2+ ε3)
EECS 247 Lecture 19: Data Converters- Flash ADC- Comparator Design © 2009 Page 32
Offset Cancellation
Cascaded Output Series Cancellation
3- S4Æ open
• Feedthrough from S4 Æ offset on Y
• Switch offset , ε4 induces error on node Y
• Since S5 remains closed, offset associated with ε4 Æ stored on C3
VY= ε4
VC2=A2x(Vos2+ ε3) – ε4
VC3=A3x(Vos3+ ε4)
EECS 247 Lecture 19: Data Converters- Flash ADC- Comparator Design © 2009 Page 33
Offset Cancellation
Cascaded Output Series Cancellation
VX = A1x(Vin+Vos1) – VC1
= A1x(Vin+Vos1) – (A1.Vos1- ε3)
=A1.Vin+ ε3
EECS 247 Lecture 19: Data Converters- Flash ADC- Comparator Design © 2009 Page 34
Offset Cancellation
Cascaded Output Series Cancellation
Vy = A2x(Vx+Vos2) – VC2
= A2x(A1Vin + ε3 + Vos2) – [A2.(Vos2+ε3) - ε4]
=A1.A2.Vin + ε4
EECS 247 Lecture 19: Data Converters- Flash ADC- Comparator Design © 2009 Page 35
Offset Cancellation
Cascaded Output Series Cancellation
Example:
3-stage open-loop differential amplifier with series offset cancellation +
output amplifier (see Ref.)
Ref: :R. Poujois and J. Borel, "A low drift fully integrated MOSFET operational amplifier," IEEE
Journal of Solid-State Circuits, vol. 13, pp. 499 - 503, August 1978.
EECS 247 Lecture 19: Data Converters- Flash ADC- Comparator Design © 2009 Page 36
Offset Cancellation
Output Series Cancellation
• Advantages:
– Almost compete cancellation
– Closed-loop stability not required
• Disadvantages:
– Gain per stage must be small
– Offset storage C in the signal path Æ could slow
down overall performance
EECS 247 Lecture 19: Data Converters- Flash ADC- Comparator Design © 2009 Page 37
Offset Cancellation
Input Series Cancellation
Ref: :R. Poujois and J. Borel, "A low drift fully integrated MOSFET operational amplifier," IEEE
Journal of Solid-State Circuits, vol. 13, pp. 499 - 503, August 1978.
EECS 247 Lecture 19: Data Converters- Flash ADC- Comparator Design © 2009 Page 38
Offset Cancellation
Input Series Cancellation
1- Store offset
Note: Mandates
closed-loop
stability
Ref: :R. Poujois and J. Borel, "A low drift fully integrated MOSFET operational amplifier," IEEE
Journal of Solid-State Circuits, vol. 13, pp. 499 - 503, August 1978.
EECS 247 Lecture 19: Data Converters- Flash ADC- Comparator Design © 2009 Page 39
Offset Cancellation
Input Series Cancellation
2- Amplify
S2, S3 Æ open
S1Æ closed
Example: A=4
ÆInput-referred
offset =Vos/5
EECS 247 Lecture 19: Data Converters- Flash ADC- Comparator Design © 2009 Page 40
Offset Cancellation
Cascaded Input Series Cancellation
⎡ Vos2 ε ⎤
Vout = A1A 2 ⎢ Vin + − 4⎥
⎣ A1 ( A 2 + 1) A1⎦
Vos2 ε
Input referred offset: − 4
A1 ( A 2 + 1) A1
EECS 247 Lecture 19: Data Converters- Flash ADC- Comparator Design © 2009 Page 41
Offset Cancellation
Input Series Cancellation
• Advantages:
– In applications such as C-array successive
approximation ADCs can use C-array to store
offset
• Disadvantages:
– Cancellation not complete
– Requires closed loop stability
– Offset storage C in the signal path- could slow
down overall performance
EECS 247 Lecture 19: Data Converters- Flash ADC- Comparator Design © 2009 Page 42
CMOS Comparators
Cascade of Gain Stages
Fully differential gain stages Æ 1st order cancellation of switch
feedthrough offset
EECS 247 Lecture 19: Data Converters- Flash ADC- Comparator Design © 2009 Page 43
CMOS Comparators
Cascade of Gain Stages
3-Combined input & output series offset cancellation
EECS 247 Lecture 19: Data Converters- Flash ADC- Comparator Design © 2009 Page 44
Offset Cancellation
• Cancel offset by additional pair of inputs
+ offset storage Cs + an extra clock
phase for offset storage (Lecture 18
slide 28 thru 30)
EECS 247 Lecture 19: Data Converters- Flash ADC- Comparator Design © 2009 Page 45
Latched Comparators
Vi+ Vi+ - Vi-
+ Vout
Vi - - (Digital Output)
t
Latch
Latch
Compares two input voltages
at time tx & generates a digital
output:
tx t
Vout
If Vi+ -Vi- > 0 Æ Vout=“1” “1”
If Vi+ -Vi- < 0 Æ Vout=“0”
“0”
t
EECS 247 Lecture 19: Data Converters- Flash ADC- Comparator Design © 2009 Page 46
CMOS Latched Comparators
Comparator amplification need not be linear
Æ can use a latch Æ regeneration
EECS 247 Lecture 19: Data Converters- Flash ADC- Comparator Design © 2009 Page 47
VDD VDD
M3 M4
M1 M2 M1 M2
EECS 247 Lecture 19: Data Converters- Flash ADC- Comparator Design © 2009 Page 48
CMOS Latched Comparators
Small Signal Model
Latch can be modeled as a:
Æ Single-pole amp + positive feedback
EECS 247 Lecture 19: Data Converters- Flash ADC- Comparator Design © 2009 Page 49
C ⎛ V2 ⎞
tD ≈ ln
g m ⎜⎝ V1 ⎟⎠
EECS 247 Lecture 19: Data Converters- Flash ADC- Comparator Design © 2009 Page 50
CMOS Latched Comparators
Normalized Latch Delay
C ⎛ V2 ⎞ V2 tD
tD ≈ ln AL =
g m ⎜⎝ V1 ⎟⎠ V1 C
gm
V2
→ Latch Gain = AL
V1
τD(3-stage amp)=
C 18.2(C/gm)
→ tD ≈ ln AL
gm
EECS 247 Lecture 19: Data Converters- Flash ADC- Comparator Design © 2009 Page 51
Latch-Only Comparator
• Much faster compared to cascade of open-
loop amplifiers
EECS 247 Lecture 19: Data Converters- Flash ADC- Comparator Design © 2009 Page 52
Pre-Amplifier + Latch
Overall Input-Referred Offset
fs
VosPreamp VosLatch
Vi+ Do+
Vi-
Av Latch
Do-
Preamp
2 1 2
σ Input − Re ferred _ Offset = σ Vos _ Pr eamp + 2
σ Vos _ Latch
APr eamp
Example : σ Vos _ Pr eamp = 4mV & σ Vos _ Latch = 50mV & APr eamp = 10
1
σ Input − Re ferred _ Offset = 42 + 502 = 6.4mV
102
EECS 247 Lecture 19: Data Converters- Flash ADC- Comparator Design © 2009 Page 53
Pre-Amplifier Tradeoffs
fs
Vi+ Do+
Vi-
Av Latch
Do-
Preamp
• Example:
– Latch offset 50 to 100mV
– Preamp DC gain 10X
– Preamp input-referred latch offset 5 to 10mV
– Input-referred preamplifier offset 2 to 10mV
– Overall input-referred offset 5.5 to 14mV
EECS 247 Lecture 19: Data Converters- Flash ADC- Comparator Design © 2009 Page 54
Comparator Preamplifier Gain-Speed Tradeoffs
• Amplifier maximum Gain-Bandwidth product (fu) or a given technology, typically a
function of maximum device ft
fu =unity gain frequency, f 0 = −3dB frequency & τ 0 = settling time
fu
f0 =
Apreamp
Magnitude
For example assuming preamp has a gain of 10:
fu 1GHz Av
f0 = = = 100 MHz
Apreamp 10 fu=0.1-10GHz
1 Apreamp
τ0 = = = 1.6n sec f0 fu freq.
2π f 0 2π fu
- Tradeoff:
• To reduce the effect of latch offset Æ high preamp gain desirable
• Fast comparator Æ low preamp gain
Æ Choice of preamp gain: compromise speed v.s. input-referred latch offset
EECS 247 Lecture 19: Data Converters- Flash ADC- Comparator Design © 2009 Page 55
Latched Comparator
fs
Vi+ Do+
Av Latch
Vi- Do-
Preamp
Important features:
– Maximum clock rate fs Æ settling time, slew rate, small signal bandwidth
– ResolutionÆ gain, offset
– Overdrive recovery
– Input capacitance (and linearity of input capacitance!)
– Power dissipation
– Input common-mode range and CMR
– Kickback noise
–…
EECS 247 Lecture 19: Data Converters- Flash ADC- Comparator Design © 2009 Page 56
Comparator Overdrive Recovery
Linear model for a single-pole amplifier:
EECS 247 Lecture 19: Data Converters- Flash ADC- Comparator Design © 2009 Page 57
If recovery time is not long enough to allow output to discharge (recover) from
previous state- then it may not be able to resolve the current input Æ error
To minimize this effect:
1. Passive clamp
2. Active restore
3. Low gain/stage
EECS 247 Lecture 19: Data Converters- Flash ADC- Comparator Design © 2009 Page 58
Comparators Overdrive Recovery
Limiting Output Voltage
Active Restore
Clamp
After outputs are latched by following stage
Adds parasitic capacitance
Æ Activate φR & equalize output nodes
EECS 247 Lecture 19: Data Converters- Flash ADC- Comparator Design © 2009 Page 59
C ⎛ V2 ⎞
τD ≈ ln
g m ⎜⎝ V1 ⎟⎠
C ⎛ V0 ⎞
τD ≈ ln
g m ⎜⎝ AvVin ⎟⎠
EECS 247 Lecture 19: Data Converters- Flash ADC- Comparator Design © 2009 Page 60
Latched Comparator Including Preamplifier
Example
VDD
M5 M3 M4 M6
-
Vo
CLK +
Preamplifier gain:
M1 M2
g mM 1 (VGS − Vth ) +
M3 M3
Av = = Vin M9
g mM 3 (VGSM 1 − VthM 1 ) -
bias M7 M8
Comparator delay:
(for simplicity, preamp delay ignored)
C ⎛ V0 ⎞
τD ≈ ln
g m ⎜⎝ AvVin ⎟⎠ Preamp Latch
EECS 247 Lecture 19: Data Converters- Flash ADC- Comparator Design © 2009 Page 61
CLK
TCLK
vO+
τdelay
vOUT
vO-
EECS 247 Lecture 19: Data Converters- Flash ADC- Comparator Design © 2009 Page 62
Comparator Resolution
CLK
VIN =10mV
1mV
0.1mV
vOUT 10μV
Δt = (gm/C).ln(Vin1/Vin2)
Note: For small Vin the comparator may not be able to make a
decision within the allotted time Æoutput ambiguous
EECS 247 Lecture 19: Data Converters- Flash ADC- Comparator Design © 2009 Page 63
VOffset
-0.5LSB 0.5LSB
Vin
EECS 247 Lecture 19: Data Converters- Flash ADC- Comparator Design © 2009 Page 64