Experiment 3: UNIVERSAL GATES

1.0 Objectives:
1.1 To be familiar with universal logic gates, the NOR and a NAND
gates.
1.2 To convert a logic function into a NOR and a NAND
implementation.
1.3 To construct the NOR and NAND implemented circuits in the
logic trainer.
1.4 To use the universal gates in minimizing the logic ICs used.

2.0 Theoretical Background

A universal logic gate is one which can implement any Boolean

function {0,1}, without the use of any other logic gate. Simply put, a
logic gate which can serve the function of ALL other logic gates,
including itself.

The NAND and NOR gates are called universal logic gates because all
the other gates can be created using these two.

A NAND gate is the NOT AND gate. The inverter bubble reverses the
output of the AND gate logic, giving a 0 output only when all inputs
are 1.

Figure 1. A NAND gate and its Equivalent Truth Table

A NOR gate is the NOT – OR gate. The inverter bubble reverses the
output of the OR gate logic giving 1 as the output only if all inputs are
0. It can have more than 1 input.

Figure 2. A NOR gate and its Equivalent Truth Table

These two universal gates can be used to replace the other gates, such
as NOT, AND, OR etc. By NAND and NOR implementation, the
equivalent gates will be:

Figure 3. NAND (left) and NOR (right) Implementation

 These universal gates are used for gate-level minimization. It is a task
for finding the simplest form of the function you are working on. The
goal of performing gate-level minimization is to see if the original
function can be further be simplified, and to know what is the minimal
number of gate and the number of IC that will be used.

3.0 Materials and Equipment

3.1 Logic ICs: 7400, 7402, 7404, 7432 and 7408
3.2 Logic trainer

4.0 Procedures, Data and Result

4.1 The group consider the following functions:

Y1 = A C’ + B’ D
Y2 = (A + D) (B’ + C’)

4.2 The group wrote the canonical forms of the two given functions.
Y1 (A, B, C, D) = ∑ (1, 3, 8, 9, 11, 12, 13)
Y1 (A, B, C, D) = Ⲡ (0, 2, 4, 5, 6, 7, 10, 14, 15)
Y2 (A, B, C, D) = ∑ (1, 3, 5, 8, 9, 10, 11, 12, 13)
Y2 (A, B, C, D) = Ⲡ (0, 2, 4, 6, 7, 14, 15)

4.3 The group draw the logic diagrams of Y1 and Y2 with IC part
numbers and pin numbers.
4.4 And the wiring diagram as well. Label everything.
Y1 = A C’ + B’

Figure 1. Logic diagram for Y1 = A C’ + B’ D

Figure 2. Wiring diagram for Y1 = A C’ + B’ D

 Figure 3. Actual experimental set-up for Y1 = A C’ + B’ D

Y2 = (A + D) (B’ + C’)

Figure 4. Logic diagram for Y2 = (A + D) (B’ + C’)

 Figure 5. Wiring diagram for Y2 = (A + D) (B’ + C’)

Figure 6. Actual experimental set-up for Y2 = (A + D) (B’ + C’)

4.5 The group constructed the logic circuit and completed the truth
table of Y1 and Y2 by indicating the logic states of the output

Table 1. Y1 = A C’ + B’ D and Y2 = (A + D) (B’ + C’)

ABCD Y1 Y2

0000 0 0

0001 1 1

0010 0 0

0011 1 1

0100 0 0

0101 0 1

0110 0 0

0111 0 0

1000 1 1

1001 1 1

1010 0 1

1011 1 1

1100 1 1

1101 1 1

1110 0 0

1111 0 0
4.6 The group implemented the use of universal gates on Y1 and Y2.
The group labeled the NAND implementation of Y1 and its NOR
implementation as Y1B and do the same for Y2, then, drew the
logic diagrams and wiring diagrams.

Figure 7. Logic diagram for Y1 = A C’ + B’ D (NAND)

Figure 8. Wiring diagram for Y1 = A C’ + B’ D (NAND)

Figure 10. Logic diagram for Y1 = A C’ + B’ D (NOR)

Figure 11. Wiring diagram for Y1 = A C’ + B’ D (NOR)

Figure 13. Logic diagram for Y2 = (A + D) (B’ + C’) (NAND)

Figure 14. Wiring diagram for Y2 = (A + D) (B’ + C’) (NAND)

Figure 17. Logic diagram for Y2 = (A + D) (B’ + C’) (NOR)

Figure 18. Wiring diagram for Y2 = (A + D) (B’ + C’) (NOR)

)
4.7 The group constructed the logic circuit and completed the truth
table of Y1A, Y1B, Y2A, and Y2B by indicating the logic outputs.

Table 2. Y1 = A C’ + B’ D and Y2 = (A + D) (B’ + C’)

ABCD Y1A Y1B Y2A Y2B

0000 0 0 0 0

0001 1 1 1 1

0010 0 0 0 0

0011 1 1 1 1

0100 0 0 0 0

0101 0 0 1 1

0110 0 0 0 0

0111 0 0 0 0

1000 1 1 1 1

1001 1 1 1 1

1010 0 0 1 1

1011 1 1 1 1

1100 1 1 1 1

1101 1 1 1 1

1110 0 0 0 0

1111 0 0 0 0
5.0 Observations, Conclusion and Recommendations

5.1 Observation

5.2 Conclusion

5.3 Recommendations

For the experiment to be finished earlier, every member should

construct the different given circuits on a breadboard and build the truth
table for the corresponding logic function.
6.0 Question and Answers

6.1. Why are NOR and NAND gates considered as universal

gates?

 A Logic Gate which can infer any of the gate among Logic Gates. OR
a gate which can be use to create any Logic gate is called Universal
Gate

NAND and NOR Gates are called Universal Gates because all the other
gates can be created by using these gates

 NAND gate to NOT Gate conversion

 NAND Gate to AND Gate Convertion

 NAND Gate to OR Gate Conversion

 NAND Gate to NOR Gate Convertion

 NAND to XOR Gate

 NAND to XNOR Gate

6.2 Explain the difference between 7400 and 7401, and between
7402 and 7403 logic ICs. Support your answers by including a
schematic diagram and or circuit application.

 7401 will not give the expected output, if the circuit is done as it is
done for 7400. Some extra components had to be added in 7401
circuit, which is internally included in 7400 chip. That is the pull
up resistor. In 7400, there is a built in pull up resistor. But in 7401
circuit, it should be included externally, because the outputs of
7401 are open collector as shown in the following diagram. That is,
major difference between 7400 and 7401 is the pull up resistor.
In 7400, current will be fixed through a particular load at a
particular voltage. So we will be forced to look for other methods, if
 this current is not sufficient to drive the load. But in 7401, simply
adjust the value of resistance to get the required load current.

The 7402 IC package contains four independent positive logic NOR GATES.
Pins 14 and 7 provide power for all four logic gates.
Outputs of one gate can be connected to inputs of another within the same
chip or to another chip as long as they share the same ground. The figure
to the left illustrates a basic circuit showing how to wire inputs and using
LEDs to display outputs.
NOR GATE Logic-Rules:
If one or both inputs are HIGH, then the output will be LOW. Otherwise,
output will be HIGH
The 7403 IC package contains four independent positive logic, open
collector, NAND GATES. Pins 14 and 7 provide power for all four logic
gates.

Outputs of one gate can be connected to inputs of another within the

same chip or to another chip as long as they share the same ground. The
figure to the left illustrates a basic circuit showing how to wire inputs
and using LEDs to display outputs.

NAND GATE Logic-Rules:

If both inputs are HIGH then the output will be LOW, otherwise output
will be HIGH.
6.3 Draw the equivalent 2-input NAND and NOR implementation of
the following. Also indicate the number of ICs used.
5.3.1 4 - Input AND

NAND (2 ICs)

NOR (3 ICs)
 4-input NOR

NAND (3 ICs)

NOR (2 ICs)
6.4 Draw the TTL and the CMOS equivalent circuits of the
followinguniversal gates. Discuss the circuit operation

6.4.1 NAND

Notice how transistors Q1 and Q3 resemble the series-connected

complementary pair from the inverter circuit. Both are controlled by the
same input signal (input A), the upper transistor turning off and the
lower transistor turning on when the input is “high” (1), and vice versa.
Notice also how transistors Q2 and Q4 are similarly controlled by the
same input signal (input B), and how they will also exhibit the same
on/off behavior for the same input logic levels. The upper transistors of
both pairs (Q1 and Q2) have their source and drain terminals paralleled,
while the lower transistors (Q3 and Q4) are series-connected. What this
means is that the output will go “high” (1) if either top transistor
saturates, and will go “low” (0) only if both lower transistors saturate. The
following sequence of illustrations shows the behavior of this NAND gate
for all four possibilities of input logic levels (00, 01, 10, and 11)

This schematic illustrates a real circuit, but it isn’t called a “two-input

inverter.” Through analysis we will discover what this circuit’s logic
function is and correspondingly what it should be designated as.

Just as in the case of the inverter and buffer, the “steering” diode
cluster marked “Q1” is actually formed like a transistor, even though it
isn’t used in any amplifying capacity. Unfortunately, a simple NPN
transistor structure is inadequate to simulate the three PN junctions
necessary in this diode network, so a different transistor (and symbol)
is needed.

6.4.2 NOR

Transistors Q1 and Q2 are both arranged in the same manner that we’ve
seen for transistor Q1 in all the other TTL circuits. Rather than
functioning as amplifiers, Q1 and Q2 are both being used as two-diode
“steering” networks. We may replace Q1 and Q2 with diode sets to help
illustrate

If input A is left floating (or connected to Vcc), current will go through

the base of transistor Q3, saturating it. If input A is grounded, that
current is diverted away from Q3‘s base through the left steering diode
of “Q1,” thus forcing Q3 into cutoff. The same can be said for input B
and transistor Q4: the logic level of input B determines Q4‘s
conduction: either saturated or cutoff.
Notice how transistors Q3 and Q4 are paralleled at their collector and
emitter terminals. In essence, these two transistors are acting as
paralleled switches, allowing current through resistors R3 and
R4 according to the logic levels of inputs A and B. If any input is at a
“high” (1) level, then at least one of the two transistors (Q3 and/or Q4)
will be saturated, allowing current through resistors R3 and R4, and
turning on the final output transistor Q5 for a “low” (0) logic level
output. The only way the output of this circuit can ever assume a
“high” (1) state is if both Q3 and Q4 are cutoff, which means both inputs
would have to be grounded, or “low” (0).
A CMOS NOR gate circuit uses four MOSFETs just like the NAND gate,
except that its transistors are differently arranged. Instead of two
paralleled sourcing (upper) transistors connected to Vdd and two
series-connected sinking (lower) transistors connected to ground, the
NOR gate uses two series-connected sourcing transistors and two
parallel-connected sinking transistors like this:
As with the NAND gate, transistors Q1 and Q3 work as a
complementary pair, as do transistors Q2 and Q4. Each pair is
controlled by a single input signal. If either input A or input B are
“high” (1), at least one of the lower transistors (Q3 or Q4) will be
saturated, thus making the output “low” (0). Only in the event
of both inputs being “low” (0) will both lower transistors be in cutoff
mode and both upper transistors be saturated, the conditions
necessary for the output to go “high” (1). This behavior, of course,
defines the NOR logic function.
7.0 References

Kuphaldt, Tony (2007). TTL NAND and AND gates. Logic gates. Lessons in Electric Circuit Vol. IV
- Digital. Chap.3. Retrieved January 21, 2017, from http://www.allaboutcircuits.com

Kuphaldt, Tony (2007). TTL NOR and OR gates. Logic gates. Lessons in Electric Circuit Vol. IV -
Digital. Chap.3. Retrieved January 21, 2017, from http://www.allaboutcircuits.com

Kuphaldt, Tony (2007). CMOS Gate Circuitry. Logic gates. Lessons in Electric Circuit Vol. IV -
Digital. Chap.3. Retrieved January 21, 2017, from http://www.allaboutcircuits.com

Futurlec (n.d). 7402 - 7402 Quad 2-Input NOR Gate Datasheet. Retrieved January 21, 2017, from
http://www.futurlec.com/74/IC7402.shtml

Futurlec (n.d). 7403 - 7403 Quad 2-Input NAND Gate with Open Collector Ouptut Datasheet.
Retrieved January 22, 2017, from http://www.futurlec.com/74/IC7403.shtml

Realfinetime electronics (05:22). How 7401 Quad 2-Input NAND Gate Differ from 7400
Quad 2-Input NAND Gate?.[Blog Post]. Retrieved January 22, 2017, from
http://www.learnerswings.com/2014/07/how-7401-quad-2-input-nand-gate-
differ.html

8.0 Member’s Participation

Diamante, Sharmaine Imari M. Procedures and drawings

Iizuka, Sakiko A. Question & answer and references
Ramos, Eril G. Theoretical Background
Salvador, Mark Angelo B. Conclusion and Observation
Villanueva, Julius Benito D. Recommendation

9.0 Appendices
Appendix A (Data Sheets for ICs Used)