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Calculate The Value of VDS
Calculate The Value of VDS
A. 0V
B. 0.35 V
C. 3.8 V
D. 33.5 V
Answer: Option C
A. 0V
B. 8V
C. 4.75 V
D. 16 V
Answer: Option D
3. Given the values of VDQ and IDQ for this circuit, determine the required values of RD and RS.
A. 2 k, 2 k
B. 1 k, 5.3 k
C. 3.2 k, 400
D. 2.5 k, 5.3 k
Answer: Option C
B. 5.167 k
C. 6.167 k
D. 6.670 k
Answer: Option B
5. For the FET, the relationship between the input and output quantities is ________ due to the
________ term in Shockley's equation.
A. nonlinear, cubed
B. linear, proportional
C. nonlinear, squared
Answer: Option C
A. 10 M
B. 100 M
C. 110 M
D. 220 M
Answer: Option B
B. A resistor RS is added.
Answer: Option D
8. The input controlling variable for a(n) ________ is a current level and a voltage level for a(n)
________.
A. BJT, FET
B. FET, BJT
C. FET, FET
D. BJT, BJT
Answer: Option A
9. Through proper design, a ________ can be introduced that will affect the biasing level of a
voltage-controlled JFET resistor.
A. photodiode
B. thermistor
C. laser diode
D. Zener diode
Answer: Option B
10.
For what value of RS can the depletion-type MOSFETs operate in enhancement mode?
A. 2.4 k
B. 5k
C. 6.2 k
Answer: Option C
11. On the universal JFET bias curve, the vertical scale labeled ________ can, in itself, be used to
find the solution to ________ configurations.
A. m, fixed-bias
B. M, fixed-bias
C. M, voltage-bias
D. m, voltage-bias
Answer: Option A
B. 1.68 k
C. 6.81 k
D. 8.5 k
Answer: Option B
A. 2k
B. 3k
C. 3.5 k
D. 4.13 k
Answer: Option D
14. At what value of RS does the circuit switch from depletion mode to enhancement mode?
A. 250
B. 500
C. 10 M
Answer: Option A
15.
A. IG = ID
B. IG = IS
C. ID = IS
D. IG = ID = IS
Answer: Option C
B. 1.50 V
C. 2.56 V
D. 3.58 V
Answer: Option D
A. –3 V
B. 3V
C. –4 V
D. 4V
Answer: Option A
18. Which of the following represents the voltage level of VGS in a self-bias configuration?
A. VG
B. VGS(off)
C. VS
D. VP
Answer: Option C
19. The self-bias configuration eliminates the need for two dc supplies.
A. True
B. False
Answer: Option A
20. Which of the following is a false statement regarding the dc load line when comparing self-
bias and voltage-divider configurations?
D. Both are obtained by writing Kirchhoff's voltage law (KVL) at the input side loop.
Answer: Option B