TMS4116 16,384-BIT DYNAMIC RANDOM-ACCESS MEMORY OCTOBER 1977-REVISED NOVEMBER 18 16,384 X 1 Organization 10% Tolerance on All Supplies {Ail Inputs Including Clocks TTL Compatible Unlatched Three-State Fully TTL-Compatibie ‘Output © Performance Ranges: ACCESS ACCESS READ READ: TIME TIME OR MODIFY. ROW COLUMN WRITE WRITE’ [ADDRESS ADORESS CYCLE CYCLE AMAX) (MAX) (MIN) (MIN) TMsest6-18 sone W0Ons 375 ns 375.09 Tweett620 2000 198m A758 375 ne FN NOMENCLATURE Juseti623 250m TeSan 410 ne 515 mt rey © Page-Mode Operation for Faster Acco: os Column Adress Sr0b0 Time > Data nowt : a ate Outpt © Common 1/0 Capebilty with Early Write me ee Fosture vee =5.V Power Supe © Low-Power Dissipation vee 5: Power Suny = Operating . . . 462 mW (Max) Yoo 1247 Powar Sup = standby . | 20 mW (Max) ss Ground w Write Enable ‘© 1-1 Colt Design, N-Channel Siicon-Ga Technology © 16-Pin 300-Mil (7,62-mm) Package Configuration description ‘The TMS4116 series is composed of monolithic high-speed dynamic 16,384-bit MOS random-eccess memories organized as 16,384 one-bit words, and employs single-transistor storage cells and N-channel silicon-gate technology. {Allinputs end outputs are compatible with Series 74 TTL circuits including clocks: Row Address Strobe RAS for Ri and Column-Address Strobe CAS or C). All address lines (AO through A6) and data in (D) ar latched on chip to simplify system design, Data out (Q) is unlatched to allow greater system flexibility. ‘Typical power dissipation is less than 360 milliwatts active and 6 milliwatts during stendby {Vcc Is not required during standby operation). To retain data, only 10 milliwatts average power is required which includes the power consumed to refresh the contents of the memory. ‘The TMS4116 series is offered in a 16-pin dual-ir operation from 0°C to 70°C. The package (300-mil) centers. plastic (N suffix) package and is guaranteed for designed for insertion in mounting-hole rows on 7,62-mm. ‘operation address (A0-A8) Fourteen address bits are required to decode 1 of 16,384 storage cell locations. Seven row-address bits ‘are set up on pins AO through A6 and latched onto the chip by the row-address strobe (RAS). Then the ‘te term “raad-write cycle" s sometimes used ex en alternative 0 ” modity-write eye.” conan © TEXAS. & INSTRUMENTS: Dynamic RAMs a‘TMS4116 44 16,384-BIT DYNAMIC RANDOM-ACCESS MEMORY seven column-address bits are set up on pins AO through AG and latched onto the chip by the column- ‘address strobe (CAS). All addresses must be stable on or before the falling edges of RAS and CAS. RAS is similar to a chip enable in that it activates the sense amplifiers as well as the row decoder. CAS is used as a chip select activating the column decoder and the input and output buffers. write enable (W) ‘The read or write mode is selected through the write-enable (W) input. A logic high on the W input selects ‘the read mode and a logie low selects the write mode. The write-enable terminal can be driven from standard TTL circuits without a pull-up resistor. The data input is disabled when the read mode is selected. When W goes low prior to CAS, data out will remain in the high-impedance state for the entire cycle permitting ‘common 1/0 operation. data in (B) Datais written during a write or ead-modity-write cycle. Depending on the mode of operation, the faling edge of CAS or W strobes data into the on-chip data latch. This latch can be driven from standard TTL Cireuits without 2 pullup resistor. In an early write cycle, W is brought low prior to GAS and the data is strobed in by CAS with setup and hold times referenced to this signal. In a delayed-write or read-modity write cycle, CAS will already be low, thus the data willbe strobed in by W with setup and hold times referenced to this signal. data out (Q) The three-state output buffer provides direct TTL compatibility (no pull-up resistor required) with a fan out of two Series 74 TTL loads. Data out isthe same polarity as data in. The output iin the high mpedance {footing} state unt CAS is brought low. In a ead cyce, the ovtput goes active after the enable ime interval ta(c) that begins with the negative transition of CAS as long as tea is satisfied. The output becomes Vald after the access time has elapsed and remains valid while CAS is low; CAS going high returns it to a high-impedance state. In an early write cycle, the output is always in the high-impedance stete. In a delayed-write or read-modify write cycle, the output will follow the sequence for the read cycle refresh A refresh operation must be performed at least every two milliseconds to retain data. Since the output buffer is in the high-impedance state unless CAS is applied, the RAS-only refresh sequence avoids any ‘output during refresh. Strobing each of the 128 row addresses (AO through A6) with RAS causes all bits in each row to be refreshed. CAS remains high (inactive) for this refresh sequence, thus conserving power. page mode Page-mode operation allows effectively faster memory access by keeping the same row address and strobing successive column addresses onto the chip. Thus, the time required to setup and strobe sequential row ‘addresses on the same page is eliminated. To extend beyond the 128 column locations on a single RAM, the row address and RAS is applied to multiple 16K RAMs; CAS is decoded to select the proper RAM. power up VB must be applied to the device either before or at the same time as the other supplies and removed last. Failure to observe this precaution will cause dissipation in excess of the absolute maximum ratings {due to internal forward bias conditions. This also applies to system use, where failure of the Vag supoly must immediately shut down the other supplies. After power up, eight RAS cycles must be performed to achieve proper device operation. TEXAS. %» INSTRUMENTSTMS4116 16,384-BIT DYNAMIC RANDOM-ACCESS MEMORY RAM 76K XT 2007/2100 G23/[REFRESH ROW! 24{PWR DWN} c2t1CoL) "This symbol isin accordonce with ANSIIEEE Std 91-1984 and IEC Publication 617-12. functional block diagram Texas % 4 INSTRUMENTS : Dynamic RAMs 8TMS4116 16,384-BIT DYNAMIC RANDOM-ACCESS MEMORY absolute maximum ratings over operating free-air temperature range (unless otherwise noted)t Voltage on any pin (see Note 1) 0.5 V 10 20V Voltage on Vcc, Vop supplies with respect to Vss -1Vt0 15V Short circuit output current eee : ~ 50 mA Power dissipation ee 1W Operating free-air temperature range += 0° to 70°C Storage temperature range . . eee “65°C to 150°C 1 Stresses beyond thos ited under only and functional operation ofthe device at these or eny other conditions beyond thos "1 Conditions section of this specticetion snot implied. Expacure to sbaclute-maximum-ated conditions fr extended pariods may affect device rebablty NOTE 1: Under absolute maximum ratings, voltage values are wth respect to the most negative supply voltage, Vag (eubstrate, unless ‘therwiee noted. Throughout the remainder of this date sheet, voltage vais ate with respect to sg. recommended operating conditions MW _NOM MAX | OWT Vas Supniy voraoe =p 5-68] Veg Svppiv vorage as ss Von Svpply vortege Toa 2 a2 |v Veg Supply voltage @ v Vin High evel ngut wotage Al inoute except FAS, ES, WRITE, a zy y AS, CAS, WRITE 27 7 Vi towel np vottage eve Nate 21 =e ee “Ta Operetng free. temperture 2 To 6 NOTE 2: The algebraic convention, whera the more negative le logic voltage ony positive) imi is designated as maximum, is used in this datasheet for exas 8 Th INSTRUMENTS‘TMS4116 16,384-BIT DYNAMIC RANDOM-ACCESS MEMORY “Jectrical characteristics over full ranges of recommended operating conditions (unless otherwis® noted) PARAMETER, TEST CONDITIONS: win Tye? max [ UNIT Vou High evel output voltage Tow = 5 mA, 24 v [Wor _tewievel ouput voltage lot = 4.2 ma. ony Wy Input current daskege! eae 10 | 0 All other ping = 0'V except Vgp ~ -8.V fo Output current leakege! Yo = 0 68. 210 | 0A TKS high X 0200) [HEEL] somes onwatencuret pneu eyo time ae Fie sung en or wt vee toe ‘p52, 10100 | oA cca | Stendby curent plaice Zio | an FAS and CAS high eee | top2 os 18 | ma, "p03, ‘inimom evel tine 50200 | oA cca | Average rtresh cuerent FES cycling 10 | oA, [too3 TRS nish 227 | ma "eB. Minimum eye time 50200 | A Tecat) Average pagemade curent | RAS low. ma pos. THB eyeing 2027 | ma 1 All typical values are et Ta ~ 2680 and nominal supply voltages. 1 yee ie applies only to the outbut buter, 80 Ig depends en output loading § Output loading two standard TTL loads. c2pactance over recommended supply voltage range and operating free-lr temperature range, f 1MHz PARAMETER, ve? MAX [ UN Tiny lant eapectance, address inputs «_5| oF Cap) noe capacitance, data put 48] oF ‘Cunicy_ Inout capacitance, eabe input 3 oF Guy) Input capacitance, wre eneble input a] Co, ‘Output eapectance 57 Lr witching characteristics over recommended supply voltage range and operating free-sk temperature range , ur. [rmsaii6-16 | Tusa116.20 | Tw56116.26 »ARAMETER est conormions | geo, MIN MAX] MIN WAX [ MIN unit GL = 1009. tic) Accesstime from TAS | Load = 2Seres | Ac 100 138 165 | ns 74 TT gotos ‘ruc = MAX. CL = 100 oF ath) Access te trom FAS. " 1 oe : " Lond = 2 Series, ae te 200 280 74 TTL gates — vaecny OU s0! ee et WICH) te CHS high Cl o 4| 0 s0| 0 60} ns Dynamic RAMs B 5 oe at Ta = 26°C and nominal supply volteges. % TEXAS. INSTRUMENTS a7TMS4116 16,384-BIT DYHAMIC RANDOM-ACCESS MEMORY —_—_——_—_$ $$ timing requirements over recommended supply voltage range and operating free-air temperature range na [-awsae. | ows 2016.25 | ayy vou "anu Yan wax [MIN Ma Tap Pera or oe fee | 70 i a = re yore ‘ae 378 375 0 7 EA ton noah wane [376 35 5 = tet Pe Stor, C5 Teas | 100 Tom80 | Tae 10666 | vos 10060 | tui) Pav Son, FS hgh rahe er] — | 109, 729 is rm tet) Pas don, FS ion inas_[ 150” Ta000 | 200 10,000 | 280" To. | ne et ie pas ton ae % 7 1 oa wpa [a «| 2 «| = Tay cao oe se | = = = Se new ars a ‘ise 3 2 7 fan ST cela 2 a ¥s ier 8 Sea vom | © 700 = 0) eee wm | © % 100 = Sao aS wmicay umes Pld ene wan | 98 120 160 = TRIGLD | Date hota time after CAS Tow tone | 35 7 rm ToL On ho tne ar I oe ‘eee 5 7 ie = TOWED] Data hold time afior Wiow: tow | 45 55 75 78 Te Rod connand hl re ero 2 2 = a ‘wen | 48 s 75 7 sa eee ee wen | 98 ve 10 7 ‘ncn ony tne, PASIow w ERS | sesu | 150 200 0 A ‘cnet ne, CAT nah RAS ow | come | ~20 =20 <2 = ‘cu On tine, CHT iow to WE ner | ngs | 100 73s ies = On te, EX owt Ww ACLWL (90d modify write-cyela only) sown | 70 Gd a ss smucr__ tnt vn ote wee ee iy te AE To to Wow TRLWL _(road-modity-write-cycle only! ee ad ee s tact ey ee ey wes | -20 “0 7 aa a aE 3 z zh exas Ti INSTRUMENTS:TMS4116 16,384-BIT DYNAMIC RANDOM-ACCESS MEMORY read cycle timing sg an vu ms h le ' Mu i ae Sea nto —O| fe ton | No r os vm “roa I fe— twicn —o] neucal ier \ won EKO EO ee ees | | aaa | ee a Xpotnee 1 RXTE : | je 144 | | K—t}revon Dynamic RAMs 8 TEXAS. ¥ 49 INSTRUMENTSTMS4116 16,384-BIT DYNAMIC RANDOM-ACCESS MEMORY early write cycle timing ae | { an I i, rere a en + crm —o| —t Sah smell ifm 4h — wen —a lees —o sn fet | fe epacicn | | rons RAY ow AD coun AEKR ISS SENN R Xt ore Te coal | = ! ta Hho) TEXAS % INSTRUMENTS vu Mu vin Mn vu Mn Vou‘TMS4116 16,384-BIT DYNAMIC RANDOM-ACCESS MEMORY write cycle timing sw geal | > WE eecas if sion a] —“* mw ay Teal een li sone TRY row PED coum ERK GT CNR KNOT erate YM (ee = . © XE AX STE XXX { lal toe 1 = sto} aes | ° COKER, vase one RAEI . Hew lef seon | ! Dynamic RAMs 8 Vou You We tie itp) for 8 write cycle is equal in duration to the access time from TAB ital in # reed eyes: but the seme active ‘the output are invalid a TEXAS, INSTRUMENTSTMS4116 16,384-BIT DYNAMIC RANDOM-ACCESS MEMORY road-write/read-modity-write cycle timing a | ms >_____ “ fel ay | je baa — | Heron vm 8 | t ee vo bm = ee g shina) \f ‘wicica) 3 or ae, SEED ~ 5 aoa “eine 2 wena 3 : | | sr 2 w Xioureae KY ‘“ ee a fo fsa i | aS | | : ROO oe OR = | | wwf eof smn —ee 412 Teas YB INSTRUMENTS,‘TMS4116 16,384-BIT DYNAMIC RANDOM-ACCESS MEMORY Bons amet | onal | | ditto | om} ore yf r | 7 be rom —al ie wio,-ol | Komp a wommbesy | samen leo | | ae) | ke Sao 1 omy ey ie | com | - bal 4 (worn, ple a | bot TEXAS % iSTRUMENTS In page-mode read cycle timing sano. — a ape 7 Hy = _—16,384-BIT DYNAMIC RANDOM-ACCESS MEMORY page-mode write cycle timing TMS4116 i Dynamic RAMsS4116 TM 16,384-BIT DYNAMIC RANDOM-ACCESS MEMOR' RAS-only refresh timing vn reo “ TT | r | | oS RESTS | CMM TERT IOAN we fess pease) none QP EER PO” RKO SM OKRA? “ & KKXKKXXLAAXK KK PHT SE KKK RA AKKAXAKY i Vou Vou YY Dynamic RAMs 5TMS4116 16,384-BIT DYNAMIC RANDOM-ACCESS MEMORY CYCLE RATE (& TIMED ‘TEMPERATURE te(rd) Cycle Time—ns. 375 300 250 sIyy oqweudg A of CYCLE RATE (& TIME) MAX SUPPLY CURRENT, Ipp1 te{rd)—Cycle Time—ns 375 1000 _ 00 400| 300 260 50 mA 2 :” t ‘| a E40 mal : KS £ 6 L : 20mA = 1 2 3 4 : 103/te(rd)—Cyole Rate—MHz ae 20marg i 10 ma +4 3 a ° (Ogeatgeeei2\eenisesssr4 103te(rd)— Cycle Rat CYCLE RATE (& TIME) PAGE-MODE CYCLE RATE (& TIME) vs vs MAX SUPPLY CURRENT, IoD3 MAX SUPPLY CURRENT, InD4 teird)— Cycle Time—ns 1000 500400 300 250 50 ma 1000590400 200 250 oan 00 30 < i i E40 mal £40 mal g : é 3 = 30m zg om a a 20 mal 4 20 ma| i i = toma gr 8 8 ° o o 1 2 3 4 10%aie— Cycle Rato—MHz o 1 2 3 4 107tc{p)—Page-Mode Cycle Rato—MHz TEXAS % INSTRUMENTS