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Datasheet PDF
Datasheet PDF
Datasheet PDF
Description
M66311P/FP is a LED array driver having a 16 bit serial-input and parallel output shiftregister function with direct
coupled reset input and output latch function.
This product guarantees the output electric current of 24 mA which is sufficient for anode common LED drive, capable
of flowing 16 bits continuously at the same time.
Parallel output is open drain output.
In addition, as this product has been designed in complete CMOS, power consumption can be greatly reduced when
compared with conventional BIPOLAR or Bi-CMOS products.
Furthermore, pin lay–out ensures the realization of an easy printed circuit.
Features
• Anode common LED drive
• High output current all parallel output IOL = 24 mA simultaneous lighting available
• Low power dissipation: 100 µW/package (max)
(VCC = 5 V, Ta = 25°C, quiescent state)
• High noise margin
schmitt input circuit provides responsiveness to a long line length.
• Equipped with direct-coupled reset
• Open drain output
(except serial data output)
• Wide operating temperature range: Ta = −40 to +85°C
• Pin lay-out facilitates printed circuit wiring. (This lay-out facilitates cascade connection and LED connection.)
Application
LED array drive of BUTTON TELEPHONE
LED array drive of ERASER of a PPC copier
Other various LED modules
Logic Diagram
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
CK CK CK CK CK CK CK CK CK CK CK CK CK CK CK CK
D S D S D S D S D S D S D S D S D S D S D S D S D S D S D S D S
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
CK CK CK CK CK CK CK CK CK CK CK CK CK CK CK CK
D S D S D S D S D S D S D S D S D S D S D S D S D S D S D S D S
5 4 8 7 6 9
OE A CKS R CKL GND
Enable Serial Shift Direct Latch
input data clock reset clock
Parallel
input Serial data input input input
data output
output
Output format
Pin Arrangement
M66311P/FP
Parallel data QA ← 1 QA QC 24 → QC
outputs QB ← 2 QB QD 23 → QD
VCC 3 QE 22 → QE
Enable input OE → 5 OE QG 20 → QG
GND 9 QK 16 → QK
Parallel data QO ← 11 QO QM 14 → QM
outputs QP ← 12 QP QN 13 → QN
(Top view)
Functional Description
As M66311P/FP uses silicon gate CMOS process, it realizes high-speed and high-output currents sufficient for LED
drive while maintaining low power consumption and allowance for high noises.
Each bit of a shiftregister consists of two flip–flops having independent clocks for shifting and latching.
As for clock input, shift clock input CKS and latch clock input CKL are independent from each other, shift and latch
operations being made when “L” changes to “H”.
Serial data input A is the data input of the first–step shiftregister and the signal of A shifts shifting registers one by one
when a pulse is impressed to CKS. When A is “H”, the signal of “L” shifts.
When the pulse is impressed to CKL, the contents of the shifting register at that time are stored in a latching register,
and they appear in the outputs from QA to QP.
Outputs from QA to QP are open drain outputs.
To extend the number of bits, use the serial data output SQP which shows the output of the shifting register of the 16th
bit.
If CKS and CKL are connected, the state of the shifting register with one clock delay is outputted to QA to QP.
When reset input R is changed to “L”, QA to QP and SQP are reset. In this case, shifting and latching registers are set.
If “H” is impressed to output enable input OE, QA to QP reaches the high impedance state, but SQP does not reach the
high impedance state. Furthermore, change in OE does not affect shift operation.
Serial
Input Parallel Data Output Data
Output
Operation Mode R CKS CKL A OE QA QB QC QD QE QF QG QH QI QJ QK QL QM QN QO QP SQP Remarks
Reset L X X X X Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z L –
Shift Shift t1 H ↑ X H L QA0 QB0 QC0 QD0 QE0 QF0 QG0 QH0 QI0 QJ0 QK0 QL0 QM0 QN0 QO0 QP0 qO0 Output
lighting
latch Latch t2 H X ↑ X L L qA0 qB0 qC0 qD0 qE0 qF0 qG0 qH0 qI0 qJ0 qK0 qL0 qM0 qN0 qO0 qO0 "H"
operation Shift t1 H ↑ X L L QA0 QB0 QC0 QD0 QE0 QF0 QG0 QH0 QI0 QJ0 QK0 QL0 QM0 QN0 QO0 QP0 qO0 Output
lights-out
Latch t2 H X ↑ X L Z qA0 qB0 qC0 qD0 qE0 qF0 qG0 qH0 qI0 qJ0 qK0 qL0 qM0 qN0 qO0 qO0 "L"
Output disable X X X X H Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z qP –
Electrical Characteristics
(VCC = 4.5 to 5.5V, unless otherwise noted)
Sy Limits
mb Ta = 25°C Ta = −40 to +85°C
Item ol Min Typ Max Min Max Unit Conditions
Positive-going VT+ 0.35×VCC — 0.7×VCC 0.35×VCC 0.7×VCC V VO = 0.1 V, VCC−0.1 V
threshold IO = 20 µA
voltage
Negative-going VT– 0.2×VCC — 0.55×VCC 0.2×VCC 0.55×VCC V VO = 0.1 V, VCC−0.1 V
threshold IO = 20 µA
voltage
Low-level VOL — — 0.1 — 0.1 V VI = VT+, VT– IOL = 20 µA
output voltage — — 0.44 — 0.53 VCC = 4.5 V IOL = 24 mA
QA to QP — — 0.73 — 0.94 IOL = 40 mA
(Note)
Switching Characteristics
(VCC = 5 V)
Limits
Ta = 25°C Ta = −40 to +85°C
Item Symbol Min Typ Max Min Max Unit Conditions
Maximum clock frequency fmax 5 — — 4 — MHz CL = 50 pF
Low-level to high-level and tPLH — — 100 — 130 ns RL = 1 kΩ
(Note 2)
high-level to low-level tPHL — — 100 — 130 ns
output propagation time
(CKS-SQP)
High-level to low-level tPHL — — 100 — 130 ns
output propagation time (R-
SQP)
Low-level to high-level tPLZ — — 150 — 200 ns
output propagation time (R-
QA to QP)
Low-level to high-level and tPZL — — 100 — 130 ns
high-level to low-level tPLZ — — 150 — 200 ns
output propagation time
(CKL-QA to QP)
Output enable time to low- tPZL — — 100 — 130 ns
level and high-level (OE−QA tPLZ — — 150 — 200 ns
to QP)
Input Capacitance CI — — 10 — 10 pF
Output Capacitance CO — — 15 — 15 pF OE = VCC
Power dissipation CPD — 5 — — — pF
(Note 1)
Capacitance
Note: 1. CPD is the internal capacitance of the IC calculated from operation supply current under no-load conditions.
(per latch)
The power dissipated during operation under no-load conditions is calculated using the following formula:
PD = CPD • VCC • fI + ICC • VCC
2
Timing Requirements
(VCC = 5 V)
Limits
Ta = 25°C Ta = −40 to +85°C
Item Symbol Min Typ Max Min Max Unit Conditions
CKS, CKL, R pulse width (Note 2)
tw 100 — — 130 — ns
A setup time with respect to tsu 100 — — 130 — ns
CKS
CKS setup time with respect tsu 100 — — 130 — ns
to CKL
A hold time with respect to th 10 — — 15 — ns
CKS
R, recovery time with trec 50 — — 70 — ns
respect to CKS, CKL
QA to QP
PG DUT SQP
CL
50 Ω
GND CL
(1) The pulse generator (PG) has the following characteristics (10% to 90%): tr = 6 ns, tf = 6 ns
(2) The capacitance CL includes stray wiring capacitance and the probe input capacitance.
Typical Characteristics
IOL (mA)
30 30 (15)
(16)
Timing Chart
tw
VCC VCC
50% 50% 50% 50%
CKS CKL
GND GND
tPLH tPHL tPZL
VOH
SQP 50% 50% 50%
QA to QP VOL
VOL
tPLZ
tw
VCC QA to QP
10%
R 50% 50% VOL
trec GND
VCC VCC
CKS 50% A 50% 50%
GND GND
tPHL
tsu th
VOH
SQP 50% VCC
VOL 50%
tPLZ CKS
GND
QA to QP
10%
VOL
VCC
VCC CKS 50%
GND
OE 50% 50%
tsu tw
GND
tPZL tPLZ
VCC
50% 50%
QA to QP 50% CKL
10% GND
VOL
Package Dimensions
JEITA Package Code RENESAS Code Previous Code MASS[Typ.]
P-DIP24-6.3x29.2-2.54 PRDP0024AA-A 24P4D 1.6g
24 13
e1
E
*1
1 12
c
NOTE)
*2 1. DIMENSIONS "*1" AND "*2"
D
DO NOT INCLUDE MOLD FLASH.
2. DIMENSION "*3" DOES NOT
INCLUDE TRIM OFFSET.
A2
Reference Dimension in Millimeters
A
Symbol
Min Nom Max
e1 7.32 7.62 7.92
D 29.0 29.2 29.4
A1
L
24 13
I2
e1
HE
x — — 0.25
L
y — — 0.1
c 0° — 10°
z b2 — 0.76 —
Z1 Detail G Detail F e1 — 7.62 —
I2 1.27 — —